clk/sunxi-ng/ccu_nkm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
0004  */
0005
0006 #ifndef _CCU_NKM_H_
0007 #define _CCU_NKM_H_
0008
0009 #include <linux/clk-provider.h>
0010
0011 #include "ccu_common.h"
0012 #include "ccu_div.h"
0013 #include "ccu_mult.h"
0014
0015 /*
0016  * struct ccu_nkm - Definition of an N-K-M clock
0017  *
0018  * Clocks based on the formula parent * N * K / M
0019  */
0020 struct ccu_nkm {
0021     u32         enable;
0022     u32         lock;
0023
0024     struct ccu_mult_internal    n;
0025     struct ccu_mult_internal    k;
0026     struct ccu_div_internal     m;
0027     struct ccu_mux_internal mux;
0028
0029     unsigned int        fixed_post_div;
0030
0031     struct ccu_common   common;
0032 };
0033
0034 #define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \
0035                      _nshift, _nwidth,      \
0036                      _kshift, _kwidth,      \
0037                      _mshift, _mwidth,      \
0038                      _muxshift, _muxwidth,      \
0039                      _gate, _lock, _flags)      \
0040     struct ccu_nkm _struct = {                  \
0041         .enable     = _gate,                \
0042         .lock       = _lock,                \
0043         .k      = _SUNXI_CCU_MULT(_kshift, _kwidth),    \
0044         .n      = _SUNXI_CCU_MULT(_nshift, _nwidth),    \
0045         .m      = _SUNXI_CCU_DIV(_mshift, _mwidth), \
0046         .mux        = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
0047         .common     = {                 \
0048             .reg        = _reg,             \
0049             .hw.init    = CLK_HW_INIT_PARENTS(_name,    \
0050                               _parents,     \
0051                               &ccu_nkm_ops, \
0052                               _flags),      \
0053         },                          \
0054     }
0055
0056 #define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
0057                      _nshift, _nwidth,          \
0058                      _kshift, _kwidth,          \
0059                      _mshift, _mwidth,          \
0060                      _gate, _lock, _flags)      \
0061     struct ccu_nkm _struct = {                  \
0062         .enable     = _gate,                \
0063         .lock       = _lock,                \
0064         .k      = _SUNXI_CCU_MULT(_kshift, _kwidth),    \
0065         .n      = _SUNXI_CCU_MULT(_nshift, _nwidth),    \
0066         .m      = _SUNXI_CCU_DIV(_mshift, _mwidth), \
0067         .common     = {                 \
0068             .reg        = _reg,             \
0069             .hw.init    = CLK_HW_INIT(_name,        \
0070                               _parent,      \
0071                               &ccu_nkm_ops, \
0072                               _flags),      \
0073         },                          \
0074     }
0075
0076 static inline struct ccu_nkm *hw_to_ccu_nkm(struct clk_hw *hw)
0077 {
0078     struct ccu_common *common = hw_to_ccu_common(hw);
0079
0080     return container_of(common, struct ccu_nkm, common);
0081 }
0082
0083 extern const struct clk_ops ccu_nkm_ops;
0084
0085 #endif /* _CCU_NKM_H_ */