clk/sunxi-ng/ccu_mux.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2016 Maxime Ripard
0004  * Maxime Ripard <maxime.ripard@free-electrons.com>
0005  */
0006
0007 #include <linux/clk.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/delay.h>
0010 #include <linux/io.h>
0011
0012 #include "ccu_gate.h"
0013 #include "ccu_mux.h"
0014
0015 #define CCU_MUX_KEY_VALUE       0x16aa0000
0016
0017 static u16 ccu_mux_get_prediv(struct ccu_common *common,
0018                   struct ccu_mux_internal *cm,
0019                   int parent_index)
0020 {
0021     u16 prediv = 1;
0022     u32 reg;
0023
0024     if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
0025           (common->features & CCU_FEATURE_VARIABLE_PREDIV) ||
0026           (common->features & CCU_FEATURE_ALL_PREDIV)))
0027         return 1;
0028
0029     if (common->features & CCU_FEATURE_ALL_PREDIV)
0030         return common->prediv;
0031
0032     reg = readl(common->base + common->reg);
0033     if (parent_index < 0) {
0034         parent_index = reg >> cm->shift;
0035         parent_index &= (1 << cm->width) - 1;
0036     }
0037
0038     if (common->features & CCU_FEATURE_FIXED_PREDIV) {
0039         int i;
0040
0041         for (i = 0; i < cm->n_predivs; i++)
0042             if (parent_index == cm->fixed_predivs[i].index)
0043                 prediv = cm->fixed_predivs[i].div;
0044     }
0045
0046     if (common->features & CCU_FEATURE_VARIABLE_PREDIV) {
0047         int i;
0048
0049         for (i = 0; i < cm->n_var_predivs; i++)
0050             if (parent_index == cm->var_predivs[i].index) {
0051                 u8 div;
0052
0053                 div = reg >> cm->var_predivs[i].shift;
0054                 div &= (1 << cm->var_predivs[i].width) - 1;
0055                 prediv = div + 1;
0056             }
0057     }
0058
0059     return prediv;
0060 }
0061
0062 unsigned long ccu_mux_helper_apply_prediv(struct ccu_common *common,
0063                       struct ccu_mux_internal *cm,
0064                       int parent_index,
0065                       unsigned long parent_rate)
0066 {
0067     return parent_rate / ccu_mux_get_prediv(common, cm, parent_index);
0068 }
0069 EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_apply_prediv, SUNXI_CCU);
0070
0071 static unsigned long ccu_mux_helper_unapply_prediv(struct ccu_common *common,
0072                         struct ccu_mux_internal *cm,
0073                         int parent_index,
0074                         unsigned long parent_rate)
0075 {
0076     return parent_rate * ccu_mux_get_prediv(common, cm, parent_index);
0077 }
0078
0079 int ccu_mux_helper_determine_rate(struct ccu_common *common,
0080                   struct ccu_mux_internal *cm,
0081                   struct clk_rate_request *req,
0082                   unsigned long (*round)(struct ccu_mux_internal *,
0083                              struct clk_hw *,
0084                              unsigned long *,
0085                              unsigned long,
0086                              void *),
0087                   void *data)
0088 {
0089     unsigned long best_parent_rate = 0, best_rate = 0;
0090     struct clk_hw *best_parent, *hw = &common->hw;
0091     unsigned int i;
0092
0093     if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
0094         unsigned long adj_parent_rate;
0095
0096         best_parent = clk_hw_get_parent(hw);
0097         best_parent_rate = clk_hw_get_rate(best_parent);
0098         adj_parent_rate = ccu_mux_helper_apply_prediv(common, cm, -1,
0099                                   best_parent_rate);
0100
0101         best_rate = round(cm, best_parent, &adj_parent_rate,
0102                   req->rate, data);
0103
0104         /*
0105          * adj_parent_rate might have been modified by our clock.
0106          * Unapply the pre-divider if there's one, and give
0107          * the actual frequency the parent needs to run at.
0108          */
0109         best_parent_rate = ccu_mux_helper_unapply_prediv(common, cm, -1,
0110                                  adj_parent_rate);
0111
0112         goto out;
0113     }
0114
0115     for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
0116         unsigned long tmp_rate, parent_rate;
0117         struct clk_hw *parent;
0118
0119         parent = clk_hw_get_parent_by_index(hw, i);
0120         if (!parent)
0121             continue;
0122
0123         parent_rate = ccu_mux_helper_apply_prediv(common, cm, i,
0124                               clk_hw_get_rate(parent));
0125
0126         tmp_rate = round(cm, parent, &parent_rate, req->rate, data);
0127
0128         /*
0129          * parent_rate might have been modified by our clock.
0130          * Unapply the pre-divider if there's one, and give
0131          * the actual frequency the parent needs to run at.
0132          */
0133         parent_rate = ccu_mux_helper_unapply_prediv(common, cm, i,
0134                                 parent_rate);
0135         if (tmp_rate == req->rate) {
0136             best_parent = parent;
0137             best_parent_rate = parent_rate;
0138             best_rate = tmp_rate;
0139             goto out;
0140         }
0141
0142         if ((req->rate - tmp_rate) < (req->rate - best_rate)) {
0143             best_rate = tmp_rate;
0144             best_parent_rate = parent_rate;
0145             best_parent = parent;
0146         }
0147     }
0148
0149     if (best_rate == 0)
0150         return -EINVAL;
0151
0152 out:
0153     req->best_parent_hw = best_parent;
0154     req->best_parent_rate = best_parent_rate;
0155     req->rate = best_rate;
0156     return 0;
0157 }
0158 EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_determine_rate, SUNXI_CCU);
0159
0160 u8 ccu_mux_helper_get_parent(struct ccu_common *common,
0161                  struct ccu_mux_internal *cm)
0162 {
0163     u32 reg;
0164     u8 parent;
0165
0166     reg = readl(common->base + common->reg);
0167     parent = reg >> cm->shift;
0168     parent &= (1 << cm->width) - 1;
0169
0170     if (cm->table) {
0171         int num_parents = clk_hw_get_num_parents(&common->hw);
0172         int i;
0173
0174         for (i = 0; i < num_parents; i++)
0175             if (cm->table[i] == parent)
0176                 return i;
0177     }
0178
0179     return parent;
0180 }
0181 EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_get_parent, SUNXI_CCU);
0182
0183 int ccu_mux_helper_set_parent(struct ccu_common *common,
0184                   struct ccu_mux_internal *cm,
0185                   u8 index)
0186 {
0187     unsigned long flags;
0188     u32 reg;
0189
0190     if (cm->table)
0191         index = cm->table[index];
0192
0193     spin_lock_irqsave(common->lock, flags);
0194
0195     reg = readl(common->base + common->reg);
0196
0197     /* The key field always reads as zero. */
0198     if (common->features & CCU_FEATURE_KEY_FIELD)
0199         reg |= CCU_MUX_KEY_VALUE;
0200
0201     reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift);
0202     writel(reg | (index << cm->shift), common->base + common->reg);
0203
0204     spin_unlock_irqrestore(common->lock, flags);
0205
0206     return 0;
0207 }
0208 EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_set_parent, SUNXI_CCU);
0209
0210 static void ccu_mux_disable(struct clk_hw *hw)
0211 {
0212     struct ccu_mux *cm = hw_to_ccu_mux(hw);
0213
0214     return ccu_gate_helper_disable(&cm->common, cm->enable);
0215 }
0216
0217 static int ccu_mux_enable(struct clk_hw *hw)
0218 {
0219     struct ccu_mux *cm = hw_to_ccu_mux(hw);
0220
0221     return ccu_gate_helper_enable(&cm->common, cm->enable);
0222 }
0223
0224 static int ccu_mux_is_enabled(struct clk_hw *hw)
0225 {
0226     struct ccu_mux *cm = hw_to_ccu_mux(hw);
0227
0228     return ccu_gate_helper_is_enabled(&cm->common, cm->enable);
0229 }
0230
0231 static u8 ccu_mux_get_parent(struct clk_hw *hw)
0232 {
0233     struct ccu_mux *cm = hw_to_ccu_mux(hw);
0234
0235     return ccu_mux_helper_get_parent(&cm->common, &cm->mux);
0236 }
0237
0238 static int ccu_mux_set_parent(struct clk_hw *hw, u8 index)
0239 {
0240     struct ccu_mux *cm = hw_to_ccu_mux(hw);
0241
0242     return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index);
0243 }
0244
0245 static unsigned long ccu_mux_recalc_rate(struct clk_hw *hw,
0246                      unsigned long parent_rate)
0247 {
0248     struct ccu_mux *cm = hw_to_ccu_mux(hw);
0249
0250     return ccu_mux_helper_apply_prediv(&cm->common, &cm->mux, -1,
0251                        parent_rate);
0252 }
0253
0254 const struct clk_ops ccu_mux_ops = {
0255     .disable    = ccu_mux_disable,
0256     .enable     = ccu_mux_enable,
0257     .is_enabled = ccu_mux_is_enabled,
0258
0259     .get_parent = ccu_mux_get_parent,
0260     .set_parent = ccu_mux_set_parent,
0261
0262     .determine_rate = __clk_mux_determine_rate,
0263     .recalc_rate    = ccu_mux_recalc_rate,
0264 };
0265 EXPORT_SYMBOL_NS_GPL(ccu_mux_ops, SUNXI_CCU);
0266
0267 /*
0268  * This clock notifier is called when the frequency of the of the parent
0269  * PLL clock is to be changed. The idea is to switch the parent to a
0270  * stable clock, such as the main oscillator, while the PLL frequency
0271  * stabilizes.
0272  */
0273 static int ccu_mux_notifier_cb(struct notifier_block *nb,
0274                    unsigned long event, void *data)
0275 {
0276     struct ccu_mux_nb *mux = to_ccu_mux_nb(nb);
0277     int ret = 0;
0278
0279     if (event == PRE_RATE_CHANGE) {
0280         mux->original_index = ccu_mux_helper_get_parent(mux->common,
0281                                 mux->cm);
0282         ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
0283                         mux->bypass_index);
0284     } else if (event == POST_RATE_CHANGE) {
0285         ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
0286                         mux->original_index);
0287     }
0288
0289     udelay(mux->delay_us);
0290
0291     return notifier_from_errno(ret);
0292 }
0293
0294 int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb)
0295 {
0296     mux_nb->clk_nb.notifier_call = ccu_mux_notifier_cb;
0297
0298     return clk_notifier_register(clk, &mux_nb->clk_nb);
0299 }
0300 EXPORT_SYMBOL_NS_GPL(ccu_mux_notifier_register, SUNXI_CCU);