clk/sunxi-ng/ccu-suniv-f1c100s.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
0004  *
0005  */
0006
0007 #ifndef _CCU_SUNIV_F1C100S_H_
0008 #define _CCU_SUNIV_F1C100S_H_
0009
0010 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
0011 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
0012
0013 #define CLK_PLL_CPU     0
0014 #define CLK_PLL_AUDIO_BASE  1
0015 #define CLK_PLL_AUDIO       2
0016 #define CLK_PLL_AUDIO_2X    3
0017 #define CLK_PLL_AUDIO_4X    4
0018 #define CLK_PLL_AUDIO_8X    5
0019 #define CLK_PLL_VIDEO       6
0020 #define CLK_PLL_VIDEO_2X    7
0021 #define CLK_PLL_VE      8
0022 #define CLK_PLL_DDR0        9
0023 #define CLK_PLL_PERIPH      10
0024
0025 /* CPU clock is exported */
0026
0027 #define CLK_AHB         12
0028 #define CLK_APB         13
0029
0030 /* All bus gates, DRAM gates and mod clocks are exported */
0031
0032 #define CLK_NUMBER      (CLK_AVS + 1)
0033
0034 #endif /* _CCU_SUNIV_F1C100S_H_ */