clk/sunxi-ng/ccu-sun9i-a80.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2016 Chen-Yu Tsai
0004  *
0005  * Chen-Yu Tsai <wens@csie.org>
0006  */
0007
0008 #ifndef _CCU_SUN9I_A80_H_
0009 #define _CCU_SUN9I_A80_H_
0010
0011 #include <dt-bindings/clock/sun9i-a80-ccu.h>
0012 #include <dt-bindings/reset/sun9i-a80-ccu.h>
0013
0014 #define CLK_PLL_C0CPUX      0
0015 #define CLK_PLL_C1CPUX      1
0016
0017 /* pll-audio and pll-periph0 are exported to the PRCM block */
0018
0019 #define CLK_PLL_VE      4
0020 #define CLK_PLL_DDR     5
0021 #define CLK_PLL_VIDEO0      6
0022 #define CLK_PLL_VIDEO1      7
0023 #define CLK_PLL_GPU     8
0024 #define CLK_PLL_DE      9
0025 #define CLK_PLL_ISP     10
0026 #define CLK_PLL_PERIPH1     11
0027
0028 /* The CPUX clocks are exported */
0029
0030 #define CLK_ATB0        14
0031 #define CLK_AXI0        15
0032 #define CLK_ATB1        16
0033 #define CLK_AXI1        17
0034 #define CLK_GTBUS       18
0035 #define CLK_AHB0        19
0036 #define CLK_AHB1        20
0037 #define CLK_AHB2        21
0038 #define CLK_APB0        22
0039 #define CLK_APB1        23
0040 #define CLK_CCI400      24
0041 #define CLK_ATS         25
0042 #define CLK_TRACE       26
0043
0044 /* module clocks and bus gates exported */
0045
0046 #define CLK_NUMBER      (CLK_BUS_UART5 + 1)
0047
0048 #endif /* _CCU_SUN9I_A80_H_ */