clk/sunxi-ng/ccu-sun9i-a80-usb.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010
0011 #include "ccu_common.h"
0012 #include "ccu_gate.h"
0013 #include "ccu_reset.h"
0014
0015 #include "ccu-sun9i-a80-usb.h"
0016
0017 static const struct clk_parent_data clk_parent_hosc[] = {
0018     { .fw_name = "hosc" },
0019 };
0020
0021 static const struct clk_parent_data clk_parent_bus[] = {
0022     { .fw_name = "bus" },
0023 };
0024
0025 static SUNXI_CCU_GATE_DATA(bus_hci0_clk, "bus-hci0", clk_parent_bus, 0x0, BIT(1), 0);
0026 static SUNXI_CCU_GATE_DATA(usb_ohci0_clk, "usb-ohci0", clk_parent_hosc, 0x0, BIT(2), 0);
0027 static SUNXI_CCU_GATE_DATA(bus_hci1_clk, "bus-hci1", clk_parent_bus, 0x0, BIT(3), 0);
0028 static SUNXI_CCU_GATE_DATA(bus_hci2_clk, "bus-hci2", clk_parent_bus, 0x0, BIT(5), 0);
0029 static SUNXI_CCU_GATE_DATA(usb_ohci2_clk, "usb-ohci2", clk_parent_hosc, 0x0, BIT(6), 0);
0030
0031 static SUNXI_CCU_GATE_DATA(usb0_phy_clk, "usb0-phy", clk_parent_hosc, 0x4, BIT(1), 0);
0032 static SUNXI_CCU_GATE_DATA(usb1_hsic_clk, "usb1-hsic", clk_parent_hosc, 0x4, BIT(2), 0);
0033 static SUNXI_CCU_GATE_DATA(usb1_phy_clk, "usb1-phy", clk_parent_hosc, 0x4, BIT(3), 0);
0034 static SUNXI_CCU_GATE_DATA(usb2_hsic_clk, "usb2-hsic", clk_parent_hosc, 0x4, BIT(4), 0);
0035 static SUNXI_CCU_GATE_DATA(usb2_phy_clk, "usb2-phy", clk_parent_hosc, 0x4, BIT(5), 0);
0036 static SUNXI_CCU_GATE_DATA(usb_hsic_clk, "usb-hsic", clk_parent_hosc, 0x4, BIT(10), 0);
0037
0038 static struct ccu_common *sun9i_a80_usb_clks[] = {
0039     &bus_hci0_clk.common,
0040     &usb_ohci0_clk.common,
0041     &bus_hci1_clk.common,
0042     &bus_hci2_clk.common,
0043     &usb_ohci2_clk.common,
0044
0045     &usb0_phy_clk.common,
0046     &usb1_hsic_clk.common,
0047     &usb1_phy_clk.common,
0048     &usb2_hsic_clk.common,
0049     &usb2_phy_clk.common,
0050     &usb_hsic_clk.common,
0051 };
0052
0053 static struct clk_hw_onecell_data sun9i_a80_usb_hw_clks = {
0054     .hws    = {
0055         [CLK_BUS_HCI0]  = &bus_hci0_clk.common.hw,
0056         [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
0057         [CLK_BUS_HCI1]  = &bus_hci1_clk.common.hw,
0058         [CLK_BUS_HCI2]  = &bus_hci2_clk.common.hw,
0059         [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
0060
0061         [CLK_USB0_PHY]  = &usb0_phy_clk.common.hw,
0062         [CLK_USB1_HSIC] = &usb1_hsic_clk.common.hw,
0063         [CLK_USB1_PHY]  = &usb1_phy_clk.common.hw,
0064         [CLK_USB2_HSIC] = &usb2_hsic_clk.common.hw,
0065         [CLK_USB2_PHY]  = &usb2_phy_clk.common.hw,
0066         [CLK_USB_HSIC]  = &usb_hsic_clk.common.hw,
0067     },
0068     .num    = CLK_NUMBER,
0069 };
0070
0071 static struct ccu_reset_map sun9i_a80_usb_resets[] = {
0072     [RST_USB0_HCI]      = { 0x0, BIT(17) },
0073     [RST_USB1_HCI]      = { 0x0, BIT(18) },
0074     [RST_USB2_HCI]      = { 0x0, BIT(19) },
0075
0076     [RST_USB0_PHY]      = { 0x4, BIT(17) },
0077     [RST_USB1_HSIC]     = { 0x4, BIT(18) },
0078     [RST_USB1_PHY]      = { 0x4, BIT(19) },
0079     [RST_USB2_HSIC]     = { 0x4, BIT(20) },
0080     [RST_USB2_PHY]      = { 0x4, BIT(21) },
0081 };
0082
0083 static const struct sunxi_ccu_desc sun9i_a80_usb_clk_desc = {
0084     .ccu_clks   = sun9i_a80_usb_clks,
0085     .num_ccu_clks   = ARRAY_SIZE(sun9i_a80_usb_clks),
0086
0087     .hw_clks    = &sun9i_a80_usb_hw_clks,
0088
0089     .resets     = sun9i_a80_usb_resets,
0090     .num_resets = ARRAY_SIZE(sun9i_a80_usb_resets),
0091 };
0092
0093 static int sun9i_a80_usb_clk_probe(struct platform_device *pdev)
0094 {
0095     struct clk *bus_clk;
0096     void __iomem *reg;
0097     int ret;
0098
0099     reg = devm_platform_ioremap_resource(pdev, 0);
0100     if (IS_ERR(reg))
0101         return PTR_ERR(reg);
0102
0103     bus_clk = devm_clk_get(&pdev->dev, "bus");
0104     if (IS_ERR(bus_clk)) {
0105         ret = PTR_ERR(bus_clk);
0106         if (ret != -EPROBE_DEFER)
0107             dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
0108         return ret;
0109     }
0110
0111     /* The bus clock needs to be enabled for us to access the registers */
0112     ret = clk_prepare_enable(bus_clk);
0113     if (ret) {
0114         dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
0115         return ret;
0116     }
0117
0118     ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun9i_a80_usb_clk_desc);
0119     if (ret)
0120         goto err_disable_clk;
0121
0122     return 0;
0123
0124 err_disable_clk:
0125     clk_disable_unprepare(bus_clk);
0126     return ret;
0127 }
0128
0129 static const struct of_device_id sun9i_a80_usb_clk_ids[] = {
0130     { .compatible = "allwinner,sun9i-a80-usb-clks" },
0131     { }
0132 };
0133
0134 static struct platform_driver sun9i_a80_usb_clk_driver = {
0135     .probe  = sun9i_a80_usb_clk_probe,
0136     .driver = {
0137         .name   = "sun9i-a80-usb-clks",
0138         .of_match_table = sun9i_a80_usb_clk_ids,
0139     },
0140 };
0141 module_platform_driver(sun9i_a80_usb_clk_driver);
0142
0143 MODULE_IMPORT_NS(SUNXI_CCU);
0144 MODULE_LICENSE("GPL");