clk/sunxi-ng/ccu-sun8i-v3s.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
0004  *
0005  * Based on ccu-sun8i-h3.h, which is:
0006  * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
0007  */
0008
0009 #ifndef _CCU_SUN8I_H3_H_
0010 #define _CCU_SUN8I_H3_H_
0011
0012 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
0013 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
0014
0015 #define CLK_PLL_CPU     0
0016 #define CLK_PLL_AUDIO_BASE  1
0017 #define CLK_PLL_AUDIO       2
0018 #define CLK_PLL_AUDIO_2X    3
0019 #define CLK_PLL_AUDIO_4X    4
0020 #define CLK_PLL_AUDIO_8X    5
0021 #define CLK_PLL_VIDEO       6
0022 #define CLK_PLL_VE      7
0023 #define CLK_PLL_DDR0        8
0024 #define CLK_PLL_PERIPH0     9
0025 #define CLK_PLL_PERIPH0_2X  10
0026 #define CLK_PLL_ISP     11
0027 #define CLK_PLL_PERIPH1     12
0028 /* Reserve one number for not implemented and not used PLL_DDR1 */
0029
0030 /* The CPU clock is exported */
0031
0032 #define CLK_AXI         15
0033 #define CLK_AHB1        16
0034 #define CLK_APB1        17
0035 #define CLK_APB2        18
0036 #define CLK_AHB2        19
0037
0038 /* All the bus gates are exported */
0039
0040 /* The first bunch of module clocks are exported */
0041
0042 #define CLK_DRAM        58
0043
0044 /* All the DRAM gates are exported */
0045
0046 /* Some more module clocks are exported */
0047
0048 #define CLK_MBUS        72
0049
0050 /* And the GPU module clock is exported */
0051
0052 #define CLK_PLL_DDR1        74
0053
0054 #endif /* _CCU_SUN8I_H3_H_ */