clk/sunxi-ng/ccu-sun8i-r40.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
0004  */
0005
0006 #ifndef _CCU_SUN8I_R40_H_
0007 #define _CCU_SUN8I_R40_H_
0008
0009 #include <dt-bindings/clock/sun8i-r40-ccu.h>
0010 #include <dt-bindings/reset/sun8i-r40-ccu.h>
0011
0012 #define CLK_OSC_12M     0
0013 #define CLK_PLL_CPU     1
0014 #define CLK_PLL_AUDIO_BASE  2
0015 #define CLK_PLL_AUDIO       3
0016 #define CLK_PLL_AUDIO_2X    4
0017 #define CLK_PLL_AUDIO_4X    5
0018 #define CLK_PLL_AUDIO_8X    6
0019
0020 /* PLL_VIDEO0 is exported */
0021
0022 #define CLK_PLL_VIDEO0_2X   8
0023 #define CLK_PLL_VE      9
0024 #define CLK_PLL_DDR0        10
0025 #define CLK_PLL_PERIPH0     11
0026 #define CLK_PLL_PERIPH0_SATA    12
0027 #define CLK_PLL_PERIPH0_2X  13
0028 #define CLK_PLL_PERIPH1     14
0029 #define CLK_PLL_PERIPH1_2X  15
0030
0031 /* PLL_VIDEO1 is exported */
0032
0033 #define CLK_PLL_VIDEO1_2X   17
0034 #define CLK_PLL_SATA        18
0035 #define CLK_PLL_SATA_OUT    19
0036 #define CLK_PLL_GPU     20
0037 #define CLK_PLL_MIPI        21
0038 #define CLK_PLL_DE      22
0039 #define CLK_PLL_DDR1        23
0040
0041 /* The CPU clock is exported */
0042
0043 #define CLK_AXI         25
0044 #define CLK_AHB1        26
0045 #define CLK_APB1        27
0046 #define CLK_APB2        28
0047
0048 /* All the bus gates are exported */
0049
0050 /* The first bunch of module clocks are exported */
0051
0052 #define CLK_DRAM        132
0053
0054 /* All the DRAM gates are exported */
0055
0056 /* Some more module clocks are exported */
0057
0058 #define CLK_NUMBER      (CLK_OUTB + 1)
0059
0060 #endif /* _CCU_SUN8I_R40_H_ */