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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
0004  */
0005 
0006 #include <linux/clk-provider.h>
0007 #include <linux/io.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/regmap.h>
0011 
0012 #include "ccu_common.h"
0013 #include "ccu_reset.h"
0014 
0015 #include "ccu_div.h"
0016 #include "ccu_gate.h"
0017 #include "ccu_mp.h"
0018 #include "ccu_mult.h"
0019 #include "ccu_nk.h"
0020 #include "ccu_nkm.h"
0021 #include "ccu_nkmp.h"
0022 #include "ccu_nm.h"
0023 #include "ccu_phase.h"
0024 
0025 #include "ccu-sun8i-r40.h"
0026 
0027 /* TODO: The result of N*K is required to be in [10, 88] range. */
0028 static struct ccu_nkmp pll_cpu_clk = {
0029     .enable     = BIT(31),
0030     .lock       = BIT(28),
0031     .n      = _SUNXI_CCU_MULT(8, 5),
0032     .k      = _SUNXI_CCU_MULT(4, 2),
0033     .m      = _SUNXI_CCU_DIV(0, 2),
0034     .p      = _SUNXI_CCU_DIV_MAX(16, 2, 4),
0035     .common     = {
0036         .reg        = 0x000,
0037         .hw.init    = CLK_HW_INIT("pll-cpu",
0038                           "osc24M",
0039                           &ccu_nkmp_ops,
0040                           CLK_SET_RATE_UNGATE),
0041     },
0042 };
0043 
0044 /*
0045  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
0046  * the base (2x, 4x and 8x), and one variable divider (the one true
0047  * pll audio).
0048  *
0049  * With sigma-delta modulation for fractional-N on the audio PLL,
0050  * we have to use specific dividers. This means the variable divider
0051  * can no longer be used, as the audio codec requests the exact clock
0052  * rates we support through this mechanism. So we now hard code the
0053  * variable divider to 1. This means the clock rates will no longer
0054  * match the clock names.
0055  */
0056 #define SUN8I_R40_PLL_AUDIO_REG 0x008
0057 
0058 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
0059     { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
0060     { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
0061 };
0062 
0063 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
0064                        "osc24M", 0x008,
0065                        8, 7,    /* N */
0066                        0, 5,    /* M */
0067                        pll_audio_sdm_table, BIT(24),
0068                        0x284, BIT(31),
0069                        BIT(31), /* gate */
0070                        BIT(28), /* lock */
0071                        CLK_SET_RATE_UNGATE);
0072 
0073 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
0074                         "osc24M", 0x0010,
0075                         192000000,  /* Minimum rate */
0076                         1008000000, /* Maximum rate */
0077                         8, 7,       /* N */
0078                         0, 4,       /* M */
0079                         BIT(24),    /* frac enable */
0080                         BIT(25),    /* frac select */
0081                         270000000,  /* frac rate 0 */
0082                         297000000,  /* frac rate 1 */
0083                         BIT(31),    /* gate */
0084                         BIT(28),    /* lock */
0085                         CLK_SET_RATE_UNGATE);
0086 
0087 /* TODO: The result of N/M is required to be in [8, 25] range. */
0088 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
0089                     "osc24M", 0x0018,
0090                     8, 7,       /* N */
0091                     0, 4,       /* M */
0092                     BIT(24),    /* frac enable */
0093                     BIT(25),    /* frac select */
0094                     270000000,  /* frac rate 0 */
0095                     297000000,  /* frac rate 1 */
0096                     BIT(31),    /* gate */
0097                     BIT(28),    /* lock */
0098                     CLK_SET_RATE_UNGATE);
0099 
0100 /* TODO: The result of N*K is required to be in [10, 77] range. */
0101 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
0102                     "osc24M", 0x020,
0103                     8, 5,   /* N */
0104                     4, 2,   /* K */
0105                     0, 2,   /* M */
0106                     BIT(31),    /* gate */
0107                     BIT(28),    /* lock */
0108                     CLK_SET_RATE_UNGATE);
0109 
0110 /* TODO: The result of N*K is required to be in [21, 58] range. */
0111 static struct ccu_nk pll_periph0_clk = {
0112     .enable     = BIT(31),
0113     .lock       = BIT(28),
0114     .n      = _SUNXI_CCU_MULT(8, 5),
0115     .k      = _SUNXI_CCU_MULT(4, 2),
0116     .fixed_post_div = 2,
0117     .common     = {
0118         .reg        = 0x028,
0119         .features   = CCU_FEATURE_FIXED_POSTDIV,
0120         .hw.init    = CLK_HW_INIT("pll-periph0", "osc24M",
0121                           &ccu_nk_ops,
0122                           CLK_SET_RATE_UNGATE),
0123     },
0124 };
0125 
0126 static struct ccu_div pll_periph0_sata_clk = {
0127     .enable     = BIT(24),
0128     .div        = _SUNXI_CCU_DIV(0, 2),
0129     /*
0130      * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
0131      * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
0132      * 6/2 = 3.
0133      */
0134     .fixed_post_div = 3,
0135     .common     = {
0136         .reg        = 0x028,
0137         .features   = CCU_FEATURE_FIXED_POSTDIV,
0138         .hw.init    = CLK_HW_INIT("pll-periph0-sata",
0139                           "pll-periph0",
0140                           &ccu_div_ops, 0),
0141     },
0142 };
0143 
0144 /* TODO: The result of N*K is required to be in [21, 58] range. */
0145 static struct ccu_nk pll_periph1_clk = {
0146     .enable     = BIT(31),
0147     .lock       = BIT(28),
0148     .n      = _SUNXI_CCU_MULT(8, 5),
0149     .k      = _SUNXI_CCU_MULT(4, 2),
0150     .fixed_post_div = 2,
0151     .common     = {
0152         .reg        = 0x02c,
0153         .features   = CCU_FEATURE_FIXED_POSTDIV,
0154         .hw.init    = CLK_HW_INIT("pll-periph1", "osc24M",
0155                           &ccu_nk_ops,
0156                           CLK_SET_RATE_UNGATE),
0157     },
0158 };
0159 
0160 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
0161                         "osc24M", 0x030,
0162                         192000000,  /* Minimum rate */
0163                         1008000000, /* Maximum rate */
0164                         8, 7,       /* N */
0165                         0, 4,       /* M */
0166                         BIT(24),    /* frac enable */
0167                         BIT(25),    /* frac select */
0168                         270000000,  /* frac rate 0 */
0169                         297000000,  /* frac rate 1 */
0170                         BIT(31),    /* gate */
0171                         BIT(28),    /* lock */
0172                         CLK_SET_RATE_UNGATE);
0173 
0174 static struct ccu_nkm pll_sata_clk = {
0175     .enable     = BIT(31),
0176     .lock       = BIT(28),
0177     .n      = _SUNXI_CCU_MULT(8, 5),
0178     .k      = _SUNXI_CCU_MULT(4, 2),
0179     .m      = _SUNXI_CCU_DIV(0, 2),
0180     .fixed_post_div = 6,
0181     .common     = {
0182         .reg        = 0x034,
0183         .features   = CCU_FEATURE_FIXED_POSTDIV,
0184         .hw.init    = CLK_HW_INIT("pll-sata", "osc24M",
0185                           &ccu_nkm_ops,
0186                           CLK_SET_RATE_UNGATE),
0187     },
0188 };
0189 
0190 static const char * const pll_sata_out_parents[] = { "pll-sata",
0191                              "pll-periph0-sata" };
0192 static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
0193                    pll_sata_out_parents, 0x034,
0194                    30, 1,   /* mux */
0195                    BIT(14), /* gate */
0196                    CLK_SET_RATE_PARENT);
0197 
0198 /* TODO: The result of N/M is required to be in [8, 25] range. */
0199 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
0200                     "osc24M", 0x038,
0201                     8, 7,       /* N */
0202                     0, 4,       /* M */
0203                     BIT(24),    /* frac enable */
0204                     BIT(25),    /* frac select */
0205                     270000000,  /* frac rate 0 */
0206                     297000000,  /* frac rate 1 */
0207                     BIT(31),    /* gate */
0208                     BIT(28),    /* lock */
0209                     CLK_SET_RATE_UNGATE);
0210 
0211 /*
0212  * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
0213  *
0214  * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
0215  * integer / fractional clock with switchable multipliers and dividers.
0216  * This is not supported here. We hardcode the PLL to MIPI mode.
0217  *
0218  * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3,
0219  * which cannot be implemented now.
0220  */
0221 #define SUN8I_R40_PLL_MIPI_REG  0x040
0222 
0223 static const char * const pll_mipi_parents[] = { "pll-video0" };
0224 static struct ccu_nkm pll_mipi_clk = {
0225     .enable = BIT(31) | BIT(23) | BIT(22),
0226     .lock   = BIT(28),
0227     .n  = _SUNXI_CCU_MULT(8, 4),
0228     .k  = _SUNXI_CCU_MULT_MIN(4, 2, 2),
0229     .m  = _SUNXI_CCU_DIV(0, 4),
0230     .mux    = _SUNXI_CCU_MUX(21, 1),
0231     .common = {
0232         .reg        = 0x040,
0233         .hw.init    = CLK_HW_INIT_PARENTS("pll-mipi",
0234                               pll_mipi_parents,
0235                               &ccu_nkm_ops,
0236                               CLK_SET_RATE_UNGATE)
0237     },
0238 };
0239 
0240 /* TODO: The result of N/M is required to be in [8, 25] range. */
0241 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
0242                     "osc24M", 0x048,
0243                     8, 7,       /* N */
0244                     0, 4,       /* M */
0245                     BIT(24),    /* frac enable */
0246                     BIT(25),    /* frac select */
0247                     270000000,  /* frac rate 0 */
0248                     297000000,  /* frac rate 1 */
0249                     BIT(31),    /* gate */
0250                     BIT(28),    /* lock */
0251                     CLK_SET_RATE_UNGATE);
0252 
0253 /* TODO: The N factor is required to be in [16, 75] range. */
0254 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
0255                    "osc24M", 0x04c,
0256                    8, 7,    /* N */
0257                    0, 2,    /* M */
0258                    BIT(31), /* gate */
0259                    BIT(28), /* lock */
0260                    CLK_SET_RATE_UNGATE);
0261 
0262 static const char * const cpu_parents[] = { "osc32k", "osc24M",
0263                          "pll-cpu", "pll-cpu" };
0264 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
0265              0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
0266 
0267 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
0268 
0269 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
0270                          "axi", "pll-periph0" };
0271 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
0272     { .index = 3, .shift = 6, .width = 2 },
0273 };
0274 static struct ccu_div ahb1_clk = {
0275     .div        = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
0276 
0277     .mux        = {
0278         .shift  = 12,
0279         .width  = 2,
0280 
0281         .var_predivs    = ahb1_predivs,
0282         .n_var_predivs  = ARRAY_SIZE(ahb1_predivs),
0283     },
0284 
0285     .common     = {
0286         .reg        = 0x054,
0287         .features   = CCU_FEATURE_VARIABLE_PREDIV,
0288         .hw.init    = CLK_HW_INIT_PARENTS("ahb1",
0289                               ahb1_parents,
0290                               &ccu_div_ops,
0291                               0),
0292     },
0293 };
0294 
0295 static struct clk_div_table apb1_div_table[] = {
0296     { .val = 0, .div = 2 },
0297     { .val = 1, .div = 2 },
0298     { .val = 2, .div = 4 },
0299     { .val = 3, .div = 8 },
0300     { /* Sentinel */ },
0301 };
0302 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0303                0x054, 8, 2, apb1_div_table, 0);
0304 
0305 static const char * const apb2_parents[] = { "osc32k", "osc24M",
0306                          "pll-periph0-2x",
0307                          "pll-periph0-2x" };
0308 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0309                  0, 5,  /* M */
0310                  16, 2, /* P */
0311                  24, 2, /* mux */
0312                  0);
0313 
0314 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
0315               0x060, BIT(1), 0);
0316 static SUNXI_CCU_GATE(bus_ce_clk,   "bus-ce",   "ahb1",
0317               0x060, BIT(5), 0);
0318 static SUNXI_CCU_GATE(bus_dma_clk,  "bus-dma",  "ahb1",
0319               0x060, BIT(6), 0);
0320 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0321               0x060, BIT(8), 0);
0322 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0323               0x060, BIT(9), 0);
0324 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0325               0x060, BIT(10), 0);
0326 static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
0327               0x060, BIT(11), 0);
0328 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
0329               0x060, BIT(13), 0);
0330 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0331               0x060, BIT(14), 0);
0332 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1",
0333               0x060, BIT(17), 0);
0334 static SUNXI_CCU_GATE(bus_ts_clk,   "bus-ts",   "ahb1",
0335               0x060, BIT(18), 0);
0336 static SUNXI_CCU_GATE(bus_hstimer_clk,  "bus-hstimer",  "ahb1",
0337               0x060, BIT(19), 0);
0338 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0339               0x060, BIT(20), 0);
0340 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
0341               0x060, BIT(21), 0);
0342 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1",
0343               0x060, BIT(22), 0);
0344 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1",
0345               0x060, BIT(23), 0);
0346 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1",
0347               0x060, BIT(24), 0);
0348 static SUNXI_CCU_GATE(bus_otg_clk,  "bus-otg",  "ahb1",
0349               0x060, BIT(25), 0);
0350 static SUNXI_CCU_GATE(bus_ehci0_clk,    "bus-ehci0",    "ahb1",
0351               0x060, BIT(26), 0);
0352 static SUNXI_CCU_GATE(bus_ehci1_clk,    "bus-ehci1",    "ahb1",
0353               0x060, BIT(27), 0);
0354 static SUNXI_CCU_GATE(bus_ehci2_clk,    "bus-ehci2",    "ahb1",
0355               0x060, BIT(28), 0);
0356 static SUNXI_CCU_GATE(bus_ohci0_clk,    "bus-ohci0",    "ahb1",
0357               0x060, BIT(29), 0);
0358 static SUNXI_CCU_GATE(bus_ohci1_clk,    "bus-ohci1",    "ahb1",
0359               0x060, BIT(30), 0);
0360 static SUNXI_CCU_GATE(bus_ohci2_clk,    "bus-ohci2",    "ahb1",
0361               0x060, BIT(31), 0);
0362 
0363 static SUNXI_CCU_GATE(bus_ve_clk,   "bus-ve",   "ahb1",
0364               0x064, BIT(0), 0);
0365 static SUNXI_CCU_GATE(bus_mp_clk,   "bus-mp",   "ahb1",
0366               0x064, BIT(2), 0);
0367 static SUNXI_CCU_GATE(bus_deinterlace_clk,  "bus-deinterlace",  "ahb1",
0368               0x064, BIT(5), 0);
0369 static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1",
0370               0x064, BIT(8), 0);
0371 static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1",
0372               0x064, BIT(9), 0);
0373 static SUNXI_CCU_GATE(bus_hdmi0_clk,    "bus-hdmi0",    "ahb1",
0374               0x064, BIT(10), 0);
0375 static SUNXI_CCU_GATE(bus_hdmi1_clk,    "bus-hdmi1",    "ahb1",
0376               0x064, BIT(11), 0);
0377 static SUNXI_CCU_GATE(bus_de_clk,   "bus-de",   "ahb1",
0378               0x064, BIT(12), 0);
0379 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1",
0380               0x064, BIT(13), 0);
0381 static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1",
0382               0x064, BIT(14), 0);
0383 static SUNXI_CCU_GATE(bus_tve_top_clk,  "bus-tve-top",  "ahb1",
0384               0x064, BIT(15), 0);
0385 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
0386               0x064, BIT(17), 0);
0387 static SUNXI_CCU_GATE(bus_gpu_clk,  "bus-gpu",  "ahb1",
0388               0x064, BIT(20), 0);
0389 static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1",
0390               0x064, BIT(21), 0);
0391 static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1",
0392               0x064, BIT(22), 0);
0393 static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1",
0394               0x064, BIT(23), 0);
0395 static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1",
0396               0x064, BIT(24), 0);
0397 static SUNXI_CCU_GATE(bus_tvd_top_clk,  "bus-tvd-top",  "ahb1",
0398               0x064, BIT(25), 0);
0399 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk,    "bus-tcon-lcd0",    "ahb1",
0400               0x064, BIT(26), 0);
0401 static SUNXI_CCU_GATE(bus_tcon_lcd1_clk,    "bus-tcon-lcd1",    "ahb1",
0402               0x064, BIT(27), 0);
0403 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1",
0404               0x064, BIT(28), 0);
0405 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1",
0406               0x064, BIT(29), 0);
0407 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1",
0408               0x064, BIT(30), 0);
0409 
0410 static SUNXI_CCU_GATE(bus_codec_clk,    "bus-codec",    "apb1",
0411               0x068, BIT(0), 0);
0412 static SUNXI_CCU_GATE(bus_spdif_clk,    "bus-spdif",    "apb1",
0413               0x068, BIT(1), 0);
0414 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1",
0415               0x068, BIT(2), 0);
0416 static SUNXI_CCU_GATE(bus_pio_clk,  "bus-pio",  "apb1",
0417               0x068, BIT(5), 0);
0418 static SUNXI_CCU_GATE(bus_ir0_clk,  "bus-ir0",  "apb1",
0419               0x068, BIT(6), 0);
0420 static SUNXI_CCU_GATE(bus_ir1_clk,  "bus-ir1",  "apb1",
0421               0x068, BIT(7), 0);
0422 static SUNXI_CCU_GATE(bus_ths_clk,  "bus-ths",  "apb1",
0423               0x068, BIT(8), 0);
0424 static SUNXI_CCU_GATE(bus_keypad_clk,   "bus-keypad",   "apb1",
0425               0x068, BIT(10), 0);
0426 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0427               0x068, BIT(12), 0);
0428 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
0429               0x068, BIT(13), 0);
0430 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
0431               0x068, BIT(14), 0);
0432 
0433 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0434               0x06c, BIT(0), 0);
0435 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0436               0x06c, BIT(1), 0);
0437 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0438               0x06c, BIT(2), 0);
0439 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2",
0440               0x06c, BIT(3), 0);
0441 /*
0442  * In datasheet here's "Reserved", however the gate exists in BSP soucre
0443  * code.
0444  */
0445 static SUNXI_CCU_GATE(bus_can_clk,  "bus-can",  "apb2",
0446               0x06c, BIT(4), 0);
0447 static SUNXI_CCU_GATE(bus_scr_clk,  "bus-scr",  "apb2",
0448               0x06c, BIT(5), 0);
0449 static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2",
0450               0x06c, BIT(6), 0);
0451 static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2",
0452               0x06c, BIT(7), 0);
0453 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2",
0454               0x06c, BIT(15), 0);
0455 static SUNXI_CCU_GATE(bus_uart0_clk,    "bus-uart0",    "apb2",
0456               0x06c, BIT(16), 0);
0457 static SUNXI_CCU_GATE(bus_uart1_clk,    "bus-uart1",    "apb2",
0458               0x06c, BIT(17), 0);
0459 static SUNXI_CCU_GATE(bus_uart2_clk,    "bus-uart2",    "apb2",
0460               0x06c, BIT(18), 0);
0461 static SUNXI_CCU_GATE(bus_uart3_clk,    "bus-uart3",    "apb2",
0462               0x06c, BIT(19), 0);
0463 static SUNXI_CCU_GATE(bus_uart4_clk,    "bus-uart4",    "apb2",
0464               0x06c, BIT(20), 0);
0465 static SUNXI_CCU_GATE(bus_uart5_clk,    "bus-uart5",    "apb2",
0466               0x06c, BIT(21), 0);
0467 static SUNXI_CCU_GATE(bus_uart6_clk,    "bus-uart6",    "apb2",
0468               0x06c, BIT(22), 0);
0469 static SUNXI_CCU_GATE(bus_uart7_clk,    "bus-uart7",    "apb2",
0470               0x06c, BIT(23), 0);
0471 
0472 static SUNXI_CCU_GATE(bus_dbg_clk,  "bus-dbg",  "ahb1",
0473               0x070, BIT(7), 0);
0474 
0475 static const char * const ths_parents[] = { "osc24M" };
0476 static struct ccu_div ths_clk = {
0477     .enable = BIT(31),
0478     .div    = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
0479     .mux    = _SUNXI_CCU_MUX(24, 2),
0480     .common = {
0481         .reg        = 0x074,
0482         .hw.init    = CLK_HW_INIT_PARENTS("ths",
0483                               ths_parents,
0484                               &ccu_div_ops,
0485                               0),
0486     },
0487 };
0488 
0489 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
0490                              "pll-periph1" };
0491 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0492                   0, 4,     /* M */
0493                   16, 2,    /* P */
0494                   24, 2,    /* mux */
0495                   BIT(31),  /* gate */
0496                   0);
0497 
0498 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0499                   0, 4,     /* M */
0500                   16, 2,    /* P */
0501                   24, 2,    /* mux */
0502                   BIT(31),  /* gate */
0503                   0);
0504 
0505 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0506                   0, 4,     /* M */
0507                   16, 2,    /* P */
0508                   24, 2,    /* mux */
0509                   BIT(31),  /* gate */
0510                   0);
0511 
0512 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0513                   0, 4,     /* M */
0514                   16, 2,    /* P */
0515                   24, 2,    /* mux */
0516                   BIT(31),  /* gate */
0517                   0);
0518 
0519 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
0520                   0, 4,     /* M */
0521                   16, 2,    /* P */
0522                   24, 2,    /* mux */
0523                   BIT(31),  /* gate */
0524                   0);
0525 
0526 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
0527 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
0528                   0, 4,     /* M */
0529                   16, 2,    /* P */
0530                   24, 4,    /* mux */
0531                   BIT(31),  /* gate */
0532                   0);
0533 
0534 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
0535                        "pll-periph1-2x" };
0536 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
0537                   0, 4,     /* M */
0538                   16, 2,    /* P */
0539                   24, 2,    /* mux */
0540                   BIT(31),  /* gate */
0541                   0);
0542 
0543 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0544                   0, 4,     /* M */
0545                   16, 2,    /* P */
0546                   24, 2,    /* mux */
0547                   BIT(31),  /* gate */
0548                   0);
0549 
0550 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0551                   0, 4,     /* M */
0552                   16, 2,    /* P */
0553                   24, 2,    /* mux */
0554                   BIT(31),  /* gate */
0555                   0);
0556 
0557 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
0558                   0, 4,     /* M */
0559                   16, 2,    /* P */
0560                   24, 2,    /* mux */
0561                   BIT(31),  /* gate */
0562                   0);
0563 
0564 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
0565                   0, 4,     /* M */
0566                   16, 2,    /* P */
0567                   24, 2,    /* mux */
0568                   BIT(31),  /* gate */
0569                   0);
0570 
0571 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
0572                         "pll-audio-2x", "pll-audio" };
0573 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
0574                    0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0575 
0576 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
0577                    0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0578 
0579 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
0580                    0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0581 
0582 static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents,
0583                    0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0584 
0585 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents,
0586                    0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0587 
0588 static const char * const keypad_parents[] = { "osc24M", "osc32k" };
0589 static const u8 keypad_table[] = { 0, 2 };
0590 static struct ccu_mp keypad_clk = {
0591     .enable = BIT(31),
0592     .m  = _SUNXI_CCU_DIV(0, 5),
0593     .p  = _SUNXI_CCU_DIV(16, 2),
0594     .mux    = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
0595     .common = {
0596         .reg        = 0x0c4,
0597         .hw.init    = CLK_HW_INIT_PARENTS("keypad",
0598                               keypad_parents,
0599                               &ccu_mp_ops,
0600                               0),
0601     }
0602 };
0603 
0604 static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
0605 static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
0606                    0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
0607 
0608 /*
0609  * There are 3 OHCI 12M clock source selection bits in this register.
0610  * We will force them to 0 (12M divided from 48M).
0611  */
0612 #define SUN8I_R40_USB_CLK_REG   0x0cc
0613 
0614 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0615               0x0cc, BIT(8), 0);
0616 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0617               0x0cc, BIT(9), 0);
0618 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
0619               0x0cc, BIT(10), 0);
0620 static SUNXI_CCU_GATE(usb_ohci0_clk,    "usb-ohci0",    "osc12M",
0621               0x0cc, BIT(16), 0);
0622 static SUNXI_CCU_GATE(usb_ohci1_clk,    "usb-ohci1",    "osc12M",
0623               0x0cc, BIT(17), 0);
0624 static SUNXI_CCU_GATE(usb_ohci2_clk,    "usb-ohci2",    "osc12M",
0625               0x0cc, BIT(18), 0);
0626 
0627 static const char * const ir_parents[] = { "osc24M", "pll-periph0",
0628                        "pll-periph1", "osc32k" };
0629 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0,
0630                   0, 4,     /* M */
0631                   16, 2,    /* P */
0632                   24, 2,    /* mux */
0633                   BIT(31),  /* gate */
0634                   0);
0635 
0636 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4,
0637                   0, 4,     /* M */
0638                   16, 2,    /* P */
0639                   24, 2,    /* mux */
0640                   BIT(31),  /* gate */
0641                   0);
0642 
0643 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
0644 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
0645                 0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL);
0646 
0647 static SUNXI_CCU_GATE(dram_ve_clk,  "dram-ve",  "dram",
0648               0x100, BIT(0), 0);
0649 static SUNXI_CCU_GATE(dram_csi0_clk,    "dram-csi0",    "dram",
0650               0x100, BIT(1), 0);
0651 static SUNXI_CCU_GATE(dram_csi1_clk,    "dram-csi1",    "dram",
0652               0x100, BIT(2), 0);
0653 static SUNXI_CCU_GATE(dram_ts_clk,  "dram-ts",  "dram",
0654               0x100, BIT(3), 0);
0655 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram",
0656               0x100, BIT(4), 0);
0657 static SUNXI_CCU_GATE(dram_mp_clk,  "dram-mp",  "dram",
0658               0x100, BIT(5), 0);
0659 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
0660               0x100, BIT(6), 0);
0661 
0662 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
0663 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0664                  0x104, 0, 4, 24, 3, BIT(31),
0665                  CLK_SET_RATE_PARENT);
0666 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
0667                  0x108, 0, 4, 24, 3, BIT(31), 0);
0668 
0669 static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
0670                          "pll-video0-2x", "pll-video1-2x",
0671                          "pll-mipi" };
0672 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
0673                    0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
0674 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
0675                    0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
0676 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
0677                  0x118, 0, 4, 24, 3, BIT(31),
0678                  CLK_SET_RATE_PARENT);
0679 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
0680                  0x11c, 0, 4, 24, 3, BIT(31),
0681                  CLK_SET_RATE_PARENT);
0682 
0683 static const char * const deinterlace_parents[] = { "pll-periph0",
0684                             "pll-periph1" };
0685 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
0686                  deinterlace_parents, 0x124, 0, 4, 24, 3,
0687                  BIT(31), 0);
0688 
0689 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
0690                          "pll-periph1" };
0691 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
0692                  0x130, 0, 5, 8, 3, BIT(15), 0);
0693 
0694 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
0695 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
0696                  0x134, 16, 4, 24, 3, BIT(31), 0);
0697 
0698 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
0699                  0x134, 0, 5, 8, 3, BIT(15), 0);
0700 
0701 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0702                  0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
0703 
0704 static SUNXI_CCU_GATE(codec_clk,    "codec",    "pll-audio",
0705               0x140, BIT(31), CLK_SET_RATE_PARENT);
0706 static SUNXI_CCU_GATE(avs_clk,      "avs",      "osc24M",
0707               0x144, BIT(31), 0);
0708 
0709 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
0710 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
0711                  0x150, 0, 4, 24, 2, BIT(31),
0712                  CLK_SET_RATE_PARENT);
0713 
0714 static SUNXI_CCU_GATE(hdmi_slow_clk,    "hdmi-slow",    "osc24M",
0715               0x154, BIT(31), 0);
0716 
0717 /*
0718  * In the SoC's user manual, the P factor is mentioned, but not used in
0719  * the frequency formula.
0720  *
0721  * Here the factor is included, according to the BSP kernel source,
0722  * which contains the P factor of this clock.
0723  */
0724 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
0725                          "pll-ddr0" };
0726 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c,
0727                   0, 4,     /* M */
0728                   16, 2,    /* P */
0729                   24, 2,    /* mux */
0730                   BIT(31),  /* gate */
0731                   CLK_IS_CRITICAL);
0732 
0733 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
0734                          "pll-periph0" };
0735 static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
0736                  0x168, 0, 4, 8, 2, BIT(15), 0);
0737 
0738 static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents,
0739                  0x180, 0, 4, 24, 3, BIT(31), 0);
0740 static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents,
0741                  0x184, 0, 4, 24, 3, BIT(31), 0);
0742 
0743 static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
0744                         "pll-video0-2x", "pll-video1-2x" };
0745 static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents,
0746                  0x188, 0, 4, 24, 3, BIT(31), 0);
0747 static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents,
0748                  0x18c, 0, 4, 24, 3, BIT(31), 0);
0749 static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents,
0750                  0x190, 0, 4, 24, 3, BIT(31), 0);
0751 static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents,
0752                  0x194, 0, 4, 24, 3, BIT(31), 0);
0753 
0754 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0755                  0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
0756 
0757 static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" };
0758 static const struct ccu_mux_fixed_prediv out_predivs[] = {
0759     { .index = 0, .div = 750, },
0760 };
0761 
0762 static struct ccu_mp outa_clk = {
0763     .enable = BIT(31),
0764     .m  = _SUNXI_CCU_DIV(8, 5),
0765     .p  = _SUNXI_CCU_DIV(20, 2),
0766     .mux    = {
0767         .shift      = 24,
0768         .width      = 2,
0769         .fixed_predivs  = out_predivs,
0770         .n_predivs  = ARRAY_SIZE(out_predivs),
0771     },
0772     .common = {
0773         .reg        = 0x1f0,
0774         .features   = CCU_FEATURE_FIXED_PREDIV,
0775         .hw.init    = CLK_HW_INIT_PARENTS("outa", out_parents,
0776                               &ccu_mp_ops,
0777                               CLK_SET_RATE_PARENT),
0778     }
0779 };
0780 
0781 static struct ccu_mp outb_clk = {
0782     .enable = BIT(31),
0783     .m  = _SUNXI_CCU_DIV(8, 5),
0784     .p  = _SUNXI_CCU_DIV(20, 2),
0785     .mux    = {
0786         .shift      = 24,
0787         .width      = 2,
0788         .fixed_predivs  = out_predivs,
0789         .n_predivs  = ARRAY_SIZE(out_predivs),
0790     },
0791     .common = {
0792         .reg        = 0x1f4,
0793         .features   = CCU_FEATURE_FIXED_PREDIV,
0794         .hw.init    = CLK_HW_INIT_PARENTS("outb", out_parents,
0795                               &ccu_mp_ops,
0796                               CLK_SET_RATE_PARENT),
0797     }
0798 };
0799 
0800 static struct ccu_common *sun8i_r40_ccu_clks[] = {
0801     &pll_cpu_clk.common,
0802     &pll_audio_base_clk.common,
0803     &pll_video0_clk.common,
0804     &pll_ve_clk.common,
0805     &pll_ddr0_clk.common,
0806     &pll_periph0_clk.common,
0807     &pll_periph0_sata_clk.common,
0808     &pll_periph1_clk.common,
0809     &pll_video1_clk.common,
0810     &pll_sata_clk.common,
0811     &pll_sata_out_clk.common,
0812     &pll_gpu_clk.common,
0813     &pll_mipi_clk.common,
0814     &pll_de_clk.common,
0815     &pll_ddr1_clk.common,
0816     &cpu_clk.common,
0817     &axi_clk.common,
0818     &ahb1_clk.common,
0819     &apb1_clk.common,
0820     &apb2_clk.common,
0821     &bus_mipi_dsi_clk.common,
0822     &bus_ce_clk.common,
0823     &bus_dma_clk.common,
0824     &bus_mmc0_clk.common,
0825     &bus_mmc1_clk.common,
0826     &bus_mmc2_clk.common,
0827     &bus_mmc3_clk.common,
0828     &bus_nand_clk.common,
0829     &bus_dram_clk.common,
0830     &bus_emac_clk.common,
0831     &bus_ts_clk.common,
0832     &bus_hstimer_clk.common,
0833     &bus_spi0_clk.common,
0834     &bus_spi1_clk.common,
0835     &bus_spi2_clk.common,
0836     &bus_spi3_clk.common,
0837     &bus_sata_clk.common,
0838     &bus_otg_clk.common,
0839     &bus_ehci0_clk.common,
0840     &bus_ehci1_clk.common,
0841     &bus_ehci2_clk.common,
0842     &bus_ohci0_clk.common,
0843     &bus_ohci1_clk.common,
0844     &bus_ohci2_clk.common,
0845     &bus_ve_clk.common,
0846     &bus_mp_clk.common,
0847     &bus_deinterlace_clk.common,
0848     &bus_csi0_clk.common,
0849     &bus_csi1_clk.common,
0850     &bus_hdmi0_clk.common,
0851     &bus_hdmi1_clk.common,
0852     &bus_de_clk.common,
0853     &bus_tve0_clk.common,
0854     &bus_tve1_clk.common,
0855     &bus_tve_top_clk.common,
0856     &bus_gmac_clk.common,
0857     &bus_gpu_clk.common,
0858     &bus_tvd0_clk.common,
0859     &bus_tvd1_clk.common,
0860     &bus_tvd2_clk.common,
0861     &bus_tvd3_clk.common,
0862     &bus_tvd_top_clk.common,
0863     &bus_tcon_lcd0_clk.common,
0864     &bus_tcon_lcd1_clk.common,
0865     &bus_tcon_tv0_clk.common,
0866     &bus_tcon_tv1_clk.common,
0867     &bus_tcon_top_clk.common,
0868     &bus_codec_clk.common,
0869     &bus_spdif_clk.common,
0870     &bus_ac97_clk.common,
0871     &bus_pio_clk.common,
0872     &bus_ir0_clk.common,
0873     &bus_ir1_clk.common,
0874     &bus_ths_clk.common,
0875     &bus_keypad_clk.common,
0876     &bus_i2s0_clk.common,
0877     &bus_i2s1_clk.common,
0878     &bus_i2s2_clk.common,
0879     &bus_i2c0_clk.common,
0880     &bus_i2c1_clk.common,
0881     &bus_i2c2_clk.common,
0882     &bus_i2c3_clk.common,
0883     &bus_can_clk.common,
0884     &bus_scr_clk.common,
0885     &bus_ps20_clk.common,
0886     &bus_ps21_clk.common,
0887     &bus_i2c4_clk.common,
0888     &bus_uart0_clk.common,
0889     &bus_uart1_clk.common,
0890     &bus_uart2_clk.common,
0891     &bus_uart3_clk.common,
0892     &bus_uart4_clk.common,
0893     &bus_uart5_clk.common,
0894     &bus_uart6_clk.common,
0895     &bus_uart7_clk.common,
0896     &bus_dbg_clk.common,
0897     &ths_clk.common,
0898     &nand_clk.common,
0899     &mmc0_clk.common,
0900     &mmc1_clk.common,
0901     &mmc2_clk.common,
0902     &mmc3_clk.common,
0903     &ts_clk.common,
0904     &ce_clk.common,
0905     &spi0_clk.common,
0906     &spi1_clk.common,
0907     &spi2_clk.common,
0908     &spi3_clk.common,
0909     &i2s0_clk.common,
0910     &i2s1_clk.common,
0911     &i2s2_clk.common,
0912     &ac97_clk.common,
0913     &spdif_clk.common,
0914     &keypad_clk.common,
0915     &sata_clk.common,
0916     &usb_phy0_clk.common,
0917     &usb_phy1_clk.common,
0918     &usb_phy2_clk.common,
0919     &usb_ohci0_clk.common,
0920     &usb_ohci1_clk.common,
0921     &usb_ohci2_clk.common,
0922     &ir0_clk.common,
0923     &ir1_clk.common,
0924     &dram_clk.common,
0925     &dram_ve_clk.common,
0926     &dram_csi0_clk.common,
0927     &dram_csi1_clk.common,
0928     &dram_ts_clk.common,
0929     &dram_tvd_clk.common,
0930     &dram_mp_clk.common,
0931     &dram_deinterlace_clk.common,
0932     &de_clk.common,
0933     &mp_clk.common,
0934     &tcon_lcd0_clk.common,
0935     &tcon_lcd1_clk.common,
0936     &tcon_tv0_clk.common,
0937     &tcon_tv1_clk.common,
0938     &deinterlace_clk.common,
0939     &csi1_mclk_clk.common,
0940     &csi_sclk_clk.common,
0941     &csi0_mclk_clk.common,
0942     &ve_clk.common,
0943     &codec_clk.common,
0944     &avs_clk.common,
0945     &hdmi_clk.common,
0946     &hdmi_slow_clk.common,
0947     &mbus_clk.common,
0948     &dsi_dphy_clk.common,
0949     &tve0_clk.common,
0950     &tve1_clk.common,
0951     &tvd0_clk.common,
0952     &tvd1_clk.common,
0953     &tvd2_clk.common,
0954     &tvd3_clk.common,
0955     &gpu_clk.common,
0956     &outa_clk.common,
0957     &outb_clk.common,
0958 };
0959 
0960 /* Fixed Factor clocks */
0961 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
0962 
0963 static const struct clk_hw *clk_parent_pll_audio[] = {
0964     &pll_audio_base_clk.common.hw
0965 };
0966 
0967 /* We hardcode the divider to 1 for now */
0968 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
0969                 clk_parent_pll_audio,
0970                 1, 1, CLK_SET_RATE_PARENT);
0971 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
0972                 clk_parent_pll_audio,
0973                 2, 1, CLK_SET_RATE_PARENT);
0974 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
0975                 clk_parent_pll_audio,
0976                 1, 1, CLK_SET_RATE_PARENT);
0977 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
0978                 clk_parent_pll_audio,
0979                 1, 2, CLK_SET_RATE_PARENT);
0980 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
0981                &pll_periph0_clk.common.hw,
0982                1, 2, 0);
0983 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
0984                &pll_periph1_clk.common.hw,
0985                1, 2, 0);
0986 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
0987                &pll_video0_clk.common.hw,
0988                1, 2, 0);
0989 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
0990                &pll_video1_clk.common.hw,
0991                1, 2, 0);
0992 
0993 static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
0994     .hws    = {
0995         [CLK_OSC_12M]       = &osc12M_clk.hw,
0996         [CLK_PLL_CPU]       = &pll_cpu_clk.common.hw,
0997         [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
0998         [CLK_PLL_AUDIO]     = &pll_audio_clk.hw,
0999         [CLK_PLL_AUDIO_2X]  = &pll_audio_2x_clk.hw,
1000         [CLK_PLL_AUDIO_4X]  = &pll_audio_4x_clk.hw,
1001         [CLK_PLL_AUDIO_8X]  = &pll_audio_8x_clk.hw,
1002         [CLK_PLL_VIDEO0]    = &pll_video0_clk.common.hw,
1003         [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
1004         [CLK_PLL_VE]        = &pll_ve_clk.common.hw,
1005         [CLK_PLL_DDR0]      = &pll_ddr0_clk.common.hw,
1006         [CLK_PLL_PERIPH0]   = &pll_periph0_clk.common.hw,
1007         [CLK_PLL_PERIPH0_SATA]  = &pll_periph0_sata_clk.common.hw,
1008         [CLK_PLL_PERIPH0_2X]    = &pll_periph0_2x_clk.hw,
1009         [CLK_PLL_PERIPH1]   = &pll_periph1_clk.common.hw,
1010         [CLK_PLL_PERIPH1_2X]    = &pll_periph1_2x_clk.hw,
1011         [CLK_PLL_VIDEO1]    = &pll_video1_clk.common.hw,
1012         [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
1013         [CLK_PLL_SATA]      = &pll_sata_clk.common.hw,
1014         [CLK_PLL_SATA_OUT]  = &pll_sata_out_clk.common.hw,
1015         [CLK_PLL_GPU]       = &pll_gpu_clk.common.hw,
1016         [CLK_PLL_MIPI]      = &pll_mipi_clk.common.hw,
1017         [CLK_PLL_DE]        = &pll_de_clk.common.hw,
1018         [CLK_PLL_DDR1]      = &pll_ddr1_clk.common.hw,
1019         [CLK_CPU]       = &cpu_clk.common.hw,
1020         [CLK_AXI]       = &axi_clk.common.hw,
1021         [CLK_AHB1]      = &ahb1_clk.common.hw,
1022         [CLK_APB1]      = &apb1_clk.common.hw,
1023         [CLK_APB2]      = &apb2_clk.common.hw,
1024         [CLK_BUS_MIPI_DSI]  = &bus_mipi_dsi_clk.common.hw,
1025         [CLK_BUS_CE]        = &bus_ce_clk.common.hw,
1026         [CLK_BUS_DMA]       = &bus_dma_clk.common.hw,
1027         [CLK_BUS_MMC0]      = &bus_mmc0_clk.common.hw,
1028         [CLK_BUS_MMC1]      = &bus_mmc1_clk.common.hw,
1029         [CLK_BUS_MMC2]      = &bus_mmc2_clk.common.hw,
1030         [CLK_BUS_MMC3]      = &bus_mmc3_clk.common.hw,
1031         [CLK_BUS_NAND]      = &bus_nand_clk.common.hw,
1032         [CLK_BUS_DRAM]      = &bus_dram_clk.common.hw,
1033         [CLK_BUS_EMAC]      = &bus_emac_clk.common.hw,
1034         [CLK_BUS_TS]        = &bus_ts_clk.common.hw,
1035         [CLK_BUS_HSTIMER]   = &bus_hstimer_clk.common.hw,
1036         [CLK_BUS_SPI0]      = &bus_spi0_clk.common.hw,
1037         [CLK_BUS_SPI1]      = &bus_spi1_clk.common.hw,
1038         [CLK_BUS_SPI2]      = &bus_spi2_clk.common.hw,
1039         [CLK_BUS_SPI3]      = &bus_spi3_clk.common.hw,
1040         [CLK_BUS_SATA]      = &bus_sata_clk.common.hw,
1041         [CLK_BUS_OTG]       = &bus_otg_clk.common.hw,
1042         [CLK_BUS_EHCI0]     = &bus_ehci0_clk.common.hw,
1043         [CLK_BUS_EHCI1]     = &bus_ehci1_clk.common.hw,
1044         [CLK_BUS_EHCI2]     = &bus_ehci2_clk.common.hw,
1045         [CLK_BUS_OHCI0]     = &bus_ohci0_clk.common.hw,
1046         [CLK_BUS_OHCI1]     = &bus_ohci1_clk.common.hw,
1047         [CLK_BUS_OHCI2]     = &bus_ohci2_clk.common.hw,
1048         [CLK_BUS_VE]        = &bus_ve_clk.common.hw,
1049         [CLK_BUS_MP]        = &bus_mp_clk.common.hw,
1050         [CLK_BUS_DEINTERLACE]   = &bus_deinterlace_clk.common.hw,
1051         [CLK_BUS_CSI0]      = &bus_csi0_clk.common.hw,
1052         [CLK_BUS_CSI1]      = &bus_csi1_clk.common.hw,
1053         [CLK_BUS_HDMI0]     = &bus_hdmi0_clk.common.hw,
1054         [CLK_BUS_HDMI1]     = &bus_hdmi1_clk.common.hw,
1055         [CLK_BUS_DE]        = &bus_de_clk.common.hw,
1056         [CLK_BUS_TVE0]      = &bus_tve0_clk.common.hw,
1057         [CLK_BUS_TVE1]      = &bus_tve1_clk.common.hw,
1058         [CLK_BUS_TVE_TOP]   = &bus_tve_top_clk.common.hw,
1059         [CLK_BUS_GMAC]      = &bus_gmac_clk.common.hw,
1060         [CLK_BUS_GPU]       = &bus_gpu_clk.common.hw,
1061         [CLK_BUS_TVD0]      = &bus_tvd0_clk.common.hw,
1062         [CLK_BUS_TVD1]      = &bus_tvd1_clk.common.hw,
1063         [CLK_BUS_TVD2]      = &bus_tvd2_clk.common.hw,
1064         [CLK_BUS_TVD3]      = &bus_tvd3_clk.common.hw,
1065         [CLK_BUS_TVD_TOP]   = &bus_tvd_top_clk.common.hw,
1066         [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
1067         [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw,
1068         [CLK_BUS_TCON_TV0]  = &bus_tcon_tv0_clk.common.hw,
1069         [CLK_BUS_TCON_TV1]  = &bus_tcon_tv1_clk.common.hw,
1070         [CLK_BUS_TCON_TOP]  = &bus_tcon_top_clk.common.hw,
1071         [CLK_BUS_CODEC]     = &bus_codec_clk.common.hw,
1072         [CLK_BUS_SPDIF]     = &bus_spdif_clk.common.hw,
1073         [CLK_BUS_AC97]      = &bus_ac97_clk.common.hw,
1074         [CLK_BUS_PIO]       = &bus_pio_clk.common.hw,
1075         [CLK_BUS_IR0]       = &bus_ir0_clk.common.hw,
1076         [CLK_BUS_IR1]       = &bus_ir1_clk.common.hw,
1077         [CLK_BUS_THS]       = &bus_ths_clk.common.hw,
1078         [CLK_BUS_KEYPAD]    = &bus_keypad_clk.common.hw,
1079         [CLK_BUS_I2S0]      = &bus_i2s0_clk.common.hw,
1080         [CLK_BUS_I2S1]      = &bus_i2s1_clk.common.hw,
1081         [CLK_BUS_I2S2]      = &bus_i2s2_clk.common.hw,
1082         [CLK_BUS_I2C0]      = &bus_i2c0_clk.common.hw,
1083         [CLK_BUS_I2C1]      = &bus_i2c1_clk.common.hw,
1084         [CLK_BUS_I2C2]      = &bus_i2c2_clk.common.hw,
1085         [CLK_BUS_I2C3]      = &bus_i2c3_clk.common.hw,
1086         [CLK_BUS_CAN]       = &bus_can_clk.common.hw,
1087         [CLK_BUS_SCR]       = &bus_scr_clk.common.hw,
1088         [CLK_BUS_PS20]      = &bus_ps20_clk.common.hw,
1089         [CLK_BUS_PS21]      = &bus_ps21_clk.common.hw,
1090         [CLK_BUS_I2C4]      = &bus_i2c4_clk.common.hw,
1091         [CLK_BUS_UART0]     = &bus_uart0_clk.common.hw,
1092         [CLK_BUS_UART1]     = &bus_uart1_clk.common.hw,
1093         [CLK_BUS_UART2]     = &bus_uart2_clk.common.hw,
1094         [CLK_BUS_UART3]     = &bus_uart3_clk.common.hw,
1095         [CLK_BUS_UART4]     = &bus_uart4_clk.common.hw,
1096         [CLK_BUS_UART5]     = &bus_uart5_clk.common.hw,
1097         [CLK_BUS_UART6]     = &bus_uart6_clk.common.hw,
1098         [CLK_BUS_UART7]     = &bus_uart7_clk.common.hw,
1099         [CLK_BUS_DBG]       = &bus_dbg_clk.common.hw,
1100         [CLK_THS]       = &ths_clk.common.hw,
1101         [CLK_NAND]      = &nand_clk.common.hw,
1102         [CLK_MMC0]      = &mmc0_clk.common.hw,
1103         [CLK_MMC1]      = &mmc1_clk.common.hw,
1104         [CLK_MMC2]      = &mmc2_clk.common.hw,
1105         [CLK_MMC3]      = &mmc3_clk.common.hw,
1106         [CLK_TS]        = &ts_clk.common.hw,
1107         [CLK_CE]        = &ce_clk.common.hw,
1108         [CLK_SPI0]      = &spi0_clk.common.hw,
1109         [CLK_SPI1]      = &spi1_clk.common.hw,
1110         [CLK_SPI2]      = &spi2_clk.common.hw,
1111         [CLK_SPI3]      = &spi3_clk.common.hw,
1112         [CLK_I2S0]      = &i2s0_clk.common.hw,
1113         [CLK_I2S1]      = &i2s1_clk.common.hw,
1114         [CLK_I2S2]      = &i2s2_clk.common.hw,
1115         [CLK_AC97]      = &ac97_clk.common.hw,
1116         [CLK_SPDIF]     = &spdif_clk.common.hw,
1117         [CLK_KEYPAD]        = &keypad_clk.common.hw,
1118         [CLK_SATA]      = &sata_clk.common.hw,
1119         [CLK_USB_PHY0]      = &usb_phy0_clk.common.hw,
1120         [CLK_USB_PHY1]      = &usb_phy1_clk.common.hw,
1121         [CLK_USB_PHY2]      = &usb_phy2_clk.common.hw,
1122         [CLK_USB_OHCI0]     = &usb_ohci0_clk.common.hw,
1123         [CLK_USB_OHCI1]     = &usb_ohci1_clk.common.hw,
1124         [CLK_USB_OHCI2]     = &usb_ohci2_clk.common.hw,
1125         [CLK_IR0]       = &ir0_clk.common.hw,
1126         [CLK_IR1]       = &ir1_clk.common.hw,
1127         [CLK_DRAM]      = &dram_clk.common.hw,
1128         [CLK_DRAM_VE]       = &dram_ve_clk.common.hw,
1129         [CLK_DRAM_CSI0]     = &dram_csi0_clk.common.hw,
1130         [CLK_DRAM_CSI1]     = &dram_csi1_clk.common.hw,
1131         [CLK_DRAM_TS]       = &dram_ts_clk.common.hw,
1132         [CLK_DRAM_TVD]      = &dram_tvd_clk.common.hw,
1133         [CLK_DRAM_MP]       = &dram_mp_clk.common.hw,
1134         [CLK_DRAM_DEINTERLACE]  = &dram_deinterlace_clk.common.hw,
1135         [CLK_DE]        = &de_clk.common.hw,
1136         [CLK_MP]        = &mp_clk.common.hw,
1137         [CLK_TCON_LCD0]     = &tcon_lcd0_clk.common.hw,
1138         [CLK_TCON_LCD1]     = &tcon_lcd1_clk.common.hw,
1139         [CLK_TCON_TV0]      = &tcon_tv0_clk.common.hw,
1140         [CLK_TCON_TV1]      = &tcon_tv1_clk.common.hw,
1141         [CLK_DEINTERLACE]   = &deinterlace_clk.common.hw,
1142         [CLK_CSI1_MCLK]     = &csi1_mclk_clk.common.hw,
1143         [CLK_CSI_SCLK]      = &csi_sclk_clk.common.hw,
1144         [CLK_CSI0_MCLK]     = &csi0_mclk_clk.common.hw,
1145         [CLK_VE]        = &ve_clk.common.hw,
1146         [CLK_CODEC]     = &codec_clk.common.hw,
1147         [CLK_AVS]       = &avs_clk.common.hw,
1148         [CLK_HDMI]      = &hdmi_clk.common.hw,
1149         [CLK_HDMI_SLOW]     = &hdmi_slow_clk.common.hw,
1150         [CLK_MBUS]      = &mbus_clk.common.hw,
1151         [CLK_DSI_DPHY]      = &dsi_dphy_clk.common.hw,
1152         [CLK_TVE0]      = &tve0_clk.common.hw,
1153         [CLK_TVE1]      = &tve1_clk.common.hw,
1154         [CLK_TVD0]      = &tvd0_clk.common.hw,
1155         [CLK_TVD1]      = &tvd1_clk.common.hw,
1156         [CLK_TVD2]      = &tvd2_clk.common.hw,
1157         [CLK_TVD3]      = &tvd3_clk.common.hw,
1158         [CLK_GPU]       = &gpu_clk.common.hw,
1159         [CLK_OUTA]      = &outa_clk.common.hw,
1160         [CLK_OUTB]      = &outb_clk.common.hw,
1161     },
1162     .num    = CLK_NUMBER,
1163 };
1164 
1165 static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
1166     [RST_USB_PHY0]      =  { 0x0cc, BIT(0) },
1167     [RST_USB_PHY1]      =  { 0x0cc, BIT(1) },
1168     [RST_USB_PHY2]      =  { 0x0cc, BIT(2) },
1169 
1170     [RST_DRAM]      =  { 0x0f4, BIT(31) },
1171     [RST_MBUS]      =  { 0x0fc, BIT(31) },
1172 
1173     [RST_BUS_MIPI_DSI]  =  { 0x2c0, BIT(1) },
1174     [RST_BUS_CE]        =  { 0x2c0, BIT(5) },
1175     [RST_BUS_DMA]       =  { 0x2c0, BIT(6) },
1176     [RST_BUS_MMC0]      =  { 0x2c0, BIT(8) },
1177     [RST_BUS_MMC1]      =  { 0x2c0, BIT(9) },
1178     [RST_BUS_MMC2]      =  { 0x2c0, BIT(10) },
1179     [RST_BUS_MMC3]      =  { 0x2c0, BIT(11) },
1180     [RST_BUS_NAND]      =  { 0x2c0, BIT(13) },
1181     [RST_BUS_DRAM]      =  { 0x2c0, BIT(14) },
1182     [RST_BUS_EMAC]      =  { 0x2c0, BIT(17) },
1183     [RST_BUS_TS]        =  { 0x2c0, BIT(18) },
1184     [RST_BUS_HSTIMER]   =  { 0x2c0, BIT(19) },
1185     [RST_BUS_SPI0]      =  { 0x2c0, BIT(20) },
1186     [RST_BUS_SPI1]      =  { 0x2c0, BIT(21) },
1187     [RST_BUS_SPI2]      =  { 0x2c0, BIT(22) },
1188     [RST_BUS_SPI3]      =  { 0x2c0, BIT(23) },
1189     [RST_BUS_SATA]      =  { 0x2c0, BIT(24) },
1190     [RST_BUS_OTG]       =  { 0x2c0, BIT(25) },
1191     [RST_BUS_EHCI0]     =  { 0x2c0, BIT(26) },
1192     [RST_BUS_EHCI1]     =  { 0x2c0, BIT(27) },
1193     [RST_BUS_EHCI2]     =  { 0x2c0, BIT(28) },
1194     [RST_BUS_OHCI0]     =  { 0x2c0, BIT(29) },
1195     [RST_BUS_OHCI1]     =  { 0x2c0, BIT(30) },
1196     [RST_BUS_OHCI2]     =  { 0x2c0, BIT(31) },
1197 
1198     [RST_BUS_VE]        =  { 0x2c4, BIT(0) },
1199     [RST_BUS_MP]        =  { 0x2c4, BIT(2) },
1200     [RST_BUS_DEINTERLACE]   =  { 0x2c4, BIT(5) },
1201     [RST_BUS_CSI0]      =  { 0x2c4, BIT(8) },
1202     [RST_BUS_CSI1]      =  { 0x2c4, BIT(9) },
1203     [RST_BUS_HDMI0]     =  { 0x2c4, BIT(10) },
1204     [RST_BUS_HDMI1]     =  { 0x2c4, BIT(11) },
1205     [RST_BUS_DE]        =  { 0x2c4, BIT(12) },
1206     [RST_BUS_TVE0]      =  { 0x2c4, BIT(13) },
1207     [RST_BUS_TVE1]      =  { 0x2c4, BIT(14) },
1208     [RST_BUS_TVE_TOP]   =  { 0x2c4, BIT(15) },
1209     [RST_BUS_GMAC]      =  { 0x2c4, BIT(17) },
1210     [RST_BUS_GPU]       =  { 0x2c4, BIT(20) },
1211     [RST_BUS_TVD0]      =  { 0x2c4, BIT(21) },
1212     [RST_BUS_TVD1]      =  { 0x2c4, BIT(22) },
1213     [RST_BUS_TVD2]      =  { 0x2c4, BIT(23) },
1214     [RST_BUS_TVD3]      =  { 0x2c4, BIT(24) },
1215     [RST_BUS_TVD_TOP]   =  { 0x2c4, BIT(25) },
1216     [RST_BUS_TCON_LCD0] =  { 0x2c4, BIT(26) },
1217     [RST_BUS_TCON_LCD1] =  { 0x2c4, BIT(27) },
1218     [RST_BUS_TCON_TV0]  =  { 0x2c4, BIT(28) },
1219     [RST_BUS_TCON_TV1]  =  { 0x2c4, BIT(29) },
1220     [RST_BUS_TCON_TOP]  =  { 0x2c4, BIT(30) },
1221     [RST_BUS_DBG]       =  { 0x2c4, BIT(31) },
1222 
1223     [RST_BUS_LVDS]      =  { 0x2c8, BIT(0) },
1224 
1225     [RST_BUS_CODEC]     =  { 0x2d0, BIT(0) },
1226     [RST_BUS_SPDIF]     =  { 0x2d0, BIT(1) },
1227     [RST_BUS_AC97]      =  { 0x2d0, BIT(2) },
1228     [RST_BUS_IR0]       =  { 0x2d0, BIT(6) },
1229     [RST_BUS_IR1]       =  { 0x2d0, BIT(7) },
1230     [RST_BUS_THS]       =  { 0x2d0, BIT(8) },
1231     [RST_BUS_KEYPAD]    =  { 0x2d0, BIT(10) },
1232     [RST_BUS_I2S0]      =  { 0x2d0, BIT(12) },
1233     [RST_BUS_I2S1]      =  { 0x2d0, BIT(13) },
1234     [RST_BUS_I2S2]      =  { 0x2d0, BIT(14) },
1235 
1236     [RST_BUS_I2C0]      =  { 0x2d8, BIT(0) },
1237     [RST_BUS_I2C1]      =  { 0x2d8, BIT(1) },
1238     [RST_BUS_I2C2]      =  { 0x2d8, BIT(2) },
1239     [RST_BUS_I2C3]      =  { 0x2d8, BIT(3) },
1240     [RST_BUS_CAN]       =  { 0x2d8, BIT(4) },
1241     [RST_BUS_SCR]       =  { 0x2d8, BIT(5) },
1242     [RST_BUS_PS20]      =  { 0x2d8, BIT(6) },
1243     [RST_BUS_PS21]      =  { 0x2d8, BIT(7) },
1244     [RST_BUS_I2C4]      =  { 0x2d8, BIT(15) },
1245     [RST_BUS_UART0]     =  { 0x2d8, BIT(16) },
1246     [RST_BUS_UART1]     =  { 0x2d8, BIT(17) },
1247     [RST_BUS_UART2]     =  { 0x2d8, BIT(18) },
1248     [RST_BUS_UART3]     =  { 0x2d8, BIT(19) },
1249     [RST_BUS_UART4]     =  { 0x2d8, BIT(20) },
1250     [RST_BUS_UART5]     =  { 0x2d8, BIT(21) },
1251     [RST_BUS_UART6]     =  { 0x2d8, BIT(22) },
1252     [RST_BUS_UART7]     =  { 0x2d8, BIT(23) },
1253 };
1254 
1255 static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = {
1256     .ccu_clks   = sun8i_r40_ccu_clks,
1257     .num_ccu_clks   = ARRAY_SIZE(sun8i_r40_ccu_clks),
1258 
1259     .hw_clks    = &sun8i_r40_hw_clks,
1260 
1261     .resets     = sun8i_r40_ccu_resets,
1262     .num_resets = ARRAY_SIZE(sun8i_r40_ccu_resets),
1263 };
1264 
1265 static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = {
1266     .common = &pll_cpu_clk.common,
1267     /* copy from pll_cpu_clk */
1268     .enable = BIT(31),
1269     .lock   = BIT(28),
1270 };
1271 
1272 static struct ccu_mux_nb sun8i_r40_cpu_nb = {
1273     .common     = &cpu_clk.common,
1274     .cm     = &cpu_clk.mux,
1275     .delay_us   = 1, /* > 8 clock cycles at 24 MHz */
1276     .bypass_index   = 1, /* index of 24 MHz oscillator */
1277 };
1278 
1279 /*
1280  * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
1281  * GMAC configuration register.
1282  * Only this register is allowed to be written, in order to
1283  * prevent overriding critical clock configuration.
1284  */
1285 
1286 #define SUN8I_R40_GMAC_CFG_REG 0x164
1287 static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev,
1288                         unsigned int reg)
1289 {
1290     if (reg == SUN8I_R40_GMAC_CFG_REG)
1291         return true;
1292     return false;
1293 }
1294 
1295 static struct regmap_config sun8i_r40_ccu_regmap_config = {
1296     .reg_bits   = 32,
1297     .val_bits   = 32,
1298     .reg_stride = 4,
1299     .max_register   = 0x320, /* PLL_LOCK_CTRL_REG */
1300 
1301     /* other devices have no business accessing other registers */
1302     .readable_reg   = sun8i_r40_ccu_regmap_accessible_reg,
1303     .writeable_reg  = sun8i_r40_ccu_regmap_accessible_reg,
1304 };
1305 
1306 #define SUN8I_R40_SYS_32K_CLK_REG 0x310
1307 #define SUN8I_R40_SYS_32K_CLK_KEY (0x16AA << 16)
1308 
1309 static int sun8i_r40_ccu_probe(struct platform_device *pdev)
1310 {
1311     struct regmap *regmap;
1312     void __iomem *reg;
1313     u32 val;
1314     int ret;
1315 
1316     reg = devm_platform_ioremap_resource(pdev, 0);
1317     if (IS_ERR(reg))
1318         return PTR_ERR(reg);
1319 
1320     /* Force the PLL-Audio-1x divider to 1 */
1321     val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
1322     val &= ~GENMASK(19, 16);
1323     writel(val | (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
1324 
1325     /* Force PLL-MIPI to MIPI mode */
1326     val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
1327     val &= ~BIT(16);
1328     writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
1329 
1330     /* Force OHCI 12M parent to 12M divided from 48M */
1331     val = readl(reg + SUN8I_R40_USB_CLK_REG);
1332     val &= ~GENMASK(25, 20);
1333     writel(val, reg + SUN8I_R40_USB_CLK_REG);
1334 
1335     /*
1336      * Force SYS 32k (otherwise known as LOSC throughout the CCU)
1337      * clock parent to LOSC output from RTC module instead of the
1338      * CCU's internal RC oscillator divided output.
1339      */
1340     writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8),
1341            reg + SUN8I_R40_SYS_32K_CLK_REG);
1342 
1343     regmap = devm_regmap_init_mmio(&pdev->dev, reg,
1344                        &sun8i_r40_ccu_regmap_config);
1345     if (IS_ERR(regmap))
1346         return PTR_ERR(regmap);
1347 
1348     ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_r40_ccu_desc);
1349     if (ret)
1350         return ret;
1351 
1352     /* Gate then ungate PLL CPU after any rate changes */
1353     ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
1354 
1355     /* Reparent CPU during PLL CPU rate changes */
1356     ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1357                   &sun8i_r40_cpu_nb);
1358 
1359     return 0;
1360 }
1361 
1362 static const struct of_device_id sun8i_r40_ccu_ids[] = {
1363     { .compatible = "allwinner,sun8i-r40-ccu" },
1364     { }
1365 };
1366 
1367 static struct platform_driver sun8i_r40_ccu_driver = {
1368     .probe  = sun8i_r40_ccu_probe,
1369     .driver = {
1370         .name   = "sun8i-r40-ccu",
1371         .suppress_bind_attrs = true,
1372         .of_match_table = sun8i_r40_ccu_ids,
1373     },
1374 };
1375 module_platform_driver(sun8i_r40_ccu_driver);
1376 
1377 MODULE_IMPORT_NS(SUNXI_CCU);
1378 MODULE_LICENSE("GPL");
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