clk/sunxi-ng/ccu-sun8i-h3.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2016 Maxime Ripard
0004  *
0005  * Maxime Ripard <maxime.ripard@free-electrons.com>
0006  */
0007
0008 #ifndef _CCU_SUN8I_H3_H_
0009 #define _CCU_SUN8I_H3_H_
0010
0011 #include <dt-bindings/clock/sun8i-h3-ccu.h>
0012 #include <dt-bindings/reset/sun8i-h3-ccu.h>
0013
0014 #define CLK_PLL_CPUX        0
0015 #define CLK_PLL_AUDIO_BASE  1
0016 #define CLK_PLL_AUDIO       2
0017 #define CLK_PLL_AUDIO_2X    3
0018 #define CLK_PLL_AUDIO_4X    4
0019 #define CLK_PLL_AUDIO_8X    5
0020
0021 /* PLL_VIDEO is exported */
0022
0023 #define CLK_PLL_VE      7
0024 #define CLK_PLL_DDR     8
0025
0026 /* PLL_PERIPH0 exported for PRCM */
0027
0028 #define CLK_PLL_PERIPH0_2X  10
0029 #define CLK_PLL_GPU     11
0030 #define CLK_PLL_PERIPH1     12
0031 #define CLK_PLL_DE      13
0032
0033 /* The CPUX clock is exported */
0034
0035 #define CLK_AXI         15
0036 #define CLK_AHB1        16
0037 #define CLK_APB1        17
0038 #define CLK_APB2        18
0039 #define CLK_AHB2        19
0040
0041 /* All the bus gates are exported */
0042
0043 /* The first bunch of module clocks are exported */
0044
0045 /* All the DRAM gates are exported */
0046
0047 /* Some more module clocks are exported */
0048
0049 #define CLK_NUMBER_H3       (CLK_GPU + 1)
0050 #define CLK_NUMBER_H5       (CLK_BUS_SCR1 + 1)
0051
0052 #endif /* _CCU_SUN8I_H3_H_ */