clk/sunxi-ng/ccu-sun8i-a83t.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2016 Chen-Yu Tsai
0004  *
0005  * Chen-Yu Tsai <wens@csie.org>
0006  */
0007
0008 #ifndef _CCU_SUN8I_A83T_H_
0009 #define _CCU_SUN8I_A83T_H_
0010
0011 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
0012 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
0013
0014 #define CLK_PLL_C0CPUX      0
0015 #define CLK_PLL_C1CPUX      1
0016 #define CLK_PLL_AUDIO       2
0017 #define CLK_PLL_VIDEO0      3
0018 #define CLK_PLL_VE      4
0019 #define CLK_PLL_DDR     5
0020
0021 /* pll-periph is exported to the PRCM block */
0022
0023 #define CLK_PLL_GPU     7
0024 #define CLK_PLL_HSIC        8
0025
0026 /* pll-de is exported for the display engine */
0027
0028 #define CLK_PLL_VIDEO1      10
0029
0030 /* The CPUX clocks are exported */
0031
0032 #define CLK_AXI0        13
0033 #define CLK_AXI1        14
0034 #define CLK_AHB1        15
0035 #define CLK_AHB2        16
0036 #define CLK_APB1        17
0037 #define CLK_APB2        18
0038
0039 /* bus gates exported */
0040
0041 #define CLK_CCI400      58
0042
0043 /* module and usb clocks exported */
0044
0045 #define CLK_DRAM        82
0046
0047 /* dram gates and more module clocks exported */
0048
0049 #define CLK_MBUS        95
0050
0051 /* more module clocks exported */
0052
0053 #define CLK_NUMBER      (CLK_GPU_HYD + 1)
0054
0055 #endif /* _CCU_SUN8I_A83T_H_ */