clk/sunxi-ng/ccu-sun8i-a33.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
0004  */
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/io.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010
0011 #include "ccu_common.h"
0012 #include "ccu_reset.h"
0013
0014 #include "ccu_div.h"
0015 #include "ccu_gate.h"
0016 #include "ccu_mp.h"
0017 #include "ccu_mult.h"
0018 #include "ccu_nk.h"
0019 #include "ccu_nkm.h"
0020 #include "ccu_nkmp.h"
0021 #include "ccu_nm.h"
0022 #include "ccu_phase.h"
0023
0024 #include "ccu-sun8i-a23-a33.h"
0025
0026 static struct ccu_nkmp pll_cpux_clk = {
0027     .enable = BIT(31),
0028     .lock   = BIT(28),
0029
0030     .n  = _SUNXI_CCU_MULT(8, 5),
0031     .k  = _SUNXI_CCU_MULT(4, 2),
0032     .m  = _SUNXI_CCU_DIV(0, 2),
0033     .p  = _SUNXI_CCU_DIV_MAX(16, 2, 4),
0034
0035     .common = {
0036         .reg        = 0x000,
0037         .hw.init    = CLK_HW_INIT("pll-cpux", "osc24M",
0038                           &ccu_nkmp_ops,
0039                           0),
0040     },
0041 };
0042
0043 /*
0044  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
0045  * the base (2x, 4x and 8x), and one variable divider (the one true
0046  * pll audio).
0047  *
0048  * With sigma-delta modulation for fractional-N on the audio PLL,
0049  * we have to use specific dividers. This means the variable divider
0050  * can no longer be used, as the audio codec requests the exact clock
0051  * rates we support through this mechanism. So we now hard code the
0052  * variable divider to 1. This means the clock rates will no longer
0053  * match the clock names.
0054  */
0055 #define SUN8I_A33_PLL_AUDIO_REG 0x008
0056
0057 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
0058     { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
0059     { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
0060 };
0061
0062 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
0063                        "osc24M", 0x008,
0064                        8, 7,    /* N */
0065                        0, 5,    /* M */
0066                        pll_audio_sdm_table, BIT(24),
0067                        0x284, BIT(31),
0068                        BIT(31), /* gate */
0069                        BIT(28), /* lock */
0070                        CLK_SET_RATE_UNGATE);
0071
0072 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
0073                     "osc24M", 0x010,
0074                     8, 7,       /* N */
0075                     0, 4,       /* M */
0076                     BIT(24),    /* frac enable */
0077                     BIT(25),    /* frac select */
0078                     270000000,  /* frac rate 0 */
0079                     297000000,  /* frac rate 1 */
0080                     BIT(31),    /* gate */
0081                     BIT(28),    /* lock */
0082                     CLK_SET_RATE_UNGATE);
0083
0084 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
0085                     "osc24M", 0x018,
0086                     8, 7,       /* N */
0087                     0, 4,       /* M */
0088                     BIT(24),    /* frac enable */
0089                     BIT(25),    /* frac select */
0090                     270000000,  /* frac rate 0 */
0091                     297000000,  /* frac rate 1 */
0092                     BIT(31),    /* gate */
0093                     BIT(28),    /* lock */
0094                     CLK_SET_RATE_UNGATE);
0095
0096 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
0097                     "osc24M", 0x020,
0098                     8, 5,       /* N */
0099                     4, 2,       /* K */
0100                     0, 2,       /* M */
0101                     BIT(31),        /* gate */
0102                     BIT(28),        /* lock */
0103                     0);
0104
0105 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
0106                        "osc24M", 0x028,
0107                        8, 5,    /* N */
0108                        4, 2,    /* K */
0109                        BIT(31), /* gate */
0110                        BIT(28), /* lock */
0111                        2,       /* post-div */
0112                        CLK_SET_RATE_UNGATE);
0113
0114 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
0115                     "osc24M", 0x038,
0116                     8, 7,       /* N */
0117                     0, 4,       /* M */
0118                     BIT(24),    /* frac enable */
0119                     BIT(25),    /* frac select */
0120                     270000000,  /* frac rate 0 */
0121                     297000000,  /* frac rate 1 */
0122                     BIT(31),    /* gate */
0123                     BIT(28),    /* lock */
0124                     CLK_SET_RATE_UNGATE);
0125
0126 /*
0127  * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
0128  *
0129  * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
0130  * integer / fractional clock with switchable multipliers and dividers.
0131  * This is not supported here. We hardcode the PLL to MIPI mode.
0132  */
0133 #define SUN8I_A33_PLL_MIPI_REG  0x040
0134 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
0135                     "pll-video", 0x040,
0136                     8, 4,       /* N */
0137                     4, 2,       /* K */
0138                     0, 4,       /* M */
0139                     BIT(31) | BIT(23) | BIT(22), /* gate */
0140                     BIT(28),        /* lock */
0141                     CLK_SET_RATE_UNGATE);
0142
0143 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
0144                     "osc24M", 0x044,
0145                     8, 7,       /* N */
0146                     0, 4,       /* M */
0147                     BIT(24),    /* frac enable */
0148                     BIT(25),    /* frac select */
0149                     270000000,  /* frac rate 0 */
0150                     297000000,  /* frac rate 1 */
0151                     BIT(31),    /* gate */
0152                     BIT(28),    /* lock */
0153                     CLK_SET_RATE_UNGATE);
0154
0155 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
0156                     "osc24M", 0x048,
0157                     8, 7,       /* N */
0158                     0, 4,       /* M */
0159                     BIT(24),    /* frac enable */
0160                     BIT(25),    /* frac select */
0161                     270000000,  /* frac rate 0 */
0162                     297000000,  /* frac rate 1 */
0163                     BIT(31),    /* gate */
0164                     BIT(28),    /* lock */
0165                     CLK_SET_RATE_UNGATE);
0166
0167 static struct ccu_mult pll_ddr1_clk = {
0168     .enable = BIT(31),
0169     .lock   = BIT(28),
0170     .mult   = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),
0171     .common = {
0172         .reg        = 0x04c,
0173         .hw.init    = CLK_HW_INIT("pll-ddr1", "osc24M",
0174                           &ccu_mult_ops,
0175                           CLK_SET_RATE_UNGATE),
0176     },
0177 };
0178
0179 static const char * const cpux_parents[] = { "osc32k", "osc24M",
0180                          "pll-cpux" , "pll-cpux" };
0181 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0182              0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
0183
0184 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
0185
0186 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
0187                          "axi" , "pll-periph" };
0188 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
0189     { .index = 3, .shift = 6, .width = 2 },
0190 };
0191 static struct ccu_div ahb1_clk = {
0192     .div        = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
0193
0194     .mux        = {
0195         .shift  = 12,
0196         .width  = 2,
0197
0198         .var_predivs    = ahb1_predivs,
0199         .n_var_predivs  = ARRAY_SIZE(ahb1_predivs),
0200     },
0201
0202     .common     = {
0203         .reg        = 0x054,
0204         .features   = CCU_FEATURE_VARIABLE_PREDIV,
0205         .hw.init    = CLK_HW_INIT_PARENTS("ahb1",
0206                               ahb1_parents,
0207                               &ccu_div_ops,
0208                               0),
0209     },
0210 };
0211
0212 static struct clk_div_table apb1_div_table[] = {
0213     { .val = 0, .div = 2 },
0214     { .val = 1, .div = 2 },
0215     { .val = 2, .div = 4 },
0216     { .val = 3, .div = 8 },
0217     { /* Sentinel */ },
0218 };
0219 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0220                0x054, 8, 2, apb1_div_table, 0);
0221
0222 static const char * const apb2_parents[] = { "osc32k", "osc24M",
0223                          "pll-periph" , "pll-periph" };
0224 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0225                  0, 5,  /* M */
0226                  16, 2, /* P */
0227                  24, 2, /* mux */
0228                  0);
0229
0230 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
0231               0x060, BIT(1), 0);
0232 static SUNXI_CCU_GATE(bus_ss_clk,   "bus-ss",   "ahb1",
0233               0x060, BIT(5), 0);
0234 static SUNXI_CCU_GATE(bus_dma_clk,  "bus-dma",  "ahb1",
0235               0x060, BIT(6), 0);
0236 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0237               0x060, BIT(8), 0);
0238 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0239               0x060, BIT(9), 0);
0240 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0241               0x060, BIT(10), 0);
0242 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
0243               0x060, BIT(13), 0);
0244 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0245               0x060, BIT(14), 0);
0246 static SUNXI_CCU_GATE(bus_hstimer_clk,  "bus-hstimer",  "ahb1",
0247               0x060, BIT(19), 0);
0248 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0249               0x060, BIT(20), 0);
0250 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
0251               0x060, BIT(21), 0);
0252 static SUNXI_CCU_GATE(bus_otg_clk,  "bus-otg",  "ahb1",
0253               0x060, BIT(24), 0);
0254 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
0255               0x060, BIT(26), 0);
0256 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
0257               0x060, BIT(29), 0);
0258
0259 static SUNXI_CCU_GATE(bus_ve_clk,   "bus-ve",   "ahb1",
0260               0x064, BIT(0), 0);
0261 static SUNXI_CCU_GATE(bus_lcd_clk,  "bus-lcd",  "ahb1",
0262               0x064, BIT(4), 0);
0263 static SUNXI_CCU_GATE(bus_csi_clk,  "bus-csi",  "ahb1",
0264               0x064, BIT(8), 0);
0265 static SUNXI_CCU_GATE(bus_de_be_clk,    "bus-de-be",    "ahb1",
0266               0x064, BIT(12), 0);
0267 static SUNXI_CCU_GATE(bus_de_fe_clk,    "bus-de-fe",    "ahb1",
0268               0x064, BIT(14), 0);
0269 static SUNXI_CCU_GATE(bus_gpu_clk,  "bus-gpu",  "ahb1",
0270               0x064, BIT(20), 0);
0271 static SUNXI_CCU_GATE(bus_msgbox_clk,   "bus-msgbox",   "ahb1",
0272               0x064, BIT(21), 0);
0273 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0274               0x064, BIT(22), 0);
0275 static SUNXI_CCU_GATE(bus_drc_clk,  "bus-drc",  "ahb1",
0276               0x064, BIT(25), 0);
0277 static SUNXI_CCU_GATE(bus_sat_clk,  "bus-sat",  "ahb1",
0278               0x064, BIT(26), 0);
0279
0280 static SUNXI_CCU_GATE(bus_codec_clk,    "bus-codec",    "apb1",
0281               0x068, BIT(0), 0);
0282 static SUNXI_CCU_GATE(bus_pio_clk,  "bus-pio",  "apb1",
0283               0x068, BIT(5), 0);
0284 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0285               0x068, BIT(12), 0);
0286 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
0287               0x068, BIT(13), 0);
0288
0289 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0290               0x06c, BIT(0), 0);
0291 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0292               0x06c, BIT(1), 0);
0293 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0294               0x06c, BIT(2), 0);
0295 static SUNXI_CCU_GATE(bus_uart0_clk,    "bus-uart0",    "apb2",
0296               0x06c, BIT(16), 0);
0297 static SUNXI_CCU_GATE(bus_uart1_clk,    "bus-uart1",    "apb2",
0298               0x06c, BIT(17), 0);
0299 static SUNXI_CCU_GATE(bus_uart2_clk,    "bus-uart2",    "apb2",
0300               0x06c, BIT(18), 0);
0301 static SUNXI_CCU_GATE(bus_uart3_clk,    "bus-uart3",    "apb2",
0302               0x06c, BIT(19), 0);
0303 static SUNXI_CCU_GATE(bus_uart4_clk,    "bus-uart4",    "apb2",
0304               0x06c, BIT(20), 0);
0305
0306 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
0307 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0308                   0, 4,     /* M */
0309                   16, 2,    /* P */
0310                   24, 2,    /* mux */
0311                   BIT(31),  /* gate */
0312                   0);
0313
0314 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0315                   0, 4,     /* M */
0316                   16, 2,    /* P */
0317                   24, 2,    /* mux */
0318                   BIT(31),  /* gate */
0319                   0);
0320
0321 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
0322                0x088, 20, 3, 0);
0323 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
0324                0x088, 8, 3, 0);
0325
0326 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0327                   0, 4,     /* M */
0328                   16, 2,    /* P */
0329                   24, 2,    /* mux */
0330                   BIT(31),  /* gate */
0331                   0);
0332
0333 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
0334                0x08c, 20, 3, 0);
0335 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
0336                0x08c, 8, 3, 0);
0337
0338 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0339                   0, 4,     /* M */
0340                   16, 2,    /* P */
0341                   24, 2,    /* mux */
0342                   BIT(31),  /* gate */
0343                   0);
0344
0345 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
0346                0x090, 20, 3, 0);
0347 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
0348                0x090, 8, 3, 0);
0349
0350 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
0351                   0, 4,     /* M */
0352                   16, 2,    /* P */
0353                   24, 2,    /* mux */
0354                   BIT(31),  /* gate */
0355                   0);
0356
0357 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0358                   0, 4,     /* M */
0359                   16, 2,    /* P */
0360                   24, 2,    /* mux */
0361                   BIT(31),  /* gate */
0362                   0);
0363
0364 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0365                   0, 4,     /* M */
0366                   16, 2,    /* P */
0367                   24, 2,    /* mux */
0368                   BIT(31),  /* gate */
0369                   0);
0370
0371 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
0372                         "pll-audio-2x", "pll-audio" };
0373 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
0374                    0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0375
0376 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
0377                    0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0378
0379 /* TODO: the parent for most of the USB clocks is not known */
0380 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0381               0x0cc, BIT(8), 0);
0382 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0383               0x0cc, BIT(9), 0);
0384 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
0385               0x0cc, BIT(10), 0);
0386 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
0387               0x0cc, BIT(11), 0);
0388 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
0389               0x0cc, BIT(16), 0);
0390
0391 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
0392            0x0f4, 0, 4, CLK_IS_CRITICAL);
0393
0394 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
0395 static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
0396              0x0f8, 16, 1, 0);
0397
0398 static SUNXI_CCU_GATE(dram_ve_clk,  "dram-ve",  "dram",
0399               0x100, BIT(0), 0);
0400 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
0401               0x100, BIT(1), 0);
0402 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "dram",
0403               0x100, BIT(16), 0);
0404 static SUNXI_CCU_GATE(dram_de_fe_clk,   "dram-de-fe",   "dram",
0405               0x100, BIT(24), 0);
0406 static SUNXI_CCU_GATE(dram_de_be_clk,   "dram-de-be",   "dram",
0407               0x100, BIT(26), 0);
0408
0409 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
0410                        "pll-gpu", "pll-de" };
0411 static const u8 de_table[] = { 0, 2, 3, 5 };
0412 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
0413                        de_parents, de_table,
0414                        0x104, 0, 4, 24, 3, BIT(31), 0);
0415
0416 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
0417                        de_parents, de_table,
0418                        0x10c, 0, 4, 24, 3, BIT(31), 0);
0419
0420 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
0421                         "pll-mipi" };
0422 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
0423 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
0424                      lcd_ch0_parents, lcd_ch0_table,
0425                      0x118, 24, 3, BIT(31),
0426                      CLK_SET_RATE_PARENT);
0427
0428 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
0429 static const u8 lcd_ch1_table[] = { 0, 2 };
0430 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
0431                        lcd_ch1_parents, lcd_ch1_table,
0432                        0x12c, 0, 4, 24, 2, BIT(31), 0);
0433
0434 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
0435                          "pll-mipi", "pll-ve" };
0436 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
0437 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
0438                        csi_sclk_parents, csi_sclk_table,
0439                        0x134, 16, 4, 24, 3, BIT(31), 0);
0440
0441 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
0442                          "osc24M" };
0443 static const u8 csi_mclk_table[] = { 0, 3, 5 };
0444 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
0445                        csi_mclk_parents, csi_mclk_table,
0446                        0x134, 0, 5, 8, 3, BIT(15), 0);
0447
0448 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0449                  0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
0450
0451 static SUNXI_CCU_GATE(ac_dig_clk,   "ac-dig",   "pll-audio",
0452               0x140, BIT(31), CLK_SET_RATE_PARENT);
0453 static SUNXI_CCU_GATE(ac_dig_4x_clk,    "ac-dig-4x",    "pll-audio-4x",
0454               0x140, BIT(30), CLK_SET_RATE_PARENT);
0455 static SUNXI_CCU_GATE(avs_clk,      "avs",      "osc24M",
0456               0x144, BIT(31), 0);
0457
0458 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
0459                          "pll-ddr0", "pll-ddr1" };
0460 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0461                  0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
0462
0463 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
0464 static const u8 dsi_sclk_table[] = { 0, 2 };
0465 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
0466                        dsi_sclk_parents, dsi_sclk_table,
0467                        0x168, 16, 4, 24, 2, BIT(31), 0);
0468
0469 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
0470 static const u8 dsi_dphy_table[] = { 0, 2 };
0471 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
0472                        dsi_dphy_parents, dsi_dphy_table,
0473                        0x168, 0, 4, 8, 2, BIT(15), 0);
0474
0475 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
0476                        de_parents, de_table,
0477                        0x180, 0, 4, 24, 3, BIT(31), 0);
0478
0479 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0480                  0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
0481
0482 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
0483 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
0484                  0x1b0, 0, 3, 24, 2, BIT(31), 0);
0485
0486 static struct ccu_common *sun8i_a33_ccu_clks[] = {
0487     &pll_cpux_clk.common,
0488     &pll_audio_base_clk.common,
0489     &pll_video_clk.common,
0490     &pll_ve_clk.common,
0491     &pll_ddr0_clk.common,
0492     &pll_periph_clk.common,
0493     &pll_gpu_clk.common,
0494     &pll_mipi_clk.common,
0495     &pll_hsic_clk.common,
0496     &pll_de_clk.common,
0497     &pll_ddr1_clk.common,
0498     &pll_ddr_clk.common,
0499     &cpux_clk.common,
0500     &axi_clk.common,
0501     &ahb1_clk.common,
0502     &apb1_clk.common,
0503     &apb2_clk.common,
0504     &bus_mipi_dsi_clk.common,
0505     &bus_ss_clk.common,
0506     &bus_dma_clk.common,
0507     &bus_mmc0_clk.common,
0508     &bus_mmc1_clk.common,
0509     &bus_mmc2_clk.common,
0510     &bus_nand_clk.common,
0511     &bus_dram_clk.common,
0512     &bus_hstimer_clk.common,
0513     &bus_spi0_clk.common,
0514     &bus_spi1_clk.common,
0515     &bus_otg_clk.common,
0516     &bus_ehci_clk.common,
0517     &bus_ohci_clk.common,
0518     &bus_ve_clk.common,
0519     &bus_lcd_clk.common,
0520     &bus_csi_clk.common,
0521     &bus_de_fe_clk.common,
0522     &bus_de_be_clk.common,
0523     &bus_gpu_clk.common,
0524     &bus_msgbox_clk.common,
0525     &bus_spinlock_clk.common,
0526     &bus_drc_clk.common,
0527     &bus_sat_clk.common,
0528     &bus_codec_clk.common,
0529     &bus_pio_clk.common,
0530     &bus_i2s0_clk.common,
0531     &bus_i2s1_clk.common,
0532     &bus_i2c0_clk.common,
0533     &bus_i2c1_clk.common,
0534     &bus_i2c2_clk.common,
0535     &bus_uart0_clk.common,
0536     &bus_uart1_clk.common,
0537     &bus_uart2_clk.common,
0538     &bus_uart3_clk.common,
0539     &bus_uart4_clk.common,
0540     &nand_clk.common,
0541     &mmc0_clk.common,
0542     &mmc0_sample_clk.common,
0543     &mmc0_output_clk.common,
0544     &mmc1_clk.common,
0545     &mmc1_sample_clk.common,
0546     &mmc1_output_clk.common,
0547     &mmc2_clk.common,
0548     &mmc2_sample_clk.common,
0549     &mmc2_output_clk.common,
0550     &ss_clk.common,
0551     &spi0_clk.common,
0552     &spi1_clk.common,
0553     &i2s0_clk.common,
0554     &i2s1_clk.common,
0555     &usb_phy0_clk.common,
0556     &usb_phy1_clk.common,
0557     &usb_hsic_clk.common,
0558     &usb_hsic_12M_clk.common,
0559     &usb_ohci_clk.common,
0560     &dram_clk.common,
0561     &dram_ve_clk.common,
0562     &dram_csi_clk.common,
0563     &dram_drc_clk.common,
0564     &dram_de_fe_clk.common,
0565     &dram_de_be_clk.common,
0566     &de_be_clk.common,
0567     &de_fe_clk.common,
0568     &lcd_ch0_clk.common,
0569     &lcd_ch1_clk.common,
0570     &csi_sclk_clk.common,
0571     &csi_mclk_clk.common,
0572     &ve_clk.common,
0573     &ac_dig_clk.common,
0574     &ac_dig_4x_clk.common,
0575     &avs_clk.common,
0576     &mbus_clk.common,
0577     &dsi_sclk_clk.common,
0578     &dsi_dphy_clk.common,
0579     &drc_clk.common,
0580     &gpu_clk.common,
0581     &ats_clk.common,
0582 };
0583
0584 static const struct clk_hw *clk_parent_pll_audio[] = {
0585     &pll_audio_base_clk.common.hw
0586 };
0587
0588 /* We hardcode the divider to 1 for now */
0589 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
0590                 clk_parent_pll_audio,
0591                 1, 1, CLK_SET_RATE_PARENT);
0592 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
0593                 clk_parent_pll_audio,
0594                 2, 1, CLK_SET_RATE_PARENT);
0595 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
0596                 clk_parent_pll_audio,
0597                 1, 1, CLK_SET_RATE_PARENT);
0598 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
0599                 clk_parent_pll_audio,
0600                 1, 2, CLK_SET_RATE_PARENT);
0601 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
0602                &pll_periph_clk.common.hw,
0603                1, 2, 0);
0604 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
0605                &pll_video_clk.common.hw,
0606                1, 2, 0);
0607
0608 static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
0609     .hws    = {
0610         [CLK_PLL_CPUX]      = &pll_cpux_clk.common.hw,
0611         [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
0612         [CLK_PLL_AUDIO]     = &pll_audio_clk.hw,
0613         [CLK_PLL_AUDIO_2X]  = &pll_audio_2x_clk.hw,
0614         [CLK_PLL_AUDIO_4X]  = &pll_audio_4x_clk.hw,
0615         [CLK_PLL_AUDIO_8X]  = &pll_audio_8x_clk.hw,
0616         [CLK_PLL_VIDEO]     = &pll_video_clk.common.hw,
0617         [CLK_PLL_VIDEO_2X]  = &pll_video_2x_clk.hw,
0618         [CLK_PLL_VE]        = &pll_ve_clk.common.hw,
0619         [CLK_PLL_DDR0]      = &pll_ddr0_clk.common.hw,
0620         [CLK_PLL_PERIPH]    = &pll_periph_clk.common.hw,
0621         [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
0622         [CLK_PLL_GPU]       = &pll_gpu_clk.common.hw,
0623         [CLK_PLL_MIPI]      = &pll_mipi_clk.common.hw,
0624         [CLK_PLL_HSIC]      = &pll_hsic_clk.common.hw,
0625         [CLK_PLL_DE]        = &pll_de_clk.common.hw,
0626         [CLK_PLL_DDR1]      = &pll_ddr1_clk.common.hw,
0627         [CLK_PLL_DDR]       = &pll_ddr_clk.common.hw,
0628         [CLK_CPUX]      = &cpux_clk.common.hw,
0629         [CLK_AXI]       = &axi_clk.common.hw,
0630         [CLK_AHB1]      = &ahb1_clk.common.hw,
0631         [CLK_APB1]      = &apb1_clk.common.hw,
0632         [CLK_APB2]      = &apb2_clk.common.hw,
0633         [CLK_BUS_MIPI_DSI]  = &bus_mipi_dsi_clk.common.hw,
0634         [CLK_BUS_SS]        = &bus_ss_clk.common.hw,
0635         [CLK_BUS_DMA]       = &bus_dma_clk.common.hw,
0636         [CLK_BUS_MMC0]      = &bus_mmc0_clk.common.hw,
0637         [CLK_BUS_MMC1]      = &bus_mmc1_clk.common.hw,
0638         [CLK_BUS_MMC2]      = &bus_mmc2_clk.common.hw,
0639         [CLK_BUS_NAND]      = &bus_nand_clk.common.hw,
0640         [CLK_BUS_DRAM]      = &bus_dram_clk.common.hw,
0641         [CLK_BUS_HSTIMER]   = &bus_hstimer_clk.common.hw,
0642         [CLK_BUS_SPI0]      = &bus_spi0_clk.common.hw,
0643         [CLK_BUS_SPI1]      = &bus_spi1_clk.common.hw,
0644         [CLK_BUS_OTG]       = &bus_otg_clk.common.hw,
0645         [CLK_BUS_EHCI]      = &bus_ehci_clk.common.hw,
0646         [CLK_BUS_OHCI]      = &bus_ohci_clk.common.hw,
0647         [CLK_BUS_VE]        = &bus_ve_clk.common.hw,
0648         [CLK_BUS_LCD]       = &bus_lcd_clk.common.hw,
0649         [CLK_BUS_CSI]       = &bus_csi_clk.common.hw,
0650         [CLK_BUS_DE_BE]     = &bus_de_be_clk.common.hw,
0651         [CLK_BUS_DE_FE]     = &bus_de_fe_clk.common.hw,
0652         [CLK_BUS_GPU]       = &bus_gpu_clk.common.hw,
0653         [CLK_BUS_MSGBOX]    = &bus_msgbox_clk.common.hw,
0654         [CLK_BUS_SPINLOCK]  = &bus_spinlock_clk.common.hw,
0655         [CLK_BUS_DRC]       = &bus_drc_clk.common.hw,
0656         [CLK_BUS_SAT]       = &bus_sat_clk.common.hw,
0657         [CLK_BUS_CODEC]     = &bus_codec_clk.common.hw,
0658         [CLK_BUS_PIO]       = &bus_pio_clk.common.hw,
0659         [CLK_BUS_I2S0]      = &bus_i2s0_clk.common.hw,
0660         [CLK_BUS_I2S1]      = &bus_i2s1_clk.common.hw,
0661         [CLK_BUS_I2C0]      = &bus_i2c0_clk.common.hw,
0662         [CLK_BUS_I2C1]      = &bus_i2c1_clk.common.hw,
0663         [CLK_BUS_I2C2]      = &bus_i2c2_clk.common.hw,
0664         [CLK_BUS_UART0]     = &bus_uart0_clk.common.hw,
0665         [CLK_BUS_UART1]     = &bus_uart1_clk.common.hw,
0666         [CLK_BUS_UART2]     = &bus_uart2_clk.common.hw,
0667         [CLK_BUS_UART3]     = &bus_uart3_clk.common.hw,
0668         [CLK_BUS_UART4]     = &bus_uart4_clk.common.hw,
0669         [CLK_NAND]      = &nand_clk.common.hw,
0670         [CLK_MMC0]      = &mmc0_clk.common.hw,
0671         [CLK_MMC0_SAMPLE]   = &mmc0_sample_clk.common.hw,
0672         [CLK_MMC0_OUTPUT]   = &mmc0_output_clk.common.hw,
0673         [CLK_MMC1]      = &mmc1_clk.common.hw,
0674         [CLK_MMC1_SAMPLE]   = &mmc1_sample_clk.common.hw,
0675         [CLK_MMC1_OUTPUT]   = &mmc1_output_clk.common.hw,
0676         [CLK_MMC2]      = &mmc2_clk.common.hw,
0677         [CLK_MMC2_SAMPLE]   = &mmc2_sample_clk.common.hw,
0678         [CLK_MMC2_OUTPUT]   = &mmc2_output_clk.common.hw,
0679         [CLK_SS]        = &ss_clk.common.hw,
0680         [CLK_SPI0]      = &spi0_clk.common.hw,
0681         [CLK_SPI1]      = &spi1_clk.common.hw,
0682         [CLK_I2S0]      = &i2s0_clk.common.hw,
0683         [CLK_I2S1]      = &i2s1_clk.common.hw,
0684         [CLK_USB_PHY0]      = &usb_phy0_clk.common.hw,
0685         [CLK_USB_PHY1]      = &usb_phy1_clk.common.hw,
0686         [CLK_USB_HSIC]      = &usb_hsic_clk.common.hw,
0687         [CLK_USB_HSIC_12M]  = &usb_hsic_12M_clk.common.hw,
0688         [CLK_USB_OHCI]      = &usb_ohci_clk.common.hw,
0689         [CLK_DRAM]      = &dram_clk.common.hw,
0690         [CLK_DRAM_VE]       = &dram_ve_clk.common.hw,
0691         [CLK_DRAM_CSI]      = &dram_csi_clk.common.hw,
0692         [CLK_DRAM_DRC]      = &dram_drc_clk.common.hw,
0693         [CLK_DRAM_DE_FE]    = &dram_de_fe_clk.common.hw,
0694         [CLK_DRAM_DE_BE]    = &dram_de_be_clk.common.hw,
0695         [CLK_DE_BE]     = &de_be_clk.common.hw,
0696         [CLK_DE_FE]     = &de_fe_clk.common.hw,
0697         [CLK_LCD_CH0]       = &lcd_ch0_clk.common.hw,
0698         [CLK_LCD_CH1]       = &lcd_ch1_clk.common.hw,
0699         [CLK_CSI_SCLK]      = &csi_sclk_clk.common.hw,
0700         [CLK_CSI_MCLK]      = &csi_mclk_clk.common.hw,
0701         [CLK_VE]        = &ve_clk.common.hw,
0702         [CLK_AC_DIG]        = &ac_dig_clk.common.hw,
0703         [CLK_AC_DIG_4X]     = &ac_dig_4x_clk.common.hw,
0704         [CLK_AVS]       = &avs_clk.common.hw,
0705         [CLK_MBUS]      = &mbus_clk.common.hw,
0706         [CLK_DSI_SCLK]      = &dsi_sclk_clk.common.hw,
0707         [CLK_DSI_DPHY]      = &dsi_dphy_clk.common.hw,
0708         [CLK_DRC]       = &drc_clk.common.hw,
0709         [CLK_GPU]       = &gpu_clk.common.hw,
0710         [CLK_ATS]       = &ats_clk.common.hw,
0711     },
0712     .num    = CLK_NUMBER,
0713 };
0714
0715 static struct ccu_reset_map sun8i_a33_ccu_resets[] = {
0716     [RST_USB_PHY0]      =  { 0x0cc, BIT(0) },
0717     [RST_USB_PHY1]      =  { 0x0cc, BIT(1) },
0718     [RST_USB_HSIC]      =  { 0x0cc, BIT(2) },
0719
0720     [RST_MBUS]      =  { 0x0fc, BIT(31) },
0721
0722     [RST_BUS_MIPI_DSI]  =  { 0x2c0, BIT(1) },
0723     [RST_BUS_SS]        =  { 0x2c0, BIT(5) },
0724     [RST_BUS_DMA]       =  { 0x2c0, BIT(6) },
0725     [RST_BUS_MMC0]      =  { 0x2c0, BIT(8) },
0726     [RST_BUS_MMC1]      =  { 0x2c0, BIT(9) },
0727     [RST_BUS_MMC2]      =  { 0x2c0, BIT(10) },
0728     [RST_BUS_NAND]      =  { 0x2c0, BIT(13) },
0729     [RST_BUS_DRAM]      =  { 0x2c0, BIT(14) },
0730     [RST_BUS_HSTIMER]   =  { 0x2c0, BIT(19) },
0731     [RST_BUS_SPI0]      =  { 0x2c0, BIT(20) },
0732     [RST_BUS_SPI1]      =  { 0x2c0, BIT(21) },
0733     [RST_BUS_OTG]       =  { 0x2c0, BIT(24) },
0734     [RST_BUS_EHCI]      =  { 0x2c0, BIT(26) },
0735     [RST_BUS_OHCI]      =  { 0x2c0, BIT(29) },
0736
0737     [RST_BUS_VE]        =  { 0x2c4, BIT(0) },
0738     [RST_BUS_LCD]       =  { 0x2c4, BIT(4) },
0739     [RST_BUS_CSI]       =  { 0x2c4, BIT(8) },
0740     [RST_BUS_DE_BE]     =  { 0x2c4, BIT(12) },
0741     [RST_BUS_DE_FE]     =  { 0x2c4, BIT(14) },
0742     [RST_BUS_GPU]       =  { 0x2c4, BIT(20) },
0743     [RST_BUS_MSGBOX]    =  { 0x2c4, BIT(21) },
0744     [RST_BUS_SPINLOCK]  =  { 0x2c4, BIT(22) },
0745     [RST_BUS_DRC]       =  { 0x2c4, BIT(25) },
0746     [RST_BUS_SAT]       =  { 0x2c4, BIT(26) },
0747
0748     [RST_BUS_LVDS]      =  { 0x2c8, BIT(0) },
0749
0750     [RST_BUS_CODEC]     =  { 0x2d0, BIT(0) },
0751     [RST_BUS_I2S0]      =  { 0x2d0, BIT(12) },
0752     [RST_BUS_I2S1]      =  { 0x2d0, BIT(13) },
0753
0754     [RST_BUS_I2C0]      =  { 0x2d8, BIT(0) },
0755     [RST_BUS_I2C1]      =  { 0x2d8, BIT(1) },
0756     [RST_BUS_I2C2]      =  { 0x2d8, BIT(2) },
0757     [RST_BUS_UART0]     =  { 0x2d8, BIT(16) },
0758     [RST_BUS_UART1]     =  { 0x2d8, BIT(17) },
0759     [RST_BUS_UART2]     =  { 0x2d8, BIT(18) },
0760     [RST_BUS_UART3]     =  { 0x2d8, BIT(19) },
0761     [RST_BUS_UART4]     =  { 0x2d8, BIT(20) },
0762 };
0763
0764 static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
0765     .ccu_clks   = sun8i_a33_ccu_clks,
0766     .num_ccu_clks   = ARRAY_SIZE(sun8i_a33_ccu_clks),
0767
0768     .hw_clks    = &sun8i_a33_hw_clks,
0769
0770     .resets     = sun8i_a33_ccu_resets,
0771     .num_resets = ARRAY_SIZE(sun8i_a33_ccu_resets),
0772 };
0773
0774 static struct ccu_pll_nb sun8i_a33_pll_cpu_nb = {
0775     .common = &pll_cpux_clk.common,
0776     /* copy from pll_cpux_clk */
0777     .enable = BIT(31),
0778     .lock   = BIT(28),
0779 };
0780
0781 static struct ccu_mux_nb sun8i_a33_cpu_nb = {
0782     .common     = &cpux_clk.common,
0783     .cm     = &cpux_clk.mux,
0784     .delay_us   = 1, /* > 8 clock cycles at 24 MHz */
0785     .bypass_index   = 1, /* index of 24 MHz oscillator */
0786 };
0787
0788 static int sun8i_a33_ccu_probe(struct platform_device *pdev)
0789 {
0790     void __iomem *reg;
0791     int ret;
0792     u32 val;
0793
0794     reg = devm_platform_ioremap_resource(pdev, 0);
0795     if (IS_ERR(reg))
0796         return PTR_ERR(reg);
0797
0798     /* Force the PLL-Audio-1x divider to 1 */
0799     val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
0800     val &= ~GENMASK(19, 16);
0801     writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
0802
0803     /* Force PLL-MIPI to MIPI mode */
0804     val = readl(reg + SUN8I_A33_PLL_MIPI_REG);
0805     val &= ~BIT(16);
0806     writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
0807
0808     ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a33_ccu_desc);
0809     if (ret)
0810         return ret;
0811
0812     /* Gate then ungate PLL CPU after any rate changes */
0813     ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
0814
0815     /* Reparent CPU during PLL CPU rate changes */
0816     ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
0817                   &sun8i_a33_cpu_nb);
0818
0819     return 0;
0820 }
0821
0822 static const struct of_device_id sun8i_a33_ccu_ids[] = {
0823     { .compatible = "allwinner,sun8i-a33-ccu" },
0824     { }
0825 };
0826
0827 static struct platform_driver sun8i_a33_ccu_driver = {
0828     .probe  = sun8i_a33_ccu_probe,
0829     .driver = {
0830         .name           = "sun8i-a33-ccu",
0831         .suppress_bind_attrs    = true,
0832         .of_match_table     = sun8i_a33_ccu_ids,
0833     },
0834 };
0835 module_platform_driver(sun8i_a33_ccu_driver);
0836
0837 MODULE_IMPORT_NS(SUNXI_CCU);
0838 MODULE_LICENSE("GPL");