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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
0004  */
0005 
0006 #include <linux/clk-provider.h>
0007 #include <linux/io.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 
0011 #include "ccu_common.h"
0012 #include "ccu_reset.h"
0013 
0014 #include "ccu_div.h"
0015 #include "ccu_gate.h"
0016 #include "ccu_mp.h"
0017 #include "ccu_mult.h"
0018 #include "ccu_nk.h"
0019 #include "ccu_nkm.h"
0020 #include "ccu_nkmp.h"
0021 #include "ccu_nm.h"
0022 #include "ccu_phase.h"
0023 #include "ccu_sdm.h"
0024 
0025 #include "ccu-sun8i-a23-a33.h"
0026 
0027 
0028 static struct ccu_nkmp pll_cpux_clk = {
0029     .enable = BIT(31),
0030     .lock   = BIT(28),
0031 
0032     .n  = _SUNXI_CCU_MULT(8, 5),
0033     .k  = _SUNXI_CCU_MULT(4, 2),
0034     .m  = _SUNXI_CCU_DIV(0, 2),
0035     .p  = _SUNXI_CCU_DIV_MAX(16, 2, 4),
0036 
0037     .common = {
0038         .reg        = 0x000,
0039         .hw.init    = CLK_HW_INIT("pll-cpux", "osc24M",
0040                           &ccu_nkmp_ops,
0041                           0),
0042     },
0043 };
0044 
0045 /*
0046  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
0047  * the base (2x, 4x and 8x), and one variable divider (the one true
0048  * pll audio).
0049  *
0050  * With sigma-delta modulation for fractional-N on the audio PLL,
0051  * we have to use specific dividers. This means the variable divider
0052  * can no longer be used, as the audio codec requests the exact clock
0053  * rates we support through this mechanism. So we now hard code the
0054  * variable divider to 1. This means the clock rates will no longer
0055  * match the clock names.
0056  */
0057 #define SUN8I_A23_PLL_AUDIO_REG 0x008
0058 
0059 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
0060     { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
0061     { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
0062 };
0063 
0064 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
0065                        "osc24M", 0x008,
0066                        8, 7,    /* N */
0067                        0, 5,    /* M */
0068                        pll_audio_sdm_table, BIT(24),
0069                        0x284, BIT(31),
0070                        BIT(31), /* gate */
0071                        BIT(28), /* lock */
0072                        CLK_SET_RATE_UNGATE);
0073 
0074 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
0075                     "osc24M", 0x010,
0076                     8, 7,       /* N */
0077                     0, 4,       /* M */
0078                     BIT(24),    /* frac enable */
0079                     BIT(25),    /* frac select */
0080                     270000000,  /* frac rate 0 */
0081                     297000000,  /* frac rate 1 */
0082                     BIT(31),    /* gate */
0083                     BIT(28),    /* lock */
0084                     CLK_SET_RATE_UNGATE);
0085 
0086 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
0087                     "osc24M", 0x018,
0088                     8, 7,       /* N */
0089                     0, 4,       /* M */
0090                     BIT(24),    /* frac enable */
0091                     BIT(25),    /* frac select */
0092                     270000000,  /* frac rate 0 */
0093                     297000000,  /* frac rate 1 */
0094                     BIT(31),    /* gate */
0095                     BIT(28),    /* lock */
0096                     CLK_SET_RATE_UNGATE);
0097 
0098 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
0099                     "osc24M", 0x020,
0100                     8, 5,       /* N */
0101                     4, 2,       /* K */
0102                     0, 2,       /* M */
0103                     BIT(31),        /* gate */
0104                     BIT(28),        /* lock */
0105                     0);
0106 
0107 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
0108                        "osc24M", 0x028,
0109                        8, 5,    /* N */
0110                        4, 2,    /* K */
0111                        BIT(31), /* gate */
0112                        BIT(28), /* lock */
0113                        2,       /* post-div */
0114                        CLK_SET_RATE_UNGATE);
0115 
0116 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
0117                     "osc24M", 0x038,
0118                     8, 7,       /* N */
0119                     0, 4,       /* M */
0120                     BIT(24),    /* frac enable */
0121                     BIT(25),    /* frac select */
0122                     270000000,  /* frac rate 0 */
0123                     297000000,  /* frac rate 1 */
0124                     BIT(31),    /* gate */
0125                     BIT(28),    /* lock */
0126                     CLK_SET_RATE_UNGATE);
0127 
0128 /*
0129  * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
0130  *
0131  * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
0132  * integer / fractional clock with switchable multipliers and dividers.
0133  * This is not supported here. We hardcode the PLL to MIPI mode.
0134  */
0135 #define SUN8I_A23_PLL_MIPI_REG  0x040
0136 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
0137                     "pll-video", 0x040,
0138                     8, 4,       /* N */
0139                     4, 2,       /* K */
0140                     0, 4,       /* M */
0141                     BIT(31) | BIT(23) | BIT(22), /* gate */
0142                     BIT(28),        /* lock */
0143                     CLK_SET_RATE_UNGATE);
0144 
0145 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
0146                     "osc24M", 0x044,
0147                     8, 7,       /* N */
0148                     0, 4,       /* M */
0149                     BIT(24),    /* frac enable */
0150                     BIT(25),    /* frac select */
0151                     270000000,  /* frac rate 0 */
0152                     297000000,  /* frac rate 1 */
0153                     BIT(31),    /* gate */
0154                     BIT(28),    /* lock */
0155                     CLK_SET_RATE_UNGATE);
0156 
0157 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
0158                     "osc24M", 0x048,
0159                     8, 7,       /* N */
0160                     0, 4,       /* M */
0161                     BIT(24),    /* frac enable */
0162                     BIT(25),    /* frac select */
0163                     270000000,  /* frac rate 0 */
0164                     297000000,  /* frac rate 1 */
0165                     BIT(31),    /* gate */
0166                     BIT(28),    /* lock */
0167                     CLK_SET_RATE_UNGATE);
0168 
0169 static const char * const cpux_parents[] = { "osc32k", "osc24M",
0170                          "pll-cpux" , "pll-cpux" };
0171 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0172              0x050, 16, 2, CLK_IS_CRITICAL);
0173 
0174 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
0175 
0176 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
0177                          "axi" , "pll-periph" };
0178 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
0179     { .index = 3, .shift = 6, .width = 2 },
0180 };
0181 static struct ccu_div ahb1_clk = {
0182     .div        = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
0183 
0184     .mux        = {
0185         .shift  = 12,
0186         .width  = 2,
0187 
0188         .var_predivs    = ahb1_predivs,
0189         .n_var_predivs  = ARRAY_SIZE(ahb1_predivs),
0190     },
0191 
0192     .common     = {
0193         .reg        = 0x054,
0194         .features   = CCU_FEATURE_VARIABLE_PREDIV,
0195         .hw.init    = CLK_HW_INIT_PARENTS("ahb1",
0196                               ahb1_parents,
0197                               &ccu_div_ops,
0198                               0),
0199     },
0200 };
0201 
0202 static struct clk_div_table apb1_div_table[] = {
0203     { .val = 0, .div = 2 },
0204     { .val = 1, .div = 2 },
0205     { .val = 2, .div = 4 },
0206     { .val = 3, .div = 8 },
0207     { /* Sentinel */ },
0208 };
0209 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0210                0x054, 8, 2, apb1_div_table, 0);
0211 
0212 static const char * const apb2_parents[] = { "osc32k", "osc24M",
0213                          "pll-periph" , "pll-periph" };
0214 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0215                  0, 5,  /* M */
0216                  16, 2, /* P */
0217                  24, 2, /* mux */
0218                  0);
0219 
0220 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
0221               0x060, BIT(1), 0);
0222 static SUNXI_CCU_GATE(bus_dma_clk,  "bus-dma",  "ahb1",
0223               0x060, BIT(6), 0);
0224 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0225               0x060, BIT(8), 0);
0226 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0227               0x060, BIT(9), 0);
0228 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0229               0x060, BIT(10), 0);
0230 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
0231               0x060, BIT(13), 0);
0232 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0233               0x060, BIT(14), 0);
0234 static SUNXI_CCU_GATE(bus_hstimer_clk,  "bus-hstimer",  "ahb1",
0235               0x060, BIT(19), 0);
0236 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0237               0x060, BIT(20), 0);
0238 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
0239               0x060, BIT(21), 0);
0240 static SUNXI_CCU_GATE(bus_otg_clk,  "bus-otg",  "ahb1",
0241               0x060, BIT(24), 0);
0242 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
0243               0x060, BIT(26), 0);
0244 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
0245               0x060, BIT(29), 0);
0246 
0247 static SUNXI_CCU_GATE(bus_ve_clk,   "bus-ve",   "ahb1",
0248               0x064, BIT(0), 0);
0249 static SUNXI_CCU_GATE(bus_lcd_clk,  "bus-lcd",  "ahb1",
0250               0x064, BIT(4), 0);
0251 static SUNXI_CCU_GATE(bus_csi_clk,  "bus-csi",  "ahb1",
0252               0x064, BIT(8), 0);
0253 static SUNXI_CCU_GATE(bus_de_be_clk,    "bus-de-be",    "ahb1",
0254               0x064, BIT(12), 0);
0255 static SUNXI_CCU_GATE(bus_de_fe_clk,    "bus-de-fe",    "ahb1",
0256               0x064, BIT(14), 0);
0257 static SUNXI_CCU_GATE(bus_gpu_clk,  "bus-gpu",  "ahb1",
0258               0x064, BIT(20), 0);
0259 static SUNXI_CCU_GATE(bus_msgbox_clk,   "bus-msgbox",   "ahb1",
0260               0x064, BIT(21), 0);
0261 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0262               0x064, BIT(22), 0);
0263 static SUNXI_CCU_GATE(bus_drc_clk,  "bus-drc",  "ahb1",
0264               0x064, BIT(25), 0);
0265 
0266 static SUNXI_CCU_GATE(bus_codec_clk,    "bus-codec",    "apb1",
0267               0x068, BIT(0), 0);
0268 static SUNXI_CCU_GATE(bus_pio_clk,  "bus-pio",  "apb1",
0269               0x068, BIT(5), 0);
0270 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0271               0x068, BIT(12), 0);
0272 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
0273               0x068, BIT(13), 0);
0274 
0275 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0276               0x06c, BIT(0), 0);
0277 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0278               0x06c, BIT(1), 0);
0279 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0280               0x06c, BIT(2), 0);
0281 static SUNXI_CCU_GATE(bus_uart0_clk,    "bus-uart0",    "apb2",
0282               0x06c, BIT(16), 0);
0283 static SUNXI_CCU_GATE(bus_uart1_clk,    "bus-uart1",    "apb2",
0284               0x06c, BIT(17), 0);
0285 static SUNXI_CCU_GATE(bus_uart2_clk,    "bus-uart2",    "apb2",
0286               0x06c, BIT(18), 0);
0287 static SUNXI_CCU_GATE(bus_uart3_clk,    "bus-uart3",    "apb2",
0288               0x06c, BIT(19), 0);
0289 static SUNXI_CCU_GATE(bus_uart4_clk,    "bus-uart4",    "apb2",
0290               0x06c, BIT(20), 0);
0291 
0292 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
0293 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0294                   0, 4,     /* M */
0295                   16, 2,    /* P */
0296                   24, 2,    /* mux */
0297                   BIT(31),  /* gate */
0298                   0);
0299 
0300 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0301                   0, 4,     /* M */
0302                   16, 2,    /* P */
0303                   24, 2,    /* mux */
0304                   BIT(31),  /* gate */
0305                   0);
0306 
0307 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
0308                0x088, 20, 3, 0);
0309 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
0310                0x088, 8, 3, 0);
0311 
0312 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0313                   0, 4,     /* M */
0314                   16, 2,    /* P */
0315                   24, 2,    /* mux */
0316                   BIT(31),  /* gate */
0317                   0);
0318 
0319 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
0320                0x08c, 20, 3, 0);
0321 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
0322                0x08c, 8, 3, 0);
0323 
0324 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0325                   0, 4,     /* M */
0326                   16, 2,    /* P */
0327                   24, 2,    /* mux */
0328                   BIT(31),  /* gate */
0329                   0);
0330 
0331 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
0332                0x090, 20, 3, 0);
0333 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
0334                0x090, 8, 3, 0);
0335 
0336 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0337                   0, 4,     /* M */
0338                   16, 2,    /* P */
0339                   24, 2,    /* mux */
0340                   BIT(31),  /* gate */
0341                   0);
0342 
0343 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0344                   0, 4,     /* M */
0345                   16, 2,    /* P */
0346                   24, 2,    /* mux */
0347                   BIT(31),  /* gate */
0348                   0);
0349 
0350 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
0351                         "pll-audio-2x", "pll-audio" };
0352 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
0353                    0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0354 
0355 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
0356                    0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0357 
0358 /* TODO: the parent for most of the USB clocks is not known */
0359 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0360               0x0cc, BIT(8), 0);
0361 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0362               0x0cc, BIT(9), 0);
0363 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
0364               0x0cc, BIT(10), 0);
0365 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
0366               0x0cc, BIT(11), 0);
0367 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
0368               0x0cc, BIT(16), 0);
0369 
0370 static SUNXI_CCU_GATE(dram_ve_clk,  "dram-ve",  "pll-ddr",
0371               0x100, BIT(0), 0);
0372 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
0373               0x100, BIT(1), 0);
0374 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "pll-ddr",
0375               0x100, BIT(16), 0);
0376 static SUNXI_CCU_GATE(dram_de_fe_clk,   "dram-de-fe",   "pll-ddr",
0377               0x100, BIT(24), 0);
0378 static SUNXI_CCU_GATE(dram_de_be_clk,   "dram-de-be",   "pll-ddr",
0379               0x100, BIT(26), 0);
0380 
0381 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
0382                        "pll-gpu", "pll-de" };
0383 static const u8 de_table[] = { 0, 2, 3, 5 };
0384 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
0385                        de_parents, de_table,
0386                        0x104, 0, 4, 24, 3, BIT(31), 0);
0387 
0388 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
0389                        de_parents, de_table,
0390                        0x10c, 0, 4, 24, 3, BIT(31), 0);
0391 
0392 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
0393                         "pll-mipi" };
0394 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
0395 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
0396                      lcd_ch0_parents, lcd_ch0_table,
0397                      0x118, 24, 3, BIT(31),
0398                      CLK_SET_RATE_PARENT);
0399 
0400 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
0401 static const u8 lcd_ch1_table[] = { 0, 2 };
0402 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
0403                        lcd_ch1_parents, lcd_ch1_table,
0404                        0x12c, 0, 4, 24, 2, BIT(31), 0);
0405 
0406 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
0407                          "pll-mipi", "pll-ve" };
0408 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
0409 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
0410                        csi_sclk_parents, csi_sclk_table,
0411                        0x134, 16, 4, 24, 3, BIT(31), 0);
0412 
0413 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
0414                          "osc24M" };
0415 static const u8 csi_mclk_table[] = { 0, 3, 5 };
0416 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
0417                        csi_mclk_parents, csi_mclk_table,
0418                        0x134, 0, 5, 8, 3, BIT(15), 0);
0419 
0420 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0421                  0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
0422 
0423 static SUNXI_CCU_GATE(ac_dig_clk,   "ac-dig",   "pll-audio",
0424               0x140, BIT(31), CLK_SET_RATE_PARENT);
0425 static SUNXI_CCU_GATE(avs_clk,      "avs",      "osc24M",
0426               0x144, BIT(31), 0);
0427 
0428 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
0429                          "pll-ddr" };
0430 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0431                  0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
0432 
0433 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
0434 static const u8 dsi_sclk_table[] = { 0, 2 };
0435 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
0436                        dsi_sclk_parents, dsi_sclk_table,
0437                        0x168, 16, 4, 24, 2, BIT(31), 0);
0438 
0439 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
0440 static const u8 dsi_dphy_table[] = { 0, 2 };
0441 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
0442                        dsi_dphy_parents, dsi_dphy_table,
0443                        0x168, 0, 4, 8, 2, BIT(15), 0);
0444 
0445 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
0446                        de_parents, de_table,
0447                        0x180, 0, 4, 24, 3, BIT(31), 0);
0448 
0449 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0450                  0x1a0, 0, 3, BIT(31), 0);
0451 
0452 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
0453 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
0454                  0x1b0, 0, 3, 24, 2, BIT(31), 0);
0455 
0456 static struct ccu_common *sun8i_a23_ccu_clks[] = {
0457     &pll_cpux_clk.common,
0458     &pll_audio_base_clk.common,
0459     &pll_video_clk.common,
0460     &pll_ve_clk.common,
0461     &pll_ddr_clk.common,
0462     &pll_periph_clk.common,
0463     &pll_gpu_clk.common,
0464     &pll_mipi_clk.common,
0465     &pll_hsic_clk.common,
0466     &pll_de_clk.common,
0467     &cpux_clk.common,
0468     &axi_clk.common,
0469     &ahb1_clk.common,
0470     &apb1_clk.common,
0471     &apb2_clk.common,
0472     &bus_mipi_dsi_clk.common,
0473     &bus_dma_clk.common,
0474     &bus_mmc0_clk.common,
0475     &bus_mmc1_clk.common,
0476     &bus_mmc2_clk.common,
0477     &bus_nand_clk.common,
0478     &bus_dram_clk.common,
0479     &bus_hstimer_clk.common,
0480     &bus_spi0_clk.common,
0481     &bus_spi1_clk.common,
0482     &bus_otg_clk.common,
0483     &bus_ehci_clk.common,
0484     &bus_ohci_clk.common,
0485     &bus_ve_clk.common,
0486     &bus_lcd_clk.common,
0487     &bus_csi_clk.common,
0488     &bus_de_fe_clk.common,
0489     &bus_de_be_clk.common,
0490     &bus_gpu_clk.common,
0491     &bus_msgbox_clk.common,
0492     &bus_spinlock_clk.common,
0493     &bus_drc_clk.common,
0494     &bus_codec_clk.common,
0495     &bus_pio_clk.common,
0496     &bus_i2s0_clk.common,
0497     &bus_i2s1_clk.common,
0498     &bus_i2c0_clk.common,
0499     &bus_i2c1_clk.common,
0500     &bus_i2c2_clk.common,
0501     &bus_uart0_clk.common,
0502     &bus_uart1_clk.common,
0503     &bus_uart2_clk.common,
0504     &bus_uart3_clk.common,
0505     &bus_uart4_clk.common,
0506     &nand_clk.common,
0507     &mmc0_clk.common,
0508     &mmc0_sample_clk.common,
0509     &mmc0_output_clk.common,
0510     &mmc1_clk.common,
0511     &mmc1_sample_clk.common,
0512     &mmc1_output_clk.common,
0513     &mmc2_clk.common,
0514     &mmc2_sample_clk.common,
0515     &mmc2_output_clk.common,
0516     &spi0_clk.common,
0517     &spi1_clk.common,
0518     &i2s0_clk.common,
0519     &i2s1_clk.common,
0520     &usb_phy0_clk.common,
0521     &usb_phy1_clk.common,
0522     &usb_hsic_clk.common,
0523     &usb_hsic_12M_clk.common,
0524     &usb_ohci_clk.common,
0525     &dram_ve_clk.common,
0526     &dram_csi_clk.common,
0527     &dram_drc_clk.common,
0528     &dram_de_fe_clk.common,
0529     &dram_de_be_clk.common,
0530     &de_be_clk.common,
0531     &de_fe_clk.common,
0532     &lcd_ch0_clk.common,
0533     &lcd_ch1_clk.common,
0534     &csi_sclk_clk.common,
0535     &csi_mclk_clk.common,
0536     &ve_clk.common,
0537     &ac_dig_clk.common,
0538     &avs_clk.common,
0539     &mbus_clk.common,
0540     &dsi_sclk_clk.common,
0541     &dsi_dphy_clk.common,
0542     &drc_clk.common,
0543     &gpu_clk.common,
0544     &ats_clk.common,
0545 };
0546 
0547 static const struct clk_hw *clk_parent_pll_audio[] = {
0548     &pll_audio_base_clk.common.hw
0549 };
0550 
0551 /* We hardcode the divider to 1 for now */
0552 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
0553                 clk_parent_pll_audio,
0554                 1, 1, CLK_SET_RATE_PARENT);
0555 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
0556                 clk_parent_pll_audio,
0557                 2, 1, CLK_SET_RATE_PARENT);
0558 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
0559                 clk_parent_pll_audio,
0560                 1, 1, CLK_SET_RATE_PARENT);
0561 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
0562                 clk_parent_pll_audio,
0563                 1, 2, CLK_SET_RATE_PARENT);
0564 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
0565                &pll_periph_clk.common.hw,
0566                1, 2, 0);
0567 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
0568                &pll_video_clk.common.hw,
0569                1, 2, 0);
0570 
0571 static struct clk_hw_onecell_data sun8i_a23_hw_clks = {
0572     .hws    = {
0573         [CLK_PLL_CPUX]      = &pll_cpux_clk.common.hw,
0574         [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
0575         [CLK_PLL_AUDIO]     = &pll_audio_clk.hw,
0576         [CLK_PLL_AUDIO_2X]  = &pll_audio_2x_clk.hw,
0577         [CLK_PLL_AUDIO_4X]  = &pll_audio_4x_clk.hw,
0578         [CLK_PLL_AUDIO_8X]  = &pll_audio_8x_clk.hw,
0579         [CLK_PLL_VIDEO]     = &pll_video_clk.common.hw,
0580         [CLK_PLL_VIDEO_2X]  = &pll_video_2x_clk.hw,
0581         [CLK_PLL_VE]        = &pll_ve_clk.common.hw,
0582         [CLK_PLL_DDR0]      = &pll_ddr_clk.common.hw,
0583         [CLK_PLL_PERIPH]    = &pll_periph_clk.common.hw,
0584         [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
0585         [CLK_PLL_GPU]       = &pll_gpu_clk.common.hw,
0586         [CLK_PLL_MIPI]      = &pll_mipi_clk.common.hw,
0587         [CLK_PLL_HSIC]      = &pll_hsic_clk.common.hw,
0588         [CLK_PLL_DE]        = &pll_de_clk.common.hw,
0589         [CLK_CPUX]      = &cpux_clk.common.hw,
0590         [CLK_AXI]       = &axi_clk.common.hw,
0591         [CLK_AHB1]      = &ahb1_clk.common.hw,
0592         [CLK_APB1]      = &apb1_clk.common.hw,
0593         [CLK_APB2]      = &apb2_clk.common.hw,
0594         [CLK_BUS_MIPI_DSI]  = &bus_mipi_dsi_clk.common.hw,
0595         [CLK_BUS_DMA]       = &bus_dma_clk.common.hw,
0596         [CLK_BUS_MMC0]      = &bus_mmc0_clk.common.hw,
0597         [CLK_BUS_MMC1]      = &bus_mmc1_clk.common.hw,
0598         [CLK_BUS_MMC2]      = &bus_mmc2_clk.common.hw,
0599         [CLK_BUS_NAND]      = &bus_nand_clk.common.hw,
0600         [CLK_BUS_DRAM]      = &bus_dram_clk.common.hw,
0601         [CLK_BUS_HSTIMER]   = &bus_hstimer_clk.common.hw,
0602         [CLK_BUS_SPI0]      = &bus_spi0_clk.common.hw,
0603         [CLK_BUS_SPI1]      = &bus_spi1_clk.common.hw,
0604         [CLK_BUS_OTG]       = &bus_otg_clk.common.hw,
0605         [CLK_BUS_EHCI]      = &bus_ehci_clk.common.hw,
0606         [CLK_BUS_OHCI]      = &bus_ohci_clk.common.hw,
0607         [CLK_BUS_VE]        = &bus_ve_clk.common.hw,
0608         [CLK_BUS_LCD]       = &bus_lcd_clk.common.hw,
0609         [CLK_BUS_CSI]       = &bus_csi_clk.common.hw,
0610         [CLK_BUS_DE_BE]     = &bus_de_be_clk.common.hw,
0611         [CLK_BUS_DE_FE]     = &bus_de_fe_clk.common.hw,
0612         [CLK_BUS_GPU]       = &bus_gpu_clk.common.hw,
0613         [CLK_BUS_MSGBOX]    = &bus_msgbox_clk.common.hw,
0614         [CLK_BUS_SPINLOCK]  = &bus_spinlock_clk.common.hw,
0615         [CLK_BUS_DRC]       = &bus_drc_clk.common.hw,
0616         [CLK_BUS_CODEC]     = &bus_codec_clk.common.hw,
0617         [CLK_BUS_PIO]       = &bus_pio_clk.common.hw,
0618         [CLK_BUS_I2S0]      = &bus_i2s0_clk.common.hw,
0619         [CLK_BUS_I2S1]      = &bus_i2s1_clk.common.hw,
0620         [CLK_BUS_I2C0]      = &bus_i2c0_clk.common.hw,
0621         [CLK_BUS_I2C1]      = &bus_i2c1_clk.common.hw,
0622         [CLK_BUS_I2C2]      = &bus_i2c2_clk.common.hw,
0623         [CLK_BUS_UART0]     = &bus_uart0_clk.common.hw,
0624         [CLK_BUS_UART1]     = &bus_uart1_clk.common.hw,
0625         [CLK_BUS_UART2]     = &bus_uart2_clk.common.hw,
0626         [CLK_BUS_UART3]     = &bus_uart3_clk.common.hw,
0627         [CLK_BUS_UART4]     = &bus_uart4_clk.common.hw,
0628         [CLK_NAND]      = &nand_clk.common.hw,
0629         [CLK_MMC0]      = &mmc0_clk.common.hw,
0630         [CLK_MMC0_SAMPLE]   = &mmc0_sample_clk.common.hw,
0631         [CLK_MMC0_OUTPUT]   = &mmc0_output_clk.common.hw,
0632         [CLK_MMC1]      = &mmc1_clk.common.hw,
0633         [CLK_MMC1_SAMPLE]   = &mmc1_sample_clk.common.hw,
0634         [CLK_MMC1_OUTPUT]   = &mmc1_output_clk.common.hw,
0635         [CLK_MMC2]      = &mmc2_clk.common.hw,
0636         [CLK_MMC2_SAMPLE]   = &mmc2_sample_clk.common.hw,
0637         [CLK_MMC2_OUTPUT]   = &mmc2_output_clk.common.hw,
0638         [CLK_SPI0]      = &spi0_clk.common.hw,
0639         [CLK_SPI1]      = &spi1_clk.common.hw,
0640         [CLK_I2S0]      = &i2s0_clk.common.hw,
0641         [CLK_I2S1]      = &i2s1_clk.common.hw,
0642         [CLK_USB_PHY0]      = &usb_phy0_clk.common.hw,
0643         [CLK_USB_PHY1]      = &usb_phy1_clk.common.hw,
0644         [CLK_USB_HSIC]      = &usb_hsic_clk.common.hw,
0645         [CLK_USB_HSIC_12M]  = &usb_hsic_12M_clk.common.hw,
0646         [CLK_USB_OHCI]      = &usb_ohci_clk.common.hw,
0647         [CLK_DRAM_VE]       = &dram_ve_clk.common.hw,
0648         [CLK_DRAM_CSI]      = &dram_csi_clk.common.hw,
0649         [CLK_DRAM_DRC]      = &dram_drc_clk.common.hw,
0650         [CLK_DRAM_DE_FE]    = &dram_de_fe_clk.common.hw,
0651         [CLK_DRAM_DE_BE]    = &dram_de_be_clk.common.hw,
0652         [CLK_DE_BE]     = &de_be_clk.common.hw,
0653         [CLK_DE_FE]     = &de_fe_clk.common.hw,
0654         [CLK_LCD_CH0]       = &lcd_ch0_clk.common.hw,
0655         [CLK_LCD_CH1]       = &lcd_ch1_clk.common.hw,
0656         [CLK_CSI_SCLK]      = &csi_sclk_clk.common.hw,
0657         [CLK_CSI_MCLK]      = &csi_mclk_clk.common.hw,
0658         [CLK_VE]        = &ve_clk.common.hw,
0659         [CLK_AC_DIG]        = &ac_dig_clk.common.hw,
0660         [CLK_AVS]       = &avs_clk.common.hw,
0661         [CLK_MBUS]      = &mbus_clk.common.hw,
0662         [CLK_DSI_SCLK]      = &dsi_sclk_clk.common.hw,
0663         [CLK_DSI_DPHY]      = &dsi_dphy_clk.common.hw,
0664         [CLK_DRC]       = &drc_clk.common.hw,
0665         [CLK_GPU]       = &gpu_clk.common.hw,
0666         [CLK_ATS]       = &ats_clk.common.hw,
0667     },
0668     .num    = CLK_NUMBER,
0669 };
0670 
0671 static struct ccu_reset_map sun8i_a23_ccu_resets[] = {
0672     [RST_USB_PHY0]      =  { 0x0cc, BIT(0) },
0673     [RST_USB_PHY1]      =  { 0x0cc, BIT(1) },
0674     [RST_USB_HSIC]      =  { 0x0cc, BIT(2) },
0675 
0676     [RST_MBUS]      =  { 0x0fc, BIT(31) },
0677 
0678     [RST_BUS_MIPI_DSI]  =  { 0x2c0, BIT(1) },
0679     [RST_BUS_DMA]       =  { 0x2c0, BIT(6) },
0680     [RST_BUS_MMC0]      =  { 0x2c0, BIT(8) },
0681     [RST_BUS_MMC1]      =  { 0x2c0, BIT(9) },
0682     [RST_BUS_MMC2]      =  { 0x2c0, BIT(10) },
0683     [RST_BUS_NAND]      =  { 0x2c0, BIT(13) },
0684     [RST_BUS_DRAM]      =  { 0x2c0, BIT(14) },
0685     [RST_BUS_HSTIMER]   =  { 0x2c0, BIT(19) },
0686     [RST_BUS_SPI0]      =  { 0x2c0, BIT(20) },
0687     [RST_BUS_SPI1]      =  { 0x2c0, BIT(21) },
0688     [RST_BUS_OTG]       =  { 0x2c0, BIT(24) },
0689     [RST_BUS_EHCI]      =  { 0x2c0, BIT(26) },
0690     [RST_BUS_OHCI]      =  { 0x2c0, BIT(29) },
0691 
0692     [RST_BUS_VE]        =  { 0x2c4, BIT(0) },
0693     [RST_BUS_LCD]       =  { 0x2c4, BIT(4) },
0694     [RST_BUS_CSI]       =  { 0x2c4, BIT(8) },
0695     [RST_BUS_DE_BE]     =  { 0x2c4, BIT(12) },
0696     [RST_BUS_DE_FE]     =  { 0x2c4, BIT(14) },
0697     [RST_BUS_GPU]       =  { 0x2c4, BIT(20) },
0698     [RST_BUS_MSGBOX]    =  { 0x2c4, BIT(21) },
0699     [RST_BUS_SPINLOCK]  =  { 0x2c4, BIT(22) },
0700     [RST_BUS_DRC]       =  { 0x2c4, BIT(25) },
0701 
0702     [RST_BUS_LVDS]      =  { 0x2c8, BIT(0) },
0703 
0704     [RST_BUS_CODEC]     =  { 0x2d0, BIT(0) },
0705     [RST_BUS_I2S0]      =  { 0x2d0, BIT(12) },
0706     [RST_BUS_I2S1]      =  { 0x2d0, BIT(13) },
0707 
0708     [RST_BUS_I2C0]      =  { 0x2d8, BIT(0) },
0709     [RST_BUS_I2C1]      =  { 0x2d8, BIT(1) },
0710     [RST_BUS_I2C2]      =  { 0x2d8, BIT(2) },
0711     [RST_BUS_UART0]     =  { 0x2d8, BIT(16) },
0712     [RST_BUS_UART1]     =  { 0x2d8, BIT(17) },
0713     [RST_BUS_UART2]     =  { 0x2d8, BIT(18) },
0714     [RST_BUS_UART3]     =  { 0x2d8, BIT(19) },
0715     [RST_BUS_UART4]     =  { 0x2d8, BIT(20) },
0716 };
0717 
0718 static const struct sunxi_ccu_desc sun8i_a23_ccu_desc = {
0719     .ccu_clks   = sun8i_a23_ccu_clks,
0720     .num_ccu_clks   = ARRAY_SIZE(sun8i_a23_ccu_clks),
0721 
0722     .hw_clks    = &sun8i_a23_hw_clks,
0723 
0724     .resets     = sun8i_a23_ccu_resets,
0725     .num_resets = ARRAY_SIZE(sun8i_a23_ccu_resets),
0726 };
0727 
0728 static int sun8i_a23_ccu_probe(struct platform_device *pdev)
0729 {
0730     void __iomem *reg;
0731     u32 val;
0732 
0733     reg = devm_platform_ioremap_resource(pdev, 0);
0734     if (IS_ERR(reg))
0735         return PTR_ERR(reg);
0736 
0737     /* Force the PLL-Audio-1x divider to 1 */
0738     val = readl(reg + SUN8I_A23_PLL_AUDIO_REG);
0739     val &= ~GENMASK(19, 16);
0740     writel(val | (0 << 16), reg + SUN8I_A23_PLL_AUDIO_REG);
0741 
0742     /* Force PLL-MIPI to MIPI mode */
0743     val = readl(reg + SUN8I_A23_PLL_MIPI_REG);
0744     val &= ~BIT(16);
0745     writel(val, reg + SUN8I_A23_PLL_MIPI_REG);
0746 
0747     return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a23_ccu_desc);
0748 }
0749 
0750 static const struct of_device_id sun8i_a23_ccu_ids[] = {
0751     { .compatible = "allwinner,sun8i-a23-ccu" },
0752     { }
0753 };
0754 
0755 static struct platform_driver sun8i_a23_ccu_driver = {
0756     .probe  = sun8i_a23_ccu_probe,
0757     .driver = {
0758         .name           = "sun8i-a23-ccu",
0759         .suppress_bind_attrs    = true,
0760         .of_match_table     = sun8i_a23_ccu_ids,
0761     },
0762 };
0763 module_platform_driver(sun8i_a23_ccu_driver);
0764 
0765 MODULE_IMPORT_NS(SUNXI_CCU);
0766 MODULE_LICENSE("GPL");
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