clk/sunxi-ng/ccu-sun8i-a23-a33.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2016 Maxime Ripard
0004  *
0005  * Maxime Ripard <maxime.ripard@free-electrons.com>
0006  */
0007
0008 #ifndef _CCU_SUN8I_A23_A33_H_
0009 #define _CCU_SUN8I_A23_A33_H_
0010
0011 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
0012 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
0013
0014 #define CLK_PLL_CPUX        0
0015 #define CLK_PLL_AUDIO_BASE  1
0016 #define CLK_PLL_AUDIO       2
0017 #define CLK_PLL_AUDIO_2X    3
0018 #define CLK_PLL_AUDIO_4X    4
0019 #define CLK_PLL_AUDIO_8X    5
0020 #define CLK_PLL_VIDEO       6
0021 #define CLK_PLL_VIDEO_2X    7
0022 #define CLK_PLL_VE      8
0023 #define CLK_PLL_DDR0        9
0024 #define CLK_PLL_PERIPH      10
0025 #define CLK_PLL_PERIPH_2X   11
0026 #define CLK_PLL_GPU     12
0027
0028 /* The PLL MIPI clock is exported */
0029
0030 #define CLK_PLL_HSIC        14
0031 #define CLK_PLL_DE      15
0032 #define CLK_PLL_DDR1        16
0033 #define CLK_PLL_DDR     17
0034
0035 /* The CPUX clock is exported */
0036
0037 #define CLK_AXI         19
0038 #define CLK_AHB1        20
0039 #define CLK_APB1        21
0040 #define CLK_APB2        22
0041
0042 /* All the bus gates are exported */
0043
0044 /* The first part of the mod clocks is exported */
0045
0046 #define CLK_DRAM        79
0047
0048 /* Some more module clocks are exported */
0049
0050 #define CLK_MBUS        95
0051
0052 /* And the last module clocks are exported */
0053
0054 #define CLK_NUMBER      (CLK_ATS + 1)
0055
0056 #endif /* _CCU_SUN8I_A23_A33_H_ */