clk/sunxi-ng/ccu-sun6i-a31.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2016 Chen-Yu Tsai
0004  *
0005  * Chen-Yu Tsai <wens@csie.org>
0006  */
0007
0008 #ifndef _CCU_SUN6I_A31_H_
0009 #define _CCU_SUN6I_A31_H_
0010
0011 #include <dt-bindings/clock/sun6i-a31-ccu.h>
0012 #include <dt-bindings/reset/sun6i-a31-ccu.h>
0013
0014 #define CLK_PLL_CPU     0
0015 #define CLK_PLL_AUDIO_BASE  1
0016 #define CLK_PLL_AUDIO       2
0017 #define CLK_PLL_AUDIO_2X    3
0018 #define CLK_PLL_AUDIO_4X    4
0019 #define CLK_PLL_AUDIO_8X    5
0020 #define CLK_PLL_VIDEO0      6
0021
0022 /* The PLL_VIDEO0_2X clock is exported */
0023
0024 #define CLK_PLL_VE      8
0025 #define CLK_PLL_DDR     9
0026
0027 /* The PLL_PERIPH clock is exported */
0028
0029 #define CLK_PLL_PERIPH_2X   11
0030 #define CLK_PLL_VIDEO1      12
0031
0032 /* The PLL_VIDEO1_2X clock is exported */
0033
0034 #define CLK_PLL_GPU     14
0035
0036 /* The PLL_VIDEO1_2X clock is exported */
0037
0038 #define CLK_PLL9        16
0039 #define CLK_PLL10       17
0040
0041 /* The CPUX clock is exported */
0042
0043 #define CLK_AXI         19
0044 #define CLK_AHB1        20
0045 #define CLK_APB1        21
0046 #define CLK_APB2        22
0047
0048 /* All the bus gates are exported */
0049
0050 /* The first bunch of module clocks are exported */
0051
0052 /* EMAC clock is not implemented */
0053
0054 #define CLK_MDFS        107
0055 #define CLK_SDRAM0      108
0056 #define CLK_SDRAM1      109
0057
0058 /* All the DRAM gates are exported */
0059
0060 /* Some more module clocks are exported */
0061
0062 #define CLK_MBUS0       141
0063 #define CLK_MBUS1       142
0064
0065 /* Some more module clocks and external clock outputs are exported */
0066
0067 #define CLK_NUMBER      (CLK_OUT_C + 1)
0068
0069 #endif /* _CCU_SUN6I_A31_H_ */