clk/sunxi-ng/ccu-sun5i.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2016 Maxime Ripard
0004  *
0005  * Maxime Ripard <maxime.ripard@free-electrons.com>
0006  */
0007
0008 #ifndef _CCU_SUN5I_H_
0009 #define _CCU_SUN5I_H_
0010
0011 #include <dt-bindings/clock/sun5i-ccu.h>
0012 #include <dt-bindings/reset/sun5i-ccu.h>
0013
0014 /* The HOSC is exported */
0015 #define CLK_PLL_CORE        2
0016 #define CLK_PLL_AUDIO_BASE  3
0017 #define CLK_PLL_AUDIO       4
0018 #define CLK_PLL_AUDIO_2X    5
0019 #define CLK_PLL_AUDIO_4X    6
0020 #define CLK_PLL_AUDIO_8X    7
0021 #define CLK_PLL_VIDEO0      8
0022
0023 /* The PLL_VIDEO0_2X is exported for HDMI */
0024
0025 #define CLK_PLL_VE      10
0026 #define CLK_PLL_DDR_BASE    11
0027 #define CLK_PLL_DDR     12
0028 #define CLK_PLL_DDR_OTHER   13
0029 #define CLK_PLL_PERIPH      14
0030 #define CLK_PLL_VIDEO1      15
0031
0032 /* The PLL_VIDEO1_2X is exported for HDMI */
0033 /* The CPU clock is exported */
0034
0035 #define CLK_AXI         18
0036 #define CLK_AHB         19
0037 #define CLK_APB0        20
0038 #define CLK_APB1        21
0039 #define CLK_DRAM_AXI        22
0040
0041 /* AHB gates are exported */
0042 /* APB0 gates are exported */
0043 /* APB1 gates are exported */
0044 /* Modules clocks are exported */
0045 /* USB clocks are exported */
0046 /* GPS clock is exported */
0047 /* DRAM gates are exported */
0048 /* More display modules clocks are exported */
0049
0050 #define CLK_TCON_CH1_SCLK   91
0051
0052 /* The rest of the module clocks are exported */
0053
0054 #define CLK_NUMBER      (CLK_IEP + 1)
0055
0056 #endif /* _CCU_SUN5I_H_ */