clk/sunxi-ng/ccu-sun5i.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
0004  */
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/io.h>
0008 #include <linux/of_address.h>
0009
0010 #include "ccu_common.h"
0011 #include "ccu_reset.h"
0012
0013 #include "ccu_div.h"
0014 #include "ccu_gate.h"
0015 #include "ccu_mp.h"
0016 #include "ccu_mult.h"
0017 #include "ccu_nk.h"
0018 #include "ccu_nkm.h"
0019 #include "ccu_nkmp.h"
0020 #include "ccu_nm.h"
0021 #include "ccu_phase.h"
0022 #include "ccu_sdm.h"
0023
0024 #include "ccu-sun5i.h"
0025
0026 static struct ccu_nkmp pll_core_clk = {
0027     .enable     = BIT(31),
0028     .n      = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
0029     .k      = _SUNXI_CCU_MULT(4, 2),
0030     .m      = _SUNXI_CCU_DIV(0, 2),
0031     .p      = _SUNXI_CCU_DIV(16, 2),
0032     .common     = {
0033         .reg        = 0x000,
0034         .hw.init    = CLK_HW_INIT("pll-core",
0035                           "hosc",
0036                           &ccu_nkmp_ops,
0037                           0),
0038     },
0039 };
0040
0041 /*
0042  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
0043  * the base (2x, 4x and 8x), and one variable divider (the one true
0044  * pll audio).
0045  *
0046  * With sigma-delta modulation for fractional-N on the audio PLL,
0047  * we have to use specific dividers. This means the variable divider
0048  * can no longer be used, as the audio codec requests the exact clock
0049  * rates we support through this mechanism. So we now hard code the
0050  * variable divider to 1. This means the clock rates will no longer
0051  * match the clock names.
0052  */
0053 #define SUN5I_PLL_AUDIO_REG 0x008
0054
0055 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
0056     { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
0057     { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
0058 };
0059
0060 static struct ccu_nm pll_audio_base_clk = {
0061     .enable     = BIT(31),
0062     .n      = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
0063
0064     /*
0065      * The datasheet is wrong here, this doesn't have any
0066      * offset
0067      */
0068     .m      = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
0069     .sdm        = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
0070                      0x00c, BIT(31)),
0071     .common     = {
0072         .reg        = 0x008,
0073         .features   = CCU_FEATURE_SIGMA_DELTA_MOD,
0074         .hw.init    = CLK_HW_INIT("pll-audio-base",
0075                           "hosc",
0076                           &ccu_nm_ops,
0077                           0),
0078     },
0079 };
0080
0081 static struct ccu_mult pll_video0_clk = {
0082     .enable     = BIT(31),
0083     .mult       = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
0084     .frac       = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
0085                       270000000, 297000000),
0086     .common     = {
0087         .reg        = 0x010,
0088         .features   = (CCU_FEATURE_FRACTIONAL |
0089                    CCU_FEATURE_ALL_PREDIV),
0090         .prediv     = 8,
0091         .hw.init    = CLK_HW_INIT("pll-video0",
0092                           "hosc",
0093                           &ccu_mult_ops,
0094                           0),
0095     },
0096 };
0097
0098 static struct ccu_nkmp pll_ve_clk = {
0099     .enable     = BIT(31),
0100     .n      = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
0101     .k      = _SUNXI_CCU_MULT(4, 2),
0102     .m      = _SUNXI_CCU_DIV(0, 2),
0103     .p      = _SUNXI_CCU_DIV(16, 2),
0104     .common     = {
0105         .reg        = 0x018,
0106         .hw.init    = CLK_HW_INIT("pll-ve",
0107                           "hosc",
0108                           &ccu_nkmp_ops,
0109                           0),
0110     },
0111 };
0112
0113 static struct ccu_nk pll_ddr_base_clk = {
0114     .enable     = BIT(31),
0115     .n      = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
0116     .k      = _SUNXI_CCU_MULT(4, 2),
0117     .common     = {
0118         .reg        = 0x020,
0119         .hw.init    = CLK_HW_INIT("pll-ddr-base",
0120                           "hosc",
0121                           &ccu_nk_ops,
0122                           0),
0123     },
0124 };
0125
0126 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
0127            CLK_IS_CRITICAL);
0128
0129 static struct ccu_div pll_ddr_other_clk = {
0130     .div        = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
0131
0132     .common     = {
0133         .reg        = 0x020,
0134         .hw.init    = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
0135                           &ccu_div_ops,
0136                           0),
0137     },
0138 };
0139
0140 static struct ccu_nk pll_periph_clk = {
0141     .enable     = BIT(31),
0142     .n      = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
0143     .k      = _SUNXI_CCU_MULT(4, 2),
0144     .fixed_post_div = 2,
0145     .common     = {
0146         .reg        = 0x028,
0147         .features   = CCU_FEATURE_FIXED_POSTDIV,
0148         .hw.init    = CLK_HW_INIT("pll-periph",
0149                           "hosc",
0150                           &ccu_nk_ops,
0151                           0),
0152     },
0153 };
0154
0155 static struct ccu_mult pll_video1_clk = {
0156     .enable     = BIT(31),
0157     .mult       = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
0158     .frac       = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
0159                   270000000, 297000000),
0160     .common     = {
0161         .reg        = 0x030,
0162         .features   = (CCU_FEATURE_FRACTIONAL |
0163                    CCU_FEATURE_ALL_PREDIV),
0164         .prediv     = 8,
0165         .hw.init    = CLK_HW_INIT("pll-video1",
0166                           "hosc",
0167                           &ccu_mult_ops,
0168                           0),
0169     },
0170 };
0171
0172 static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
0173
0174 #define SUN5I_AHB_REG   0x054
0175 static const char * const cpu_parents[] = { "osc32k", "hosc",
0176                         "pll-core" , "pll-periph" };
0177 static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
0178     { .index = 3, .div = 3, },
0179 };
0180 static struct ccu_mux cpu_clk = {
0181     .mux        = {
0182         .shift      = 16,
0183         .width      = 2,
0184         .fixed_predivs  = cpu_predivs,
0185         .n_predivs  = ARRAY_SIZE(cpu_predivs),
0186     },
0187     .common     = {
0188         .reg        = 0x054,
0189         .features   = CCU_FEATURE_FIXED_PREDIV,
0190         .hw.init    = CLK_HW_INIT_PARENTS("cpu",
0191                               cpu_parents,
0192                               &ccu_mux_ops,
0193                               CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
0194     }
0195 };
0196
0197 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
0198
0199 static const char * const ahb_parents[] = { "axi" , "cpu", "pll-periph" };
0200 static const struct ccu_mux_fixed_prediv ahb_predivs[] = {
0201     { .index = 2, .div = 2, },
0202 };
0203 static struct ccu_div ahb_clk = {
0204     .div        = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
0205     .mux        = {
0206         .shift      = 6,
0207         .width      = 2,
0208         .fixed_predivs  = ahb_predivs,
0209         .n_predivs  = ARRAY_SIZE(ahb_predivs),
0210     },
0211
0212     .common     = {
0213         .reg        = 0x054,
0214         .hw.init    = CLK_HW_INIT_PARENTS("ahb",
0215                               ahb_parents,
0216                               &ccu_div_ops,
0217                               0),
0218     },
0219 };
0220
0221 static struct clk_div_table apb0_div_table[] = {
0222     { .val = 0, .div = 2 },
0223     { .val = 1, .div = 2 },
0224     { .val = 2, .div = 4 },
0225     { .val = 3, .div = 8 },
0226     { /* Sentinel */ },
0227 };
0228 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
0229                0x054, 8, 2, apb0_div_table, 0);
0230
0231 static const char * const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
0232 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
0233                  0, 5,  /* M */
0234                  16, 2, /* P */
0235                  24, 2, /* mux */
0236                  0);
0237
0238 static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "axi",
0239               0x05c, BIT(0), 0);
0240
0241 static SUNXI_CCU_GATE(ahb_otg_clk,  "ahb-otg",  "ahb",
0242               0x060, BIT(0), 0);
0243 static SUNXI_CCU_GATE(ahb_ehci_clk, "ahb-ehci", "ahb",
0244               0x060, BIT(1), 0);
0245 static SUNXI_CCU_GATE(ahb_ohci_clk, "ahb-ohci", "ahb",
0246               0x060, BIT(2), 0);
0247 static SUNXI_CCU_GATE(ahb_ss_clk,   "ahb-ss",   "ahb",
0248               0x060, BIT(5), 0);
0249 static SUNXI_CCU_GATE(ahb_dma_clk,  "ahb-dma",  "ahb",
0250               0x060, BIT(6), 0);
0251 static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
0252               0x060, BIT(7), 0);
0253 static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
0254               0x060, BIT(8), 0);
0255 static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
0256               0x060, BIT(9), 0);
0257 static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",
0258               0x060, BIT(10), 0);
0259 static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",
0260               0x060, BIT(13), 0);
0261 static SUNXI_CCU_GATE(ahb_sdram_clk,    "ahb-sdram",    "ahb",
0262               0x060, BIT(14), CLK_IS_CRITICAL);
0263 static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",
0264               0x060, BIT(17), 0);
0265 static SUNXI_CCU_GATE(ahb_ts_clk,   "ahb-ts",   "ahb",
0266               0x060, BIT(18), 0);
0267 static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",
0268               0x060, BIT(20), 0);
0269 static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",
0270               0x060, BIT(21), 0);
0271 static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",
0272               0x060, BIT(22), 0);
0273 static SUNXI_CCU_GATE(ahb_gps_clk,  "ahb-gps",  "ahb",
0274               0x060, BIT(26), 0);
0275 static SUNXI_CCU_GATE(ahb_hstimer_clk,  "ahb-hstimer",  "ahb",
0276               0x060, BIT(28), 0);
0277
0278 static SUNXI_CCU_GATE(ahb_ve_clk,   "ahb-ve",   "ahb",
0279               0x064, BIT(0), 0);
0280 static SUNXI_CCU_GATE(ahb_tve_clk,  "ahb-tve",  "ahb",
0281               0x064, BIT(2), 0);
0282 static SUNXI_CCU_GATE(ahb_lcd_clk,  "ahb-lcd",  "ahb",
0283               0x064, BIT(4), 0);
0284 static SUNXI_CCU_GATE(ahb_csi_clk,  "ahb-csi",  "ahb",
0285               0x064, BIT(8), 0);
0286 static SUNXI_CCU_GATE(ahb_hdmi_clk, "ahb-hdmi", "ahb",
0287               0x064, BIT(11), 0);
0288 static SUNXI_CCU_GATE(ahb_de_be_clk,    "ahb-de-be",    "ahb",
0289               0x064, BIT(12), 0);
0290 static SUNXI_CCU_GATE(ahb_de_fe_clk,    "ahb-de-fe",    "ahb",
0291               0x064, BIT(14), 0);
0292 static SUNXI_CCU_GATE(ahb_iep_clk,  "ahb-iep",  "ahb",
0293               0x064, BIT(19), 0);
0294 static SUNXI_CCU_GATE(ahb_gpu_clk,  "ahb-gpu",  "ahb",
0295               0x064, BIT(20), 0);
0296
0297 static SUNXI_CCU_GATE(apb0_codec_clk,   "apb0-codec",   "apb0",
0298               0x068, BIT(0), 0);
0299 static SUNXI_CCU_GATE(apb0_spdif_clk,   "apb0-spdif",   "apb0",
0300               0x068, BIT(1), 0);
0301 static SUNXI_CCU_GATE(apb0_i2s_clk, "apb0-i2s", "apb0",
0302               0x068, BIT(3), 0);
0303 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
0304               0x068, BIT(5), 0);
0305 static SUNXI_CCU_GATE(apb0_ir_clk,  "apb0-ir",  "apb0",
0306               0x068, BIT(6), 0);
0307 static SUNXI_CCU_GATE(apb0_keypad_clk,  "apb0-keypad",  "apb0",
0308               0x068, BIT(10), 0);
0309
0310 static SUNXI_CCU_GATE(apb1_i2c0_clk,    "apb1-i2c0",    "apb1",
0311               0x06c, BIT(0), 0);
0312 static SUNXI_CCU_GATE(apb1_i2c1_clk,    "apb1-i2c1",    "apb1",
0313               0x06c, BIT(1), 0);
0314 static SUNXI_CCU_GATE(apb1_i2c2_clk,    "apb1-i2c2",    "apb1",
0315               0x06c, BIT(2), 0);
0316 static SUNXI_CCU_GATE(apb1_uart0_clk,   "apb1-uart0",   "apb1",
0317               0x06c, BIT(16), 0);
0318 static SUNXI_CCU_GATE(apb1_uart1_clk,   "apb1-uart1",   "apb1",
0319               0x06c, BIT(17), 0);
0320 static SUNXI_CCU_GATE(apb1_uart2_clk,   "apb1-uart2",   "apb1",
0321               0x06c, BIT(18), 0);
0322 static SUNXI_CCU_GATE(apb1_uart3_clk,   "apb1-uart3",   "apb1",
0323               0x06c, BIT(19), 0);
0324
0325 static const char * const mod0_default_parents[] = { "hosc", "pll-periph",
0326                              "pll-ddr-other" };
0327 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0328                   0, 4,     /* M */
0329                   16, 2,    /* P */
0330                   24, 2,    /* mux */
0331                   BIT(31),  /* gate */
0332                   0);
0333
0334 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0335                   0, 4,     /* M */
0336                   16, 2,    /* P */
0337                   24, 2,    /* mux */
0338                   BIT(31),  /* gate */
0339                   0);
0340
0341 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0342                   0, 4,     /* M */
0343                   16, 2,    /* P */
0344                   24, 2,    /* mux */
0345                   BIT(31),  /* gate */
0346                   0);
0347
0348 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0349                   0, 4,     /* M */
0350                   16, 2,    /* P */
0351                   24, 2,    /* mux */
0352                   BIT(31),  /* gate */
0353                   0);
0354
0355 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
0356                   0, 4,     /* M */
0357                   16, 2,    /* P */
0358                   24, 2,    /* mux */
0359                   BIT(31),  /* gate */
0360                   0);
0361
0362 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
0363                   0, 4,     /* M */
0364                   16, 2,    /* P */
0365                   24, 2,    /* mux */
0366                   BIT(31),  /* gate */
0367                   0);
0368
0369 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0370                   0, 4,     /* M */
0371                   16, 2,    /* P */
0372                   24, 2,    /* mux */
0373                   BIT(31),  /* gate */
0374                   0);
0375
0376 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0377                   0, 4,     /* M */
0378                   16, 2,    /* P */
0379                   24, 2,    /* mux */
0380                   BIT(31),  /* gate */
0381                   0);
0382
0383 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
0384                   0, 4,     /* M */
0385                   16, 2,    /* P */
0386                   24, 2,    /* mux */
0387                   BIT(31),  /* gate */
0388                   0);
0389
0390 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", mod0_default_parents, 0x0b0,
0391                   0, 4,     /* M */
0392                   16, 2,    /* P */
0393                   24, 2,    /* mux */
0394                   BIT(31),  /* gate */
0395                   0);
0396
0397 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
0398                         "pll-audio-2x", "pll-audio" };
0399 static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_parents,
0400                    0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0401
0402 static const char * const spdif_parents[] = { "pll-audio-8x", "pll-audio-4x",
0403                         "pll-audio-2x", "pll-audio" };
0404 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", spdif_parents,
0405                    0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0406
0407 static const char * const keypad_parents[] = { "hosc", "losc"};
0408 static const u8 keypad_table[] = { 0, 2 };
0409 static struct ccu_mp keypad_clk = {
0410     .enable     = BIT(31),
0411     .m      = _SUNXI_CCU_DIV(8, 5),
0412     .p      = _SUNXI_CCU_DIV(20, 2),
0413     .mux        = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
0414
0415     .common     = {
0416         .reg        = 0x0c4,
0417         .hw.init    = CLK_HW_INIT_PARENTS("keypad",
0418                               keypad_parents,
0419                               &ccu_mp_ops,
0420                               0),
0421     },
0422 };
0423
0424 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "pll-periph",
0425               0x0cc, BIT(6), 0);
0426 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "pll-periph",
0427               0x0cc, BIT(8), 0);
0428 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "pll-periph",
0429               0x0cc, BIT(9), 0);
0430
0431 static const char * const gps_parents[] = { "hosc", "pll-periph",
0432                         "pll-video1", "pll-ve" };
0433 static SUNXI_CCU_M_WITH_MUX_GATE(gps_clk, "gps", gps_parents,
0434                  0x0d0, 0, 3, 24, 2, BIT(31), 0);
0435
0436 static SUNXI_CCU_GATE(dram_ve_clk,  "dram-ve",  "pll-ddr",
0437               0x100, BIT(0), 0);
0438 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
0439               0x100, BIT(1), 0);
0440 static SUNXI_CCU_GATE(dram_ts_clk,  "dram-ts",  "pll-ddr",
0441               0x100, BIT(3), 0);
0442 static SUNXI_CCU_GATE(dram_tve_clk, "dram-tve", "pll-ddr",
0443               0x100, BIT(5), 0);
0444 static SUNXI_CCU_GATE(dram_de_fe_clk,   "dram-de-fe",   "pll-ddr",
0445               0x100, BIT(25), 0);
0446 static SUNXI_CCU_GATE(dram_de_be_clk,   "dram-de-be",   "pll-ddr",
0447               0x100, BIT(26), 0);
0448 static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",
0449               0x100, BIT(29), 0);
0450 static SUNXI_CCU_GATE(dram_iep_clk, "dram-iep", "pll-ddr",
0451               0x100, BIT(31), 0);
0452
0453 static const char * const de_parents[] = { "pll-video0", "pll-video1",
0454                        "pll-ddr-other" };
0455 static SUNXI_CCU_M_WITH_MUX_GATE(de_be_clk, "de-be", de_parents,
0456                  0x104, 0, 4, 24, 2, BIT(31), 0);
0457
0458 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe_clk, "de-fe", de_parents,
0459                  0x10c, 0, 4, 24, 2, BIT(31), 0);
0460
0461 static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
0462                          "pll-video0-2x", "pll-video1-2x" };
0463 static SUNXI_CCU_MUX_WITH_GATE(tcon_ch0_clk, "tcon-ch0-sclk", tcon_parents,
0464                    0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
0465
0466 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_ch1_sclk2_clk, "tcon-ch1-sclk2",
0467                  tcon_parents,
0468                  0x12c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
0469
0470 static SUNXI_CCU_M_WITH_GATE(tcon_ch1_sclk1_clk, "tcon-ch1-sclk1", "tcon-ch1-sclk2",
0471                  0x12c, 11, 1, BIT(15), CLK_SET_RATE_PARENT);
0472
0473 static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
0474                         "pll-video0-2x", "pll-video1-2x" };
0475 static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
0476 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",
0477                        csi_parents, csi_table,
0478                        0x134, 0, 5, 24, 3, BIT(31), 0);
0479
0480 static SUNXI_CCU_GATE(ve_clk,       "ve",       "pll-ve",
0481               0x13c, BIT(31), CLK_SET_RATE_PARENT);
0482
0483 static SUNXI_CCU_GATE(codec_clk,    "codec",    "pll-audio",
0484               0x140, BIT(31), CLK_SET_RATE_PARENT);
0485
0486 static SUNXI_CCU_GATE(avs_clk,      "avs",      "hosc",
0487               0x144, BIT(31), 0);
0488
0489 static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-2x" };
0490 static const u8 hdmi_table[] = { 0, 2 };
0491 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi",
0492                        hdmi_parents, hdmi_table,
0493                        0x150, 0, 4, 24, 2, BIT(31),
0494                        CLK_SET_RATE_PARENT);
0495
0496 static const char * const gpu_parents[] = { "pll-video0", "pll-ve",
0497                         "pll-ddr-other", "pll-video1",
0498                         "pll-video1-2x" };
0499 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents,
0500                  0x154, 0, 4, 24, 3, BIT(31), 0);
0501
0502 static const char * const mbus_parents[] = { "hosc", "pll-periph", "pll-ddr" };
0503 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0504                   0x15c, 0, 4, 16, 2, 24, 2, BIT(31), CLK_IS_CRITICAL);
0505
0506 static SUNXI_CCU_GATE(iep_clk,      "iep",      "de-be",
0507               0x160, BIT(31), 0);
0508
0509 static struct ccu_common *sun5i_a10s_ccu_clks[] = {
0510     &hosc_clk.common,
0511     &pll_core_clk.common,
0512     &pll_audio_base_clk.common,
0513     &pll_video0_clk.common,
0514     &pll_ve_clk.common,
0515     &pll_ddr_base_clk.common,
0516     &pll_ddr_clk.common,
0517     &pll_ddr_other_clk.common,
0518     &pll_periph_clk.common,
0519     &pll_video1_clk.common,
0520     &cpu_clk.common,
0521     &axi_clk.common,
0522     &ahb_clk.common,
0523     &apb0_clk.common,
0524     &apb1_clk.common,
0525     &axi_dram_clk.common,
0526     &ahb_otg_clk.common,
0527     &ahb_ehci_clk.common,
0528     &ahb_ohci_clk.common,
0529     &ahb_ss_clk.common,
0530     &ahb_dma_clk.common,
0531     &ahb_bist_clk.common,
0532     &ahb_mmc0_clk.common,
0533     &ahb_mmc1_clk.common,
0534     &ahb_mmc2_clk.common,
0535     &ahb_nand_clk.common,
0536     &ahb_sdram_clk.common,
0537     &ahb_emac_clk.common,
0538     &ahb_ts_clk.common,
0539     &ahb_spi0_clk.common,
0540     &ahb_spi1_clk.common,
0541     &ahb_spi2_clk.common,
0542     &ahb_gps_clk.common,
0543     &ahb_hstimer_clk.common,
0544     &ahb_ve_clk.common,
0545     &ahb_tve_clk.common,
0546     &ahb_lcd_clk.common,
0547     &ahb_csi_clk.common,
0548     &ahb_hdmi_clk.common,
0549     &ahb_de_be_clk.common,
0550     &ahb_de_fe_clk.common,
0551     &ahb_iep_clk.common,
0552     &ahb_gpu_clk.common,
0553     &apb0_codec_clk.common,
0554     &apb0_spdif_clk.common,
0555     &apb0_i2s_clk.common,
0556     &apb0_pio_clk.common,
0557     &apb0_ir_clk.common,
0558     &apb0_keypad_clk.common,
0559     &apb1_i2c0_clk.common,
0560     &apb1_i2c1_clk.common,
0561     &apb1_i2c2_clk.common,
0562     &apb1_uart0_clk.common,
0563     &apb1_uart1_clk.common,
0564     &apb1_uart2_clk.common,
0565     &apb1_uart3_clk.common,
0566     &nand_clk.common,
0567     &mmc0_clk.common,
0568     &mmc1_clk.common,
0569     &mmc2_clk.common,
0570     &ts_clk.common,
0571     &ss_clk.common,
0572     &spi0_clk.common,
0573     &spi1_clk.common,
0574     &spi2_clk.common,
0575     &ir_clk.common,
0576     &i2s_clk.common,
0577     &spdif_clk.common,
0578     &keypad_clk.common,
0579     &usb_ohci_clk.common,
0580     &usb_phy0_clk.common,
0581     &usb_phy1_clk.common,
0582     &gps_clk.common,
0583     &dram_ve_clk.common,
0584     &dram_csi_clk.common,
0585     &dram_ts_clk.common,
0586     &dram_tve_clk.common,
0587     &dram_de_fe_clk.common,
0588     &dram_de_be_clk.common,
0589     &dram_ace_clk.common,
0590     &dram_iep_clk.common,
0591     &de_be_clk.common,
0592     &de_fe_clk.common,
0593     &tcon_ch0_clk.common,
0594     &tcon_ch1_sclk2_clk.common,
0595     &tcon_ch1_sclk1_clk.common,
0596     &csi_clk.common,
0597     &ve_clk.common,
0598     &codec_clk.common,
0599     &avs_clk.common,
0600     &hdmi_clk.common,
0601     &gpu_clk.common,
0602     &mbus_clk.common,
0603     &iep_clk.common,
0604 };
0605
0606 static const struct clk_hw *clk_parent_pll_audio[] = {
0607     &pll_audio_base_clk.common.hw
0608 };
0609
0610 /* We hardcode the divider to 1 for now */
0611 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
0612                 clk_parent_pll_audio,
0613                 1, 1, CLK_SET_RATE_PARENT);
0614 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
0615                 clk_parent_pll_audio,
0616                 2, 1, CLK_SET_RATE_PARENT);
0617 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
0618                 clk_parent_pll_audio,
0619                 1, 1, CLK_SET_RATE_PARENT);
0620 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
0621                 clk_parent_pll_audio,
0622                 1, 2, CLK_SET_RATE_PARENT);
0623 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
0624                &pll_video0_clk.common.hw,
0625                1, 2, CLK_SET_RATE_PARENT);
0626 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
0627                &pll_video1_clk.common.hw,
0628                1, 2, CLK_SET_RATE_PARENT);
0629
0630 static struct clk_hw_onecell_data sun5i_a10s_hw_clks = {
0631     .hws    = {
0632         [CLK_HOSC]      = &hosc_clk.common.hw,
0633         [CLK_PLL_CORE]      = &pll_core_clk.common.hw,
0634         [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
0635         [CLK_PLL_AUDIO]     = &pll_audio_clk.hw,
0636         [CLK_PLL_AUDIO_2X]  = &pll_audio_2x_clk.hw,
0637         [CLK_PLL_AUDIO_4X]  = &pll_audio_4x_clk.hw,
0638         [CLK_PLL_AUDIO_8X]  = &pll_audio_8x_clk.hw,
0639         [CLK_PLL_VIDEO0]    = &pll_video0_clk.common.hw,
0640         [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
0641         [CLK_PLL_VE]        = &pll_ve_clk.common.hw,
0642         [CLK_PLL_DDR_BASE]  = &pll_ddr_base_clk.common.hw,
0643         [CLK_PLL_DDR]       = &pll_ddr_clk.common.hw,
0644         [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
0645         [CLK_PLL_PERIPH]    = &pll_periph_clk.common.hw,
0646         [CLK_PLL_VIDEO1]    = &pll_video1_clk.common.hw,
0647         [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
0648         [CLK_CPU]       = &cpu_clk.common.hw,
0649         [CLK_AXI]       = &axi_clk.common.hw,
0650         [CLK_AHB]       = &ahb_clk.common.hw,
0651         [CLK_APB0]      = &apb0_clk.common.hw,
0652         [CLK_APB1]      = &apb1_clk.common.hw,
0653         [CLK_DRAM_AXI]      = &axi_dram_clk.common.hw,
0654         [CLK_AHB_OTG]       = &ahb_otg_clk.common.hw,
0655         [CLK_AHB_EHCI]      = &ahb_ehci_clk.common.hw,
0656         [CLK_AHB_OHCI]      = &ahb_ohci_clk.common.hw,
0657         [CLK_AHB_SS]        = &ahb_ss_clk.common.hw,
0658         [CLK_AHB_DMA]       = &ahb_dma_clk.common.hw,
0659         [CLK_AHB_BIST]      = &ahb_bist_clk.common.hw,
0660         [CLK_AHB_MMC0]      = &ahb_mmc0_clk.common.hw,
0661         [CLK_AHB_MMC1]      = &ahb_mmc1_clk.common.hw,
0662         [CLK_AHB_MMC2]      = &ahb_mmc2_clk.common.hw,
0663         [CLK_AHB_NAND]      = &ahb_nand_clk.common.hw,
0664         [CLK_AHB_SDRAM]     = &ahb_sdram_clk.common.hw,
0665         [CLK_AHB_EMAC]      = &ahb_emac_clk.common.hw,
0666         [CLK_AHB_TS]        = &ahb_ts_clk.common.hw,
0667         [CLK_AHB_SPI0]      = &ahb_spi0_clk.common.hw,
0668         [CLK_AHB_SPI1]      = &ahb_spi1_clk.common.hw,
0669         [CLK_AHB_SPI2]      = &ahb_spi2_clk.common.hw,
0670         [CLK_AHB_GPS]       = &ahb_gps_clk.common.hw,
0671         [CLK_AHB_HSTIMER]   = &ahb_hstimer_clk.common.hw,
0672         [CLK_AHB_VE]        = &ahb_ve_clk.common.hw,
0673         [CLK_AHB_TVE]       = &ahb_tve_clk.common.hw,
0674         [CLK_AHB_LCD]       = &ahb_lcd_clk.common.hw,
0675         [CLK_AHB_CSI]       = &ahb_csi_clk.common.hw,
0676         [CLK_AHB_HDMI]      = &ahb_hdmi_clk.common.hw,
0677         [CLK_AHB_DE_BE]     = &ahb_de_be_clk.common.hw,
0678         [CLK_AHB_DE_FE]     = &ahb_de_fe_clk.common.hw,
0679         [CLK_AHB_IEP]       = &ahb_iep_clk.common.hw,
0680         [CLK_AHB_GPU]       = &ahb_gpu_clk.common.hw,
0681         [CLK_APB0_CODEC]    = &apb0_codec_clk.common.hw,
0682         [CLK_APB0_I2S]      = &apb0_i2s_clk.common.hw,
0683         [CLK_APB0_PIO]      = &apb0_pio_clk.common.hw,
0684         [CLK_APB0_IR]       = &apb0_ir_clk.common.hw,
0685         [CLK_APB0_KEYPAD]   = &apb0_keypad_clk.common.hw,
0686         [CLK_APB1_I2C0]     = &apb1_i2c0_clk.common.hw,
0687         [CLK_APB1_I2C1]     = &apb1_i2c1_clk.common.hw,
0688         [CLK_APB1_I2C2]     = &apb1_i2c2_clk.common.hw,
0689         [CLK_APB1_UART0]    = &apb1_uart0_clk.common.hw,
0690         [CLK_APB1_UART1]    = &apb1_uart1_clk.common.hw,
0691         [CLK_APB1_UART2]    = &apb1_uart2_clk.common.hw,
0692         [CLK_APB1_UART3]    = &apb1_uart3_clk.common.hw,
0693         [CLK_NAND]      = &nand_clk.common.hw,
0694         [CLK_MMC0]      = &mmc0_clk.common.hw,
0695         [CLK_MMC1]      = &mmc1_clk.common.hw,
0696         [CLK_MMC2]      = &mmc2_clk.common.hw,
0697         [CLK_TS]        = &ts_clk.common.hw,
0698         [CLK_SS]        = &ss_clk.common.hw,
0699         [CLK_SPI0]      = &spi0_clk.common.hw,
0700         [CLK_SPI1]      = &spi1_clk.common.hw,
0701         [CLK_SPI2]      = &spi2_clk.common.hw,
0702         [CLK_IR]        = &ir_clk.common.hw,
0703         [CLK_I2S]       = &i2s_clk.common.hw,
0704         [CLK_KEYPAD]        = &keypad_clk.common.hw,
0705         [CLK_USB_OHCI]      = &usb_ohci_clk.common.hw,
0706         [CLK_USB_PHY0]      = &usb_phy0_clk.common.hw,
0707         [CLK_USB_PHY1]      = &usb_phy1_clk.common.hw,
0708         [CLK_GPS]       = &gps_clk.common.hw,
0709         [CLK_DRAM_VE]       = &dram_ve_clk.common.hw,
0710         [CLK_DRAM_CSI]      = &dram_csi_clk.common.hw,
0711         [CLK_DRAM_TS]       = &dram_ts_clk.common.hw,
0712         [CLK_DRAM_TVE]      = &dram_tve_clk.common.hw,
0713         [CLK_DRAM_DE_FE]    = &dram_de_fe_clk.common.hw,
0714         [CLK_DRAM_DE_BE]    = &dram_de_be_clk.common.hw,
0715         [CLK_DRAM_ACE]      = &dram_ace_clk.common.hw,
0716         [CLK_DRAM_IEP]      = &dram_iep_clk.common.hw,
0717         [CLK_DE_BE]     = &de_be_clk.common.hw,
0718         [CLK_DE_FE]     = &de_fe_clk.common.hw,
0719         [CLK_TCON_CH0]      = &tcon_ch0_clk.common.hw,
0720         [CLK_TCON_CH1_SCLK] = &tcon_ch1_sclk2_clk.common.hw,
0721         [CLK_TCON_CH1]      = &tcon_ch1_sclk1_clk.common.hw,
0722         [CLK_CSI]       = &csi_clk.common.hw,
0723         [CLK_VE]        = &ve_clk.common.hw,
0724         [CLK_CODEC]     = &codec_clk.common.hw,
0725         [CLK_AVS]       = &avs_clk.common.hw,
0726         [CLK_HDMI]      = &hdmi_clk.common.hw,
0727         [CLK_GPU]       = &gpu_clk.common.hw,
0728         [CLK_MBUS]      = &mbus_clk.common.hw,
0729         [CLK_IEP]       = &iep_clk.common.hw,
0730     },
0731     .num    = CLK_NUMBER,
0732 };
0733
0734 static struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
0735     [RST_USB_PHY0]      =  { 0x0cc, BIT(0) },
0736     [RST_USB_PHY1]      =  { 0x0cc, BIT(1) },
0737
0738     [RST_GPS]       =  { 0x0d0, BIT(30) },
0739
0740     [RST_DE_BE]     =  { 0x104, BIT(30) },
0741
0742     [RST_DE_FE]     =  { 0x10c, BIT(30) },
0743
0744     [RST_TVE]       =  { 0x118, BIT(29) },
0745     [RST_LCD]       =  { 0x118, BIT(30) },
0746
0747     [RST_CSI]       =  { 0x134, BIT(30) },
0748
0749     [RST_VE]        =  { 0x13c, BIT(0) },
0750
0751     [RST_GPU]       =  { 0x154, BIT(30) },
0752
0753     [RST_IEP]       =  { 0x160, BIT(30) },
0754 };
0755
0756 static const struct sunxi_ccu_desc sun5i_a10s_ccu_desc = {
0757     .ccu_clks   = sun5i_a10s_ccu_clks,
0758     .num_ccu_clks   = ARRAY_SIZE(sun5i_a10s_ccu_clks),
0759
0760     .hw_clks    = &sun5i_a10s_hw_clks,
0761
0762     .resets     = sun5i_a10s_ccu_resets,
0763     .num_resets = ARRAY_SIZE(sun5i_a10s_ccu_resets),
0764 };
0765
0766 /*
0767  * The A13 is the A10s minus the TS, GPS, HDMI, I2S and the keypad
0768  */
0769 static struct clk_hw_onecell_data sun5i_a13_hw_clks = {
0770     .hws    = {
0771         [CLK_HOSC]      = &hosc_clk.common.hw,
0772         [CLK_PLL_CORE]      = &pll_core_clk.common.hw,
0773         [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
0774         [CLK_PLL_AUDIO]     = &pll_audio_clk.hw,
0775         [CLK_PLL_AUDIO_2X]  = &pll_audio_2x_clk.hw,
0776         [CLK_PLL_AUDIO_4X]  = &pll_audio_4x_clk.hw,
0777         [CLK_PLL_AUDIO_8X]  = &pll_audio_8x_clk.hw,
0778         [CLK_PLL_VIDEO0]    = &pll_video0_clk.common.hw,
0779         [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
0780         [CLK_PLL_VE]        = &pll_ve_clk.common.hw,
0781         [CLK_PLL_DDR_BASE]  = &pll_ddr_base_clk.common.hw,
0782         [CLK_PLL_DDR]       = &pll_ddr_clk.common.hw,
0783         [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
0784         [CLK_PLL_PERIPH]    = &pll_periph_clk.common.hw,
0785         [CLK_PLL_VIDEO1]    = &pll_video1_clk.common.hw,
0786         [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
0787         [CLK_CPU]       = &cpu_clk.common.hw,
0788         [CLK_AXI]       = &axi_clk.common.hw,
0789         [CLK_AHB]       = &ahb_clk.common.hw,
0790         [CLK_APB0]      = &apb0_clk.common.hw,
0791         [CLK_APB1]      = &apb1_clk.common.hw,
0792         [CLK_DRAM_AXI]      = &axi_dram_clk.common.hw,
0793         [CLK_AHB_OTG]       = &ahb_otg_clk.common.hw,
0794         [CLK_AHB_EHCI]      = &ahb_ehci_clk.common.hw,
0795         [CLK_AHB_OHCI]      = &ahb_ohci_clk.common.hw,
0796         [CLK_AHB_SS]        = &ahb_ss_clk.common.hw,
0797         [CLK_AHB_DMA]       = &ahb_dma_clk.common.hw,
0798         [CLK_AHB_BIST]      = &ahb_bist_clk.common.hw,
0799         [CLK_AHB_MMC0]      = &ahb_mmc0_clk.common.hw,
0800         [CLK_AHB_MMC1]      = &ahb_mmc1_clk.common.hw,
0801         [CLK_AHB_MMC2]      = &ahb_mmc2_clk.common.hw,
0802         [CLK_AHB_NAND]      = &ahb_nand_clk.common.hw,
0803         [CLK_AHB_SDRAM]     = &ahb_sdram_clk.common.hw,
0804         [CLK_AHB_EMAC]      = &ahb_emac_clk.common.hw,
0805         [CLK_AHB_SPI0]      = &ahb_spi0_clk.common.hw,
0806         [CLK_AHB_SPI1]      = &ahb_spi1_clk.common.hw,
0807         [CLK_AHB_SPI2]      = &ahb_spi2_clk.common.hw,
0808         [CLK_AHB_HSTIMER]   = &ahb_hstimer_clk.common.hw,
0809         [CLK_AHB_VE]        = &ahb_ve_clk.common.hw,
0810         [CLK_AHB_TVE]       = &ahb_tve_clk.common.hw,
0811         [CLK_AHB_LCD]       = &ahb_lcd_clk.common.hw,
0812         [CLK_AHB_CSI]       = &ahb_csi_clk.common.hw,
0813         [CLK_AHB_DE_BE]     = &ahb_de_be_clk.common.hw,
0814         [CLK_AHB_DE_FE]     = &ahb_de_fe_clk.common.hw,
0815         [CLK_AHB_IEP]       = &ahb_iep_clk.common.hw,
0816         [CLK_AHB_GPU]       = &ahb_gpu_clk.common.hw,
0817         [CLK_APB0_CODEC]    = &apb0_codec_clk.common.hw,
0818         [CLK_APB0_PIO]      = &apb0_pio_clk.common.hw,
0819         [CLK_APB0_IR]       = &apb0_ir_clk.common.hw,
0820         [CLK_APB1_I2C0]     = &apb1_i2c0_clk.common.hw,
0821         [CLK_APB1_I2C1]     = &apb1_i2c1_clk.common.hw,
0822         [CLK_APB1_I2C2]     = &apb1_i2c2_clk.common.hw,
0823         [CLK_APB1_UART0]    = &apb1_uart0_clk.common.hw,
0824         [CLK_APB1_UART1]    = &apb1_uart1_clk.common.hw,
0825         [CLK_APB1_UART2]    = &apb1_uart2_clk.common.hw,
0826         [CLK_APB1_UART3]    = &apb1_uart3_clk.common.hw,
0827         [CLK_NAND]      = &nand_clk.common.hw,
0828         [CLK_MMC0]      = &mmc0_clk.common.hw,
0829         [CLK_MMC1]      = &mmc1_clk.common.hw,
0830         [CLK_MMC2]      = &mmc2_clk.common.hw,
0831         [CLK_SS]        = &ss_clk.common.hw,
0832         [CLK_SPI0]      = &spi0_clk.common.hw,
0833         [CLK_SPI1]      = &spi1_clk.common.hw,
0834         [CLK_SPI2]      = &spi2_clk.common.hw,
0835         [CLK_IR]        = &ir_clk.common.hw,
0836         [CLK_USB_OHCI]      = &usb_ohci_clk.common.hw,
0837         [CLK_USB_PHY0]      = &usb_phy0_clk.common.hw,
0838         [CLK_USB_PHY1]      = &usb_phy1_clk.common.hw,
0839         [CLK_DRAM_VE]       = &dram_ve_clk.common.hw,
0840         [CLK_DRAM_CSI]      = &dram_csi_clk.common.hw,
0841         [CLK_DRAM_TVE]      = &dram_tve_clk.common.hw,
0842         [CLK_DRAM_DE_FE]    = &dram_de_fe_clk.common.hw,
0843         [CLK_DRAM_DE_BE]    = &dram_de_be_clk.common.hw,
0844         [CLK_DRAM_ACE]      = &dram_ace_clk.common.hw,
0845         [CLK_DRAM_IEP]      = &dram_iep_clk.common.hw,
0846         [CLK_DE_BE]     = &de_be_clk.common.hw,
0847         [CLK_DE_FE]     = &de_fe_clk.common.hw,
0848         [CLK_TCON_CH0]      = &tcon_ch0_clk.common.hw,
0849         [CLK_TCON_CH1_SCLK] = &tcon_ch1_sclk2_clk.common.hw,
0850         [CLK_TCON_CH1]      = &tcon_ch1_sclk1_clk.common.hw,
0851         [CLK_CSI]       = &csi_clk.common.hw,
0852         [CLK_VE]        = &ve_clk.common.hw,
0853         [CLK_CODEC]     = &codec_clk.common.hw,
0854         [CLK_AVS]       = &avs_clk.common.hw,
0855         [CLK_GPU]       = &gpu_clk.common.hw,
0856         [CLK_MBUS]      = &mbus_clk.common.hw,
0857         [CLK_IEP]       = &iep_clk.common.hw,
0858     },
0859     .num    = CLK_NUMBER,
0860 };
0861
0862 static const struct sunxi_ccu_desc sun5i_a13_ccu_desc = {
0863     .ccu_clks   = sun5i_a10s_ccu_clks,
0864     .num_ccu_clks   = ARRAY_SIZE(sun5i_a10s_ccu_clks),
0865
0866     .hw_clks    = &sun5i_a13_hw_clks,
0867
0868     .resets     = sun5i_a10s_ccu_resets,
0869     .num_resets = ARRAY_SIZE(sun5i_a10s_ccu_resets),
0870 };
0871
0872 /*
0873  * The GR8 is the A10s CCU minus the HDMI and keypad, plus SPDIF
0874  */
0875 static struct clk_hw_onecell_data sun5i_gr8_hw_clks = {
0876     .hws    = {
0877         [CLK_HOSC]      = &hosc_clk.common.hw,
0878         [CLK_PLL_CORE]      = &pll_core_clk.common.hw,
0879         [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
0880         [CLK_PLL_AUDIO]     = &pll_audio_clk.hw,
0881         [CLK_PLL_AUDIO_2X]  = &pll_audio_2x_clk.hw,
0882         [CLK_PLL_AUDIO_4X]  = &pll_audio_4x_clk.hw,
0883         [CLK_PLL_AUDIO_8X]  = &pll_audio_8x_clk.hw,
0884         [CLK_PLL_VIDEO0]    = &pll_video0_clk.common.hw,
0885         [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
0886         [CLK_PLL_VE]        = &pll_ve_clk.common.hw,
0887         [CLK_PLL_DDR_BASE]  = &pll_ddr_base_clk.common.hw,
0888         [CLK_PLL_DDR]       = &pll_ddr_clk.common.hw,
0889         [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
0890         [CLK_PLL_PERIPH]    = &pll_periph_clk.common.hw,
0891         [CLK_PLL_VIDEO1]    = &pll_video1_clk.common.hw,
0892         [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
0893         [CLK_CPU]       = &cpu_clk.common.hw,
0894         [CLK_AXI]       = &axi_clk.common.hw,
0895         [CLK_AHB]       = &ahb_clk.common.hw,
0896         [CLK_APB0]      = &apb0_clk.common.hw,
0897         [CLK_APB1]      = &apb1_clk.common.hw,
0898         [CLK_DRAM_AXI]      = &axi_dram_clk.common.hw,
0899         [CLK_AHB_OTG]       = &ahb_otg_clk.common.hw,
0900         [CLK_AHB_EHCI]      = &ahb_ehci_clk.common.hw,
0901         [CLK_AHB_OHCI]      = &ahb_ohci_clk.common.hw,
0902         [CLK_AHB_SS]        = &ahb_ss_clk.common.hw,
0903         [CLK_AHB_DMA]       = &ahb_dma_clk.common.hw,
0904         [CLK_AHB_BIST]      = &ahb_bist_clk.common.hw,
0905         [CLK_AHB_MMC0]      = &ahb_mmc0_clk.common.hw,
0906         [CLK_AHB_MMC1]      = &ahb_mmc1_clk.common.hw,
0907         [CLK_AHB_MMC2]      = &ahb_mmc2_clk.common.hw,
0908         [CLK_AHB_NAND]      = &ahb_nand_clk.common.hw,
0909         [CLK_AHB_SDRAM]     = &ahb_sdram_clk.common.hw,
0910         [CLK_AHB_EMAC]      = &ahb_emac_clk.common.hw,
0911         [CLK_AHB_TS]        = &ahb_ts_clk.common.hw,
0912         [CLK_AHB_SPI0]      = &ahb_spi0_clk.common.hw,
0913         [CLK_AHB_SPI1]      = &ahb_spi1_clk.common.hw,
0914         [CLK_AHB_SPI2]      = &ahb_spi2_clk.common.hw,
0915         [CLK_AHB_GPS]       = &ahb_gps_clk.common.hw,
0916         [CLK_AHB_HSTIMER]   = &ahb_hstimer_clk.common.hw,
0917         [CLK_AHB_VE]        = &ahb_ve_clk.common.hw,
0918         [CLK_AHB_TVE]       = &ahb_tve_clk.common.hw,
0919         [CLK_AHB_LCD]       = &ahb_lcd_clk.common.hw,
0920         [CLK_AHB_CSI]       = &ahb_csi_clk.common.hw,
0921         [CLK_AHB_DE_BE]     = &ahb_de_be_clk.common.hw,
0922         [CLK_AHB_DE_FE]     = &ahb_de_fe_clk.common.hw,
0923         [CLK_AHB_IEP]       = &ahb_iep_clk.common.hw,
0924         [CLK_AHB_GPU]       = &ahb_gpu_clk.common.hw,
0925         [CLK_APB0_CODEC]    = &apb0_codec_clk.common.hw,
0926         [CLK_APB0_SPDIF]    = &apb0_spdif_clk.common.hw,
0927         [CLK_APB0_I2S]      = &apb0_i2s_clk.common.hw,
0928         [CLK_APB0_PIO]      = &apb0_pio_clk.common.hw,
0929         [CLK_APB0_IR]       = &apb0_ir_clk.common.hw,
0930         [CLK_APB1_I2C0]     = &apb1_i2c0_clk.common.hw,
0931         [CLK_APB1_I2C1]     = &apb1_i2c1_clk.common.hw,
0932         [CLK_APB1_I2C2]     = &apb1_i2c2_clk.common.hw,
0933         [CLK_APB1_UART0]    = &apb1_uart0_clk.common.hw,
0934         [CLK_APB1_UART1]    = &apb1_uart1_clk.common.hw,
0935         [CLK_APB1_UART2]    = &apb1_uart2_clk.common.hw,
0936         [CLK_APB1_UART3]    = &apb1_uart3_clk.common.hw,
0937         [CLK_NAND]      = &nand_clk.common.hw,
0938         [CLK_MMC0]      = &mmc0_clk.common.hw,
0939         [CLK_MMC1]      = &mmc1_clk.common.hw,
0940         [CLK_MMC2]      = &mmc2_clk.common.hw,
0941         [CLK_TS]        = &ts_clk.common.hw,
0942         [CLK_SS]        = &ss_clk.common.hw,
0943         [CLK_SPI0]      = &spi0_clk.common.hw,
0944         [CLK_SPI1]      = &spi1_clk.common.hw,
0945         [CLK_SPI2]      = &spi2_clk.common.hw,
0946         [CLK_IR]        = &ir_clk.common.hw,
0947         [CLK_I2S]       = &i2s_clk.common.hw,
0948         [CLK_SPDIF]     = &spdif_clk.common.hw,
0949         [CLK_USB_OHCI]      = &usb_ohci_clk.common.hw,
0950         [CLK_USB_PHY0]      = &usb_phy0_clk.common.hw,
0951         [CLK_USB_PHY1]      = &usb_phy1_clk.common.hw,
0952         [CLK_GPS]       = &gps_clk.common.hw,
0953         [CLK_DRAM_VE]       = &dram_ve_clk.common.hw,
0954         [CLK_DRAM_CSI]      = &dram_csi_clk.common.hw,
0955         [CLK_DRAM_TS]       = &dram_ts_clk.common.hw,
0956         [CLK_DRAM_TVE]      = &dram_tve_clk.common.hw,
0957         [CLK_DRAM_DE_FE]    = &dram_de_fe_clk.common.hw,
0958         [CLK_DRAM_DE_BE]    = &dram_de_be_clk.common.hw,
0959         [CLK_DRAM_ACE]      = &dram_ace_clk.common.hw,
0960         [CLK_DRAM_IEP]      = &dram_iep_clk.common.hw,
0961         [CLK_DE_BE]     = &de_be_clk.common.hw,
0962         [CLK_DE_FE]     = &de_fe_clk.common.hw,
0963         [CLK_TCON_CH0]      = &tcon_ch0_clk.common.hw,
0964         [CLK_TCON_CH1_SCLK] = &tcon_ch1_sclk2_clk.common.hw,
0965         [CLK_TCON_CH1]      = &tcon_ch1_sclk1_clk.common.hw,
0966         [CLK_CSI]       = &csi_clk.common.hw,
0967         [CLK_VE]        = &ve_clk.common.hw,
0968         [CLK_CODEC]     = &codec_clk.common.hw,
0969         [CLK_AVS]       = &avs_clk.common.hw,
0970         [CLK_GPU]       = &gpu_clk.common.hw,
0971         [CLK_MBUS]      = &mbus_clk.common.hw,
0972         [CLK_IEP]       = &iep_clk.common.hw,
0973     },
0974     .num    = CLK_NUMBER,
0975 };
0976
0977 static const struct sunxi_ccu_desc sun5i_gr8_ccu_desc = {
0978     .ccu_clks   = sun5i_a10s_ccu_clks,
0979     .num_ccu_clks   = ARRAY_SIZE(sun5i_a10s_ccu_clks),
0980
0981     .hw_clks    = &sun5i_gr8_hw_clks,
0982
0983     .resets     = sun5i_a10s_ccu_resets,
0984     .num_resets = ARRAY_SIZE(sun5i_a10s_ccu_resets),
0985 };
0986
0987 static void __init sun5i_ccu_init(struct device_node *node,
0988                   const struct sunxi_ccu_desc *desc)
0989 {
0990     void __iomem *reg;
0991     u32 val;
0992
0993     reg = of_io_request_and_map(node, 0, of_node_full_name(node));
0994     if (IS_ERR(reg)) {
0995         pr_err("%pOF: Could not map the clock registers\n", node);
0996         return;
0997     }
0998
0999     /* Force the PLL-Audio-1x divider to 1 */
1000     val = readl(reg + SUN5I_PLL_AUDIO_REG);
1001     val &= ~GENMASK(29, 26);
1002     writel(val | (0 << 26), reg + SUN5I_PLL_AUDIO_REG);
1003
1004     /*
1005      * Use the peripheral PLL as the AHB parent, instead of CPU /
1006      * AXI which have rate changes due to cpufreq.
1007      *
1008      * This is especially a big deal for the HS timer whose parent
1009      * clock is AHB.
1010      */
1011     val = readl(reg + SUN5I_AHB_REG);
1012     val &= ~GENMASK(7, 6);
1013     writel(val | (2 << 6), reg + SUN5I_AHB_REG);
1014
1015     of_sunxi_ccu_probe(node, reg, desc);
1016 }
1017
1018 static void __init sun5i_a10s_ccu_setup(struct device_node *node)
1019 {
1020     sun5i_ccu_init(node, &sun5i_a10s_ccu_desc);
1021 }
1022 CLK_OF_DECLARE(sun5i_a10s_ccu, "allwinner,sun5i-a10s-ccu",
1023            sun5i_a10s_ccu_setup);
1024
1025 static void __init sun5i_a13_ccu_setup(struct device_node *node)
1026 {
1027     sun5i_ccu_init(node, &sun5i_a13_ccu_desc);
1028 }
1029 CLK_OF_DECLARE(sun5i_a13_ccu, "allwinner,sun5i-a13-ccu",
1030            sun5i_a13_ccu_setup);
1031
1032 static void __init sun5i_gr8_ccu_setup(struct device_node *node)
1033 {
1034     sun5i_ccu_init(node, &sun5i_gr8_ccu_desc);
1035 }
1036 CLK_OF_DECLARE(sun5i_gr8_ccu, "nextthing,gr8-ccu",
1037            sun5i_gr8_ccu_setup);