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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020 Arm Ltd.
0004  * Based on the H6 CCU driver, which is:
0005  *   Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
0006  */
0007 
0008 #include <linux/clk-provider.h>
0009 #include <linux/io.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012 
0013 #include "ccu_common.h"
0014 #include "ccu_reset.h"
0015 
0016 #include "ccu_div.h"
0017 #include "ccu_gate.h"
0018 #include "ccu_mp.h"
0019 #include "ccu_mult.h"
0020 #include "ccu_nk.h"
0021 #include "ccu_nkm.h"
0022 #include "ccu_nkmp.h"
0023 #include "ccu_nm.h"
0024 
0025 #include "ccu-sun50i-h616.h"
0026 
0027 /*
0028  * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
0029  * P should only be used for output frequencies lower than 288 MHz.
0030  *
0031  * For now we can just model it as a multiplier clock, and force P to /1.
0032  *
0033  * The M factor is present in the register's description, but not in the
0034  * frequency formula, and it's documented as "M is only used for backdoor
0035  * testing", so it's not modelled and then force to 0.
0036  */
0037 #define SUN50I_H616_PLL_CPUX_REG    0x000
0038 static struct ccu_mult pll_cpux_clk = {
0039     .enable     = BIT(31),
0040     .lock       = BIT(28),
0041     .mult       = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0042     .common     = {
0043         .reg        = 0x000,
0044         .hw.init    = CLK_HW_INIT("pll-cpux", "osc24M",
0045                           &ccu_mult_ops,
0046                           CLK_SET_RATE_UNGATE),
0047     },
0048 };
0049 
0050 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
0051 #define SUN50I_H616_PLL_DDR0_REG    0x010
0052 static struct ccu_nkmp pll_ddr0_clk = {
0053     .enable     = BIT(31),
0054     .lock       = BIT(28),
0055     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0056     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0057     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0058     .common     = {
0059         .reg        = 0x010,
0060         .hw.init    = CLK_HW_INIT("pll-ddr0", "osc24M",
0061                           &ccu_nkmp_ops,
0062                           CLK_SET_RATE_UNGATE),
0063     },
0064 };
0065 
0066 #define SUN50I_H616_PLL_DDR1_REG    0x018
0067 static struct ccu_nkmp pll_ddr1_clk = {
0068     .enable     = BIT(31),
0069     .lock       = BIT(28),
0070     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0071     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0072     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0073     .common     = {
0074         .reg        = 0x018,
0075         .hw.init    = CLK_HW_INIT("pll-ddr1", "osc24M",
0076                           &ccu_nkmp_ops,
0077                           CLK_SET_RATE_UNGATE),
0078     },
0079 };
0080 
0081 #define SUN50I_H616_PLL_PERIPH0_REG 0x020
0082 static struct ccu_nkmp pll_periph0_clk = {
0083     .enable     = BIT(31),
0084     .lock       = BIT(28),
0085     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0086     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0087     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0088     .fixed_post_div = 2,
0089     .common     = {
0090         .reg        = 0x020,
0091         .features   = CCU_FEATURE_FIXED_POSTDIV,
0092         .hw.init    = CLK_HW_INIT("pll-periph0", "osc24M",
0093                           &ccu_nkmp_ops,
0094                           CLK_SET_RATE_UNGATE),
0095     },
0096 };
0097 
0098 #define SUN50I_H616_PLL_PERIPH1_REG 0x028
0099 static struct ccu_nkmp pll_periph1_clk = {
0100     .enable     = BIT(31),
0101     .lock       = BIT(28),
0102     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0103     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0104     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0105     .fixed_post_div = 2,
0106     .common     = {
0107         .reg        = 0x028,
0108         .features   = CCU_FEATURE_FIXED_POSTDIV,
0109         .hw.init    = CLK_HW_INIT("pll-periph1", "osc24M",
0110                           &ccu_nkmp_ops,
0111                           CLK_SET_RATE_UNGATE),
0112     },
0113 };
0114 
0115 #define SUN50I_H616_PLL_GPU_REG     0x030
0116 static struct ccu_nkmp pll_gpu_clk = {
0117     .enable     = BIT(31),
0118     .lock       = BIT(28),
0119     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0120     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0121     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0122     .common     = {
0123         .reg        = 0x030,
0124         .hw.init    = CLK_HW_INIT("pll-gpu", "osc24M",
0125                           &ccu_nkmp_ops,
0126                           CLK_SET_RATE_UNGATE),
0127     },
0128 };
0129 
0130 /*
0131  * For Video PLLs, the output divider is described as "used for testing"
0132  * in the user manual. So it's not modelled and forced to 0.
0133  */
0134 #define SUN50I_H616_PLL_VIDEO0_REG  0x040
0135 static struct ccu_nm pll_video0_clk = {
0136     .enable     = BIT(31),
0137     .lock       = BIT(28),
0138     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0139     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0140     .fixed_post_div = 4,
0141     .min_rate   = 288000000,
0142     .max_rate   = 2400000000UL,
0143     .common     = {
0144         .reg        = 0x040,
0145         .features   = CCU_FEATURE_FIXED_POSTDIV,
0146         .hw.init    = CLK_HW_INIT("pll-video0", "osc24M",
0147                           &ccu_nm_ops,
0148                           CLK_SET_RATE_UNGATE),
0149     },
0150 };
0151 
0152 #define SUN50I_H616_PLL_VIDEO1_REG  0x048
0153 static struct ccu_nm pll_video1_clk = {
0154     .enable     = BIT(31),
0155     .lock       = BIT(28),
0156     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0157     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0158     .fixed_post_div = 4,
0159     .min_rate   = 288000000,
0160     .max_rate   = 2400000000UL,
0161     .common     = {
0162         .reg        = 0x048,
0163         .features   = CCU_FEATURE_FIXED_POSTDIV,
0164         .hw.init    = CLK_HW_INIT("pll-video1", "osc24M",
0165                           &ccu_nm_ops,
0166                           CLK_SET_RATE_UNGATE),
0167     },
0168 };
0169 
0170 #define SUN50I_H616_PLL_VIDEO2_REG  0x050
0171 static struct ccu_nm pll_video2_clk = {
0172     .enable     = BIT(31),
0173     .lock       = BIT(28),
0174     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0175     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0176     .fixed_post_div = 4,
0177     .min_rate   = 288000000,
0178     .max_rate   = 2400000000UL,
0179     .common     = {
0180         .reg        = 0x050,
0181         .features   = CCU_FEATURE_FIXED_POSTDIV,
0182         .hw.init    = CLK_HW_INIT("pll-video2", "osc24M",
0183                           &ccu_nm_ops,
0184                           CLK_SET_RATE_UNGATE),
0185     },
0186 };
0187 
0188 #define SUN50I_H616_PLL_VE_REG      0x058
0189 static struct ccu_nkmp pll_ve_clk = {
0190     .enable     = BIT(31),
0191     .lock       = BIT(28),
0192     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0193     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0194     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0195     .common     = {
0196         .reg        = 0x058,
0197         .hw.init    = CLK_HW_INIT("pll-ve", "osc24M",
0198                           &ccu_nkmp_ops,
0199                           CLK_SET_RATE_UNGATE),
0200     },
0201 };
0202 
0203 #define SUN50I_H616_PLL_DE_REG      0x060
0204 static struct ccu_nkmp pll_de_clk = {
0205     .enable     = BIT(31),
0206     .lock       = BIT(28),
0207     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0208     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0209     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0210     .common     = {
0211         .reg        = 0x060,
0212         .hw.init    = CLK_HW_INIT("pll-de", "osc24M",
0213                           &ccu_nkmp_ops,
0214                           CLK_SET_RATE_UNGATE),
0215     },
0216 };
0217 
0218 /*
0219  * TODO: Determine SDM settings for the audio PLL. The manual suggests
0220  * PLL_FACTOR_N=16, PLL_POST_DIV_P=2, OUTPUT_DIV=2, pattern=0xe000c49b
0221  * for 24.576 MHz, and PLL_FACTOR_N=22, PLL_POST_DIV_P=3, OUTPUT_DIV=2,
0222  * pattern=0xe001288c for 22.5792 MHz.
0223  * This clashes with our fixed PLL_POST_DIV_P.
0224  */
0225 #define SUN50I_H616_PLL_AUDIO_REG   0x078
0226 static struct ccu_nm pll_audio_hs_clk = {
0227     .enable     = BIT(31),
0228     .lock       = BIT(28),
0229     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0230     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0231     .common     = {
0232         .reg        = 0x078,
0233         .hw.init    = CLK_HW_INIT("pll-audio-hs", "osc24M",
0234                           &ccu_nm_ops,
0235                           CLK_SET_RATE_UNGATE),
0236     },
0237 };
0238 
0239 static const char * const cpux_parents[] = { "osc24M", "osc32k",
0240                     "iosc", "pll-cpux", "pll-periph0" };
0241 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0242              0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
0243 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
0244 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
0245 
0246 static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k",
0247                               "iosc", "pll-periph0" };
0248 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
0249                  psi_ahb1_ahb2_parents,
0250                  0x510,
0251                  0, 2,  /* M */
0252                  8, 2,  /* P */
0253                  24, 2, /* mux */
0254                  0);
0255 
0256 static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
0257                                "psi-ahb1-ahb2",
0258                                "pll-periph0" };
0259 static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
0260                  0, 2,  /* M */
0261                  8, 2,  /* P */
0262                  24, 2, /* mux */
0263                  0);
0264 
0265 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
0266                  0, 2,  /* M */
0267                  8, 2,  /* P */
0268                  24, 2, /* mux */
0269                  0);
0270 
0271 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
0272                  0, 2,  /* M */
0273                  8, 2,  /* P */
0274                  24, 2, /* mux */
0275                  0);
0276 
0277 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
0278                          "pll-ddr0", "pll-ddr1" };
0279 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540,
0280                     0, 3,   /* M */
0281                     24, 2,  /* mux */
0282                     BIT(31),    /* gate */
0283                     CLK_IS_CRITICAL);
0284 
0285 static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" };
0286 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600,
0287                        0, 4,    /* M */
0288                        24, 1,   /* mux */
0289                        BIT(31), /* gate */
0290                        CLK_SET_RATE_PARENT);
0291 
0292 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
0293               0x60c, BIT(0), 0);
0294 
0295 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
0296                        de_parents,
0297                        0x620,
0298                        0, 4,    /* M */
0299                        24, 1,   /* mux */
0300                        BIT(31), /* gate */
0301                        0);
0302 
0303 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
0304               0x62c, BIT(0), 0);
0305 
0306 static SUNXI_CCU_M_WITH_MUX_GATE(g2d_clk, "g2d", de_parents, 0x630,
0307                        0, 4,    /* M */
0308                        24, 1,   /* mux */
0309                        BIT(31), /* gate */
0310                        0);
0311 
0312 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
0313               0x63c, BIT(0), 0);
0314 
0315 static const char * const gpu0_parents[] = { "pll-gpu", "gpu1" };
0316 static SUNXI_CCU_M_WITH_MUX_GATE(gpu0_clk, "gpu0", gpu0_parents, 0x670,
0317                        0, 2,    /* M */
0318                        24, 1,   /* mux */
0319                        BIT(31), /* gate */
0320                        CLK_SET_RATE_PARENT);
0321 static SUNXI_CCU_M_WITH_GATE(gpu1_clk, "gpu1", "pll-periph0-2x", 0x674,
0322                     0, 2,   /* M */
0323                     BIT(31),/* gate */
0324                     0);
0325 
0326 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
0327               0x67c, BIT(0), 0);
0328 
0329 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
0330 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
0331                     0, 4,   /* M */
0332                     8, 2,   /* N */
0333                     24, 1,  /* mux */
0334                     BIT(31),/* gate */
0335                     0);
0336 
0337 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
0338               0x68c, BIT(0), 0);
0339 
0340 static const char * const ve_parents[] = { "pll-ve" };
0341 static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
0342                        0, 3,    /* M */
0343                        24, 1,   /* mux */
0344                        BIT(31), /* gate */
0345                        CLK_SET_RATE_PARENT);
0346 
0347 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
0348               0x69c, BIT(0), 0);
0349 
0350 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
0351               0x70c, BIT(0), 0);
0352 
0353 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
0354               0x73c, BIT(0), 0);
0355 
0356 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0);
0357 
0358 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
0359               0x78c, BIT(0), 0);
0360 
0361 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
0362               0x79c, BIT(0), 0);
0363 
0364 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
0365 
0366 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
0367 
0368 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
0369 static struct ccu_div dram_clk = {
0370     .div        = _SUNXI_CCU_DIV(0, 2),
0371     .mux        = _SUNXI_CCU_MUX(24, 2),
0372     .common = {
0373         .reg        = 0x800,
0374         .hw.init    = CLK_HW_INIT_PARENTS("dram",
0375                               dram_parents,
0376                               &ccu_div_ops,
0377                               CLK_IS_CRITICAL),
0378     },
0379 };
0380 
0381 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
0382               0x804, BIT(0), 0);
0383 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
0384               0x804, BIT(1), 0);
0385 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
0386               0x804, BIT(2), 0);
0387 static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
0388               0x804, BIT(3), 0);
0389 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
0390               0x804, BIT(5), 0);
0391 static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus",
0392               0x804, BIT(10), 0);
0393 
0394 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
0395               0x80c, BIT(0), CLK_IS_CRITICAL);
0396 
0397 static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0",
0398                          "pll-periph1", "pll-periph0-2x",
0399                          "pll-periph1-2x" };
0400 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810,
0401                     0, 4,   /* M */
0402                     8, 2,   /* N */
0403                     24, 3,  /* mux */
0404                     BIT(31),/* gate */
0405                     0);
0406 
0407 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814,
0408                     0, 4,   /* M */
0409                     8, 2,   /* N */
0410                     24, 3,  /* mux */
0411                     BIT(31),/* gate */
0412                     0);
0413 
0414 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
0415 
0416 static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
0417                         "pll-periph1-2x" };
0418 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
0419                       0, 4,     /* M */
0420                       8, 2,     /* N */
0421                       24, 2,    /* mux */
0422                       BIT(31),  /* gate */
0423                       2,        /* post-div */
0424                       0);
0425 
0426 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
0427                       0, 4,     /* M */
0428                       8, 2,     /* N */
0429                       24, 2,    /* mux */
0430                       BIT(31),  /* gate */
0431                       2,        /* post-div */
0432                       0);
0433 
0434 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
0435                       0, 4,     /* M */
0436                       8, 2,     /* N */
0437                       24, 2,    /* mux */
0438                       BIT(31),  /* gate */
0439                       2,        /* post-div */
0440                       0);
0441 
0442 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
0443 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
0444 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
0445 
0446 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
0447 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
0448 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
0449 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
0450 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
0451 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 0x90c, BIT(5), 0);
0452 
0453 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
0454 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
0455 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
0456 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
0457 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2", 0x91c, BIT(4), 0);
0458 
0459 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940,
0460                     0, 4,   /* M */
0461                     8, 2,   /* N */
0462                     24, 3,  /* mux */
0463                     BIT(31),/* gate */
0464                     0);
0465 
0466 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
0467                     0, 4,   /* M */
0468                     8, 2,   /* N */
0469                     24, 3,  /* mux */
0470                     BIT(31),/* gate */
0471                     0);
0472 
0473 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
0474 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
0475 
0476 static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
0477               BIT(31) | BIT(30), 0);
0478 
0479 static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0), 0);
0480 static SUNXI_CCU_GATE(bus_emac1_clk, "bus-emac1", "ahb3", 0x97c, BIT(1), 0);
0481 
0482 static const char * const ts_parents[] = { "osc24M", "pll-periph0" };
0483 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
0484                     0, 4,   /* M */
0485                     8, 2,   /* N */
0486                     24, 1,  /* mux */
0487                     BIT(31),/* gate */
0488                     0);
0489 
0490 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
0491 
0492 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
0493 
0494 static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",
0495                           "pll-audio-4x", "pll-audio-hs" };
0496 static struct ccu_div spdif_clk = {
0497     .enable     = BIT(31),
0498     .div        = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
0499     .mux        = _SUNXI_CCU_MUX(24, 2),
0500     .common     = {
0501         .reg        = 0xa20,
0502         .hw.init    = CLK_HW_INIT_PARENTS("spdif",
0503                               audio_parents,
0504                               &ccu_div_ops,
0505                               0),
0506     },
0507 };
0508 
0509 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
0510 
0511 static struct ccu_div dmic_clk = {
0512     .enable     = BIT(31),
0513     .div        = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
0514     .mux        = _SUNXI_CCU_MUX(24, 2),
0515     .common     = {
0516         .reg        = 0xa40,
0517         .hw.init    = CLK_HW_INIT_PARENTS("dmic",
0518                               audio_parents,
0519                               &ccu_div_ops,
0520                               0),
0521     },
0522 };
0523 
0524 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
0525 
0526 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_1x_clk, "audio-codec-1x",
0527                  audio_parents, 0xa50,
0528                  0, 4,  /* M */
0529                  24, 2, /* mux */
0530                  BIT(31),   /* gate */
0531                  CLK_SET_RATE_PARENT);
0532 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x",
0533                  audio_parents, 0xa54,
0534                  0, 4,  /* M */
0535                  24, 2, /* mux */
0536                  BIT(31),   /* gate */
0537                  CLK_SET_RATE_PARENT);
0538 
0539 static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c,
0540         BIT(0), 0);
0541 
0542 static struct ccu_div audio_hub_clk = {
0543     .enable     = BIT(31),
0544     .div        = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
0545     .mux        = _SUNXI_CCU_MUX(24, 2),
0546     .common     = {
0547         .reg        = 0xa60,
0548         .hw.init    = CLK_HW_INIT_PARENTS("audio-hub",
0549                               audio_parents,
0550                               &ccu_div_ops,
0551                               0),
0552     },
0553 };
0554 
0555 static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0);
0556 
0557 /*
0558  * There are OHCI 12M clock source selection bits for the four USB 2.0 ports.
0559  * We will force them to 0 (12M divided from 48M).
0560  */
0561 #define SUN50I_H616_USB0_CLK_REG        0xa70
0562 #define SUN50I_H616_USB1_CLK_REG        0xa74
0563 #define SUN50I_H616_USB2_CLK_REG        0xa78
0564 #define SUN50I_H616_USB3_CLK_REG        0xa7c
0565 
0566 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
0567 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
0568 
0569 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
0570 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0);
0571 
0572 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M", 0xa78, BIT(31), 0);
0573 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 0xa78, BIT(29), 0);
0574 
0575 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
0576 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M", 0xa7c, BIT(29), 0);
0577 
0578 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
0579 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0);
0580 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb3", 0xa8c, BIT(2), 0);
0581 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
0582 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
0583 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0);
0584 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb3", 0xa8c, BIT(6), 0);
0585 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
0586 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
0587 
0588 static SUNXI_CCU_GATE(bus_keyadc_clk, "bus-keyadc", "apb1", 0xa9c, BIT(0), 0);
0589 
0590 static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-4x",
0591                          "pll-video2", "pll-video2-4x" };
0592 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00,
0593                  0, 4,      /* M */
0594                  24, 2,     /* mux */
0595                  BIT(31),   /* gate */
0596                  0);
0597 
0598 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
0599 
0600 static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
0601 static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = {
0602     { .index = 1, .div = 36621 },
0603 };
0604 
0605 #define SUN50I_H616_HDMI_CEC_CLK_REG        0xb10
0606 static struct ccu_mux hdmi_cec_clk = {
0607     .enable     = BIT(31) | BIT(30),
0608 
0609     .mux        = {
0610         .shift  = 24,
0611         .width  = 2,
0612 
0613         .fixed_predivs  = hdmi_cec_predivs,
0614         .n_predivs  = ARRAY_SIZE(hdmi_cec_predivs),
0615     },
0616 
0617     .common     = {
0618         .reg        = 0xb10,
0619         .features   = CCU_FEATURE_FIXED_PREDIV,
0620         .hw.init    = CLK_HW_INIT_PARENTS("hdmi-cec",
0621                               hdmi_cec_parents,
0622                               &ccu_mux_ops,
0623                               0),
0624     },
0625 };
0626 
0627 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
0628 
0629 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
0630               0xb5c, BIT(0), 0);
0631 
0632 static const char * const tcon_tv_parents[] = { "pll-video0",
0633                         "pll-video0-4x",
0634                         "pll-video1",
0635                         "pll-video1-4x" };
0636 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
0637                   tcon_tv_parents, 0xb80,
0638                   0, 4,     /* M */
0639                   8, 2,     /* P */
0640                   24, 3,    /* mux */
0641                   BIT(31),  /* gate */
0642                   CLK_SET_RATE_PARENT);
0643 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1",
0644                   tcon_tv_parents, 0xb84,
0645                   0, 4,     /* M */
0646                   8, 2,     /* P */
0647                   24, 3,    /* mux */
0648                   BIT(31),  /* gate */
0649                   CLK_SET_RATE_PARENT);
0650 
0651 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
0652               0xb9c, BIT(0), 0);
0653 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb3",
0654               0xb9c, BIT(1), 0);
0655 
0656 static SUNXI_CCU_MP_WITH_MUX_GATE(tve0_clk, "tve0",
0657                   tcon_tv_parents, 0xbb0,
0658                   0, 4,     /* M */
0659                   8, 2,     /* P */
0660                   24, 3,    /* mux */
0661                   BIT(31),  /* gate */
0662                   CLK_SET_RATE_PARENT);
0663 
0664 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb3",
0665               0xbbc, BIT(0), 0);
0666 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb3",
0667               0xbbc, BIT(1), 0);
0668 
0669 static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" };
0670 static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40,
0671                  0, 4,      /* M */
0672                  24, 2,     /* mux */
0673                  BIT(31),   /* gate */
0674                  0);
0675 
0676 static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
0677 
0678 /* Fixed factor clocks */
0679 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
0680 
0681 static const struct clk_hw *clk_parent_pll_audio[] = {
0682     &pll_audio_hs_clk.common.hw
0683 };
0684 
0685 /*
0686  * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
0687  * rates can be set exactly in conjunction with sigma-delta modulation.
0688  */
0689 static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x",
0690                 clk_parent_pll_audio,
0691                 96, 1, CLK_SET_RATE_PARENT);
0692 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
0693                 clk_parent_pll_audio,
0694                 48, 1, CLK_SET_RATE_PARENT);
0695 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
0696                 clk_parent_pll_audio,
0697                 24, 1, CLK_SET_RATE_PARENT);
0698 
0699 static const struct clk_hw *pll_periph0_parents[] = {
0700     &pll_periph0_clk.common.hw
0701 };
0702 
0703 static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
0704                 pll_periph0_parents,
0705                 1, 2, 0);
0706 
0707 static const struct clk_hw *pll_periph0_2x_hws[] = {
0708     &pll_periph0_2x_clk.hw
0709 };
0710 
0711 static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k",
0712                 pll_periph0_2x_hws, 36621, 1, 0);
0713 
0714 static const struct clk_hw *pll_periph1_parents[] = {
0715     &pll_periph1_clk.common.hw
0716 };
0717 
0718 static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
0719                 pll_periph1_parents,
0720                 1, 2, 0);
0721 
0722 static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
0723                &pll_video0_clk.common.hw,
0724                1, 4, CLK_SET_RATE_PARENT);
0725 static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
0726                &pll_video1_clk.common.hw,
0727                1, 4, CLK_SET_RATE_PARENT);
0728 static CLK_FIXED_FACTOR_HW(pll_video2_4x_clk, "pll-video2-4x",
0729                &pll_video2_clk.common.hw,
0730                1, 4, CLK_SET_RATE_PARENT);
0731 
0732 static struct ccu_common *sun50i_h616_ccu_clks[] = {
0733     &pll_cpux_clk.common,
0734     &pll_ddr0_clk.common,
0735     &pll_ddr1_clk.common,
0736     &pll_periph0_clk.common,
0737     &pll_periph1_clk.common,
0738     &pll_gpu_clk.common,
0739     &pll_video0_clk.common,
0740     &pll_video1_clk.common,
0741     &pll_video2_clk.common,
0742     &pll_ve_clk.common,
0743     &pll_de_clk.common,
0744     &pll_audio_hs_clk.common,
0745     &cpux_clk.common,
0746     &axi_clk.common,
0747     &cpux_apb_clk.common,
0748     &psi_ahb1_ahb2_clk.common,
0749     &ahb3_clk.common,
0750     &apb1_clk.common,
0751     &apb2_clk.common,
0752     &mbus_clk.common,
0753     &de_clk.common,
0754     &bus_de_clk.common,
0755     &deinterlace_clk.common,
0756     &bus_deinterlace_clk.common,
0757     &g2d_clk.common,
0758     &bus_g2d_clk.common,
0759     &gpu0_clk.common,
0760     &bus_gpu_clk.common,
0761     &gpu1_clk.common,
0762     &ce_clk.common,
0763     &bus_ce_clk.common,
0764     &ve_clk.common,
0765     &bus_ve_clk.common,
0766     &bus_dma_clk.common,
0767     &bus_hstimer_clk.common,
0768     &avs_clk.common,
0769     &bus_dbg_clk.common,
0770     &bus_psi_clk.common,
0771     &bus_pwm_clk.common,
0772     &bus_iommu_clk.common,
0773     &dram_clk.common,
0774     &mbus_dma_clk.common,
0775     &mbus_ve_clk.common,
0776     &mbus_ce_clk.common,
0777     &mbus_ts_clk.common,
0778     &mbus_nand_clk.common,
0779     &mbus_g2d_clk.common,
0780     &bus_dram_clk.common,
0781     &nand0_clk.common,
0782     &nand1_clk.common,
0783     &bus_nand_clk.common,
0784     &mmc0_clk.common,
0785     &mmc1_clk.common,
0786     &mmc2_clk.common,
0787     &bus_mmc0_clk.common,
0788     &bus_mmc1_clk.common,
0789     &bus_mmc2_clk.common,
0790     &bus_uart0_clk.common,
0791     &bus_uart1_clk.common,
0792     &bus_uart2_clk.common,
0793     &bus_uart3_clk.common,
0794     &bus_uart4_clk.common,
0795     &bus_uart5_clk.common,
0796     &bus_i2c0_clk.common,
0797     &bus_i2c1_clk.common,
0798     &bus_i2c2_clk.common,
0799     &bus_i2c3_clk.common,
0800     &bus_i2c4_clk.common,
0801     &spi0_clk.common,
0802     &spi1_clk.common,
0803     &bus_spi0_clk.common,
0804     &bus_spi1_clk.common,
0805     &emac_25m_clk.common,
0806     &bus_emac0_clk.common,
0807     &bus_emac1_clk.common,
0808     &ts_clk.common,
0809     &bus_ts_clk.common,
0810     &bus_ths_clk.common,
0811     &spdif_clk.common,
0812     &bus_spdif_clk.common,
0813     &dmic_clk.common,
0814     &bus_dmic_clk.common,
0815     &audio_codec_1x_clk.common,
0816     &audio_codec_4x_clk.common,
0817     &bus_audio_codec_clk.common,
0818     &audio_hub_clk.common,
0819     &bus_audio_hub_clk.common,
0820     &usb_ohci0_clk.common,
0821     &usb_phy0_clk.common,
0822     &usb_ohci1_clk.common,
0823     &usb_phy1_clk.common,
0824     &usb_ohci2_clk.common,
0825     &usb_phy2_clk.common,
0826     &usb_ohci3_clk.common,
0827     &usb_phy3_clk.common,
0828     &bus_ohci0_clk.common,
0829     &bus_ohci1_clk.common,
0830     &bus_ohci2_clk.common,
0831     &bus_ohci3_clk.common,
0832     &bus_ehci0_clk.common,
0833     &bus_ehci1_clk.common,
0834     &bus_ehci2_clk.common,
0835     &bus_ehci3_clk.common,
0836     &bus_otg_clk.common,
0837     &bus_keyadc_clk.common,
0838     &hdmi_clk.common,
0839     &hdmi_slow_clk.common,
0840     &hdmi_cec_clk.common,
0841     &bus_hdmi_clk.common,
0842     &bus_tcon_top_clk.common,
0843     &tcon_tv0_clk.common,
0844     &tcon_tv1_clk.common,
0845     &bus_tcon_tv0_clk.common,
0846     &bus_tcon_tv1_clk.common,
0847     &tve0_clk.common,
0848     &bus_tve_top_clk.common,
0849     &bus_tve0_clk.common,
0850     &hdcp_clk.common,
0851     &bus_hdcp_clk.common,
0852 };
0853 
0854 static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
0855     .hws    = {
0856         [CLK_OSC12M]        = &osc12M_clk.hw,
0857         [CLK_PLL_CPUX]      = &pll_cpux_clk.common.hw,
0858         [CLK_PLL_DDR0]      = &pll_ddr0_clk.common.hw,
0859         [CLK_PLL_DDR1]      = &pll_ddr1_clk.common.hw,
0860         [CLK_PLL_PERIPH0]   = &pll_periph0_clk.common.hw,
0861         [CLK_PLL_PERIPH0_2X]    = &pll_periph0_2x_clk.hw,
0862         [CLK_PLL_SYSTEM_32K]    = &pll_system_32k_clk.hw,
0863         [CLK_PLL_PERIPH1]   = &pll_periph1_clk.common.hw,
0864         [CLK_PLL_PERIPH1_2X]    = &pll_periph1_2x_clk.hw,
0865         [CLK_PLL_GPU]       = &pll_gpu_clk.common.hw,
0866         [CLK_PLL_VIDEO0]    = &pll_video0_clk.common.hw,
0867         [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw,
0868         [CLK_PLL_VIDEO1]    = &pll_video1_clk.common.hw,
0869         [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw,
0870         [CLK_PLL_VIDEO2]    = &pll_video2_clk.common.hw,
0871         [CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.hw,
0872         [CLK_PLL_VE]        = &pll_ve_clk.common.hw,
0873         [CLK_PLL_DE]        = &pll_de_clk.common.hw,
0874         [CLK_PLL_AUDIO_HS]  = &pll_audio_hs_clk.common.hw,
0875         [CLK_PLL_AUDIO_1X]  = &pll_audio_1x_clk.hw,
0876         [CLK_PLL_AUDIO_2X]  = &pll_audio_2x_clk.hw,
0877         [CLK_PLL_AUDIO_4X]  = &pll_audio_4x_clk.hw,
0878         [CLK_CPUX]      = &cpux_clk.common.hw,
0879         [CLK_AXI]       = &axi_clk.common.hw,
0880         [CLK_CPUX_APB]      = &cpux_apb_clk.common.hw,
0881         [CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw,
0882         [CLK_AHB3]      = &ahb3_clk.common.hw,
0883         [CLK_APB1]      = &apb1_clk.common.hw,
0884         [CLK_APB2]      = &apb2_clk.common.hw,
0885         [CLK_MBUS]      = &mbus_clk.common.hw,
0886         [CLK_DE]        = &de_clk.common.hw,
0887         [CLK_BUS_DE]        = &bus_de_clk.common.hw,
0888         [CLK_DEINTERLACE]   = &deinterlace_clk.common.hw,
0889         [CLK_BUS_DEINTERLACE]   = &bus_deinterlace_clk.common.hw,
0890         [CLK_G2D]       = &g2d_clk.common.hw,
0891         [CLK_BUS_G2D]       = &bus_g2d_clk.common.hw,
0892         [CLK_GPU0]      = &gpu0_clk.common.hw,
0893         [CLK_BUS_GPU]       = &bus_gpu_clk.common.hw,
0894         [CLK_GPU1]      = &gpu1_clk.common.hw,
0895         [CLK_CE]        = &ce_clk.common.hw,
0896         [CLK_BUS_CE]        = &bus_ce_clk.common.hw,
0897         [CLK_VE]        = &ve_clk.common.hw,
0898         [CLK_BUS_VE]        = &bus_ve_clk.common.hw,
0899         [CLK_BUS_DMA]       = &bus_dma_clk.common.hw,
0900         [CLK_BUS_HSTIMER]   = &bus_hstimer_clk.common.hw,
0901         [CLK_AVS]       = &avs_clk.common.hw,
0902         [CLK_BUS_DBG]       = &bus_dbg_clk.common.hw,
0903         [CLK_BUS_PSI]       = &bus_psi_clk.common.hw,
0904         [CLK_BUS_PWM]       = &bus_pwm_clk.common.hw,
0905         [CLK_BUS_IOMMU]     = &bus_iommu_clk.common.hw,
0906         [CLK_DRAM]      = &dram_clk.common.hw,
0907         [CLK_MBUS_DMA]      = &mbus_dma_clk.common.hw,
0908         [CLK_MBUS_VE]       = &mbus_ve_clk.common.hw,
0909         [CLK_MBUS_CE]       = &mbus_ce_clk.common.hw,
0910         [CLK_MBUS_TS]       = &mbus_ts_clk.common.hw,
0911         [CLK_MBUS_NAND]     = &mbus_nand_clk.common.hw,
0912         [CLK_MBUS_G2D]      = &mbus_g2d_clk.common.hw,
0913         [CLK_BUS_DRAM]      = &bus_dram_clk.common.hw,
0914         [CLK_NAND0]     = &nand0_clk.common.hw,
0915         [CLK_NAND1]     = &nand1_clk.common.hw,
0916         [CLK_BUS_NAND]      = &bus_nand_clk.common.hw,
0917         [CLK_MMC0]      = &mmc0_clk.common.hw,
0918         [CLK_MMC1]      = &mmc1_clk.common.hw,
0919         [CLK_MMC2]      = &mmc2_clk.common.hw,
0920         [CLK_BUS_MMC0]      = &bus_mmc0_clk.common.hw,
0921         [CLK_BUS_MMC1]      = &bus_mmc1_clk.common.hw,
0922         [CLK_BUS_MMC2]      = &bus_mmc2_clk.common.hw,
0923         [CLK_BUS_UART0]     = &bus_uart0_clk.common.hw,
0924         [CLK_BUS_UART1]     = &bus_uart1_clk.common.hw,
0925         [CLK_BUS_UART2]     = &bus_uart2_clk.common.hw,
0926         [CLK_BUS_UART3]     = &bus_uart3_clk.common.hw,
0927         [CLK_BUS_UART4]     = &bus_uart4_clk.common.hw,
0928         [CLK_BUS_UART5]     = &bus_uart5_clk.common.hw,
0929         [CLK_BUS_I2C0]      = &bus_i2c0_clk.common.hw,
0930         [CLK_BUS_I2C1]      = &bus_i2c1_clk.common.hw,
0931         [CLK_BUS_I2C2]      = &bus_i2c2_clk.common.hw,
0932         [CLK_BUS_I2C3]      = &bus_i2c3_clk.common.hw,
0933         [CLK_BUS_I2C4]      = &bus_i2c4_clk.common.hw,
0934         [CLK_SPI0]      = &spi0_clk.common.hw,
0935         [CLK_SPI1]      = &spi1_clk.common.hw,
0936         [CLK_BUS_SPI0]      = &bus_spi0_clk.common.hw,
0937         [CLK_BUS_SPI1]      = &bus_spi1_clk.common.hw,
0938         [CLK_EMAC_25M]      = &emac_25m_clk.common.hw,
0939         [CLK_BUS_EMAC0]     = &bus_emac0_clk.common.hw,
0940         [CLK_BUS_EMAC1]     = &bus_emac1_clk.common.hw,
0941         [CLK_TS]        = &ts_clk.common.hw,
0942         [CLK_BUS_TS]        = &bus_ts_clk.common.hw,
0943         [CLK_BUS_THS]       = &bus_ths_clk.common.hw,
0944         [CLK_SPDIF]     = &spdif_clk.common.hw,
0945         [CLK_BUS_SPDIF]     = &bus_spdif_clk.common.hw,
0946         [CLK_DMIC]      = &dmic_clk.common.hw,
0947         [CLK_BUS_DMIC]      = &bus_dmic_clk.common.hw,
0948         [CLK_AUDIO_CODEC_1X]    = &audio_codec_1x_clk.common.hw,
0949         [CLK_AUDIO_CODEC_4X]    = &audio_codec_4x_clk.common.hw,
0950         [CLK_BUS_AUDIO_CODEC]   = &bus_audio_codec_clk.common.hw,
0951         [CLK_AUDIO_HUB]     = &audio_hub_clk.common.hw,
0952         [CLK_BUS_AUDIO_HUB] = &bus_audio_hub_clk.common.hw,
0953         [CLK_USB_OHCI0]     = &usb_ohci0_clk.common.hw,
0954         [CLK_USB_PHY0]      = &usb_phy0_clk.common.hw,
0955         [CLK_USB_OHCI1]     = &usb_ohci1_clk.common.hw,
0956         [CLK_USB_PHY1]      = &usb_phy1_clk.common.hw,
0957         [CLK_USB_OHCI2]     = &usb_ohci2_clk.common.hw,
0958         [CLK_USB_PHY2]      = &usb_phy2_clk.common.hw,
0959         [CLK_USB_OHCI3]     = &usb_ohci3_clk.common.hw,
0960         [CLK_USB_PHY3]      = &usb_phy3_clk.common.hw,
0961         [CLK_BUS_OHCI0]     = &bus_ohci0_clk.common.hw,
0962         [CLK_BUS_OHCI1]     = &bus_ohci1_clk.common.hw,
0963         [CLK_BUS_OHCI2]     = &bus_ohci2_clk.common.hw,
0964         [CLK_BUS_OHCI3]     = &bus_ohci3_clk.common.hw,
0965         [CLK_BUS_EHCI0]     = &bus_ehci0_clk.common.hw,
0966         [CLK_BUS_EHCI1]     = &bus_ehci1_clk.common.hw,
0967         [CLK_BUS_EHCI2]     = &bus_ehci2_clk.common.hw,
0968         [CLK_BUS_EHCI3]     = &bus_ehci3_clk.common.hw,
0969         [CLK_BUS_OTG]       = &bus_otg_clk.common.hw,
0970         [CLK_BUS_KEYADC]    = &bus_keyadc_clk.common.hw,
0971         [CLK_HDMI]      = &hdmi_clk.common.hw,
0972         [CLK_HDMI_SLOW]     = &hdmi_slow_clk.common.hw,
0973         [CLK_HDMI_CEC]      = &hdmi_cec_clk.common.hw,
0974         [CLK_BUS_HDMI]      = &bus_hdmi_clk.common.hw,
0975         [CLK_BUS_TCON_TOP]  = &bus_tcon_top_clk.common.hw,
0976         [CLK_TCON_TV0]      = &tcon_tv0_clk.common.hw,
0977         [CLK_TCON_TV1]      = &tcon_tv1_clk.common.hw,
0978         [CLK_BUS_TCON_TV0]  = &bus_tcon_tv0_clk.common.hw,
0979         [CLK_BUS_TCON_TV1]  = &bus_tcon_tv1_clk.common.hw,
0980         [CLK_TVE0]      = &tve0_clk.common.hw,
0981         [CLK_BUS_TVE_TOP]   = &bus_tve_top_clk.common.hw,
0982         [CLK_BUS_TVE0]      = &bus_tve0_clk.common.hw,
0983         [CLK_HDCP]      = &hdcp_clk.common.hw,
0984         [CLK_BUS_HDCP]      = &bus_hdcp_clk.common.hw,
0985     },
0986     .num = CLK_NUMBER,
0987 };
0988 
0989 static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
0990     [RST_MBUS]      = { 0x540, BIT(30) },
0991 
0992     [RST_BUS_DE]        = { 0x60c, BIT(16) },
0993     [RST_BUS_DEINTERLACE]   = { 0x62c, BIT(16) },
0994     [RST_BUS_GPU]       = { 0x67c, BIT(16) },
0995     [RST_BUS_CE]        = { 0x68c, BIT(16) },
0996     [RST_BUS_VE]        = { 0x69c, BIT(16) },
0997     [RST_BUS_DMA]       = { 0x70c, BIT(16) },
0998     [RST_BUS_HSTIMER]   = { 0x73c, BIT(16) },
0999     [RST_BUS_DBG]       = { 0x78c, BIT(16) },
1000     [RST_BUS_PSI]       = { 0x79c, BIT(16) },
1001     [RST_BUS_PWM]       = { 0x7ac, BIT(16) },
1002     [RST_BUS_IOMMU]     = { 0x7bc, BIT(16) },
1003     [RST_BUS_DRAM]      = { 0x80c, BIT(16) },
1004     [RST_BUS_NAND]      = { 0x82c, BIT(16) },
1005     [RST_BUS_MMC0]      = { 0x84c, BIT(16) },
1006     [RST_BUS_MMC1]      = { 0x84c, BIT(17) },
1007     [RST_BUS_MMC2]      = { 0x84c, BIT(18) },
1008     [RST_BUS_UART0]     = { 0x90c, BIT(16) },
1009     [RST_BUS_UART1]     = { 0x90c, BIT(17) },
1010     [RST_BUS_UART2]     = { 0x90c, BIT(18) },
1011     [RST_BUS_UART3]     = { 0x90c, BIT(19) },
1012     [RST_BUS_UART4]     = { 0x90c, BIT(20) },
1013     [RST_BUS_UART5]     = { 0x90c, BIT(21) },
1014     [RST_BUS_I2C0]      = { 0x91c, BIT(16) },
1015     [RST_BUS_I2C1]      = { 0x91c, BIT(17) },
1016     [RST_BUS_I2C2]      = { 0x91c, BIT(18) },
1017     [RST_BUS_I2C3]      = { 0x91c, BIT(19) },
1018     [RST_BUS_I2C4]      = { 0x91c, BIT(20) },
1019     [RST_BUS_SPI0]      = { 0x96c, BIT(16) },
1020     [RST_BUS_SPI1]      = { 0x96c, BIT(17) },
1021     [RST_BUS_EMAC0]     = { 0x97c, BIT(16) },
1022     [RST_BUS_EMAC1]     = { 0x97c, BIT(17) },
1023     [RST_BUS_TS]        = { 0x9bc, BIT(16) },
1024     [RST_BUS_THS]       = { 0x9fc, BIT(16) },
1025     [RST_BUS_SPDIF]     = { 0xa2c, BIT(16) },
1026     [RST_BUS_DMIC]      = { 0xa4c, BIT(16) },
1027     [RST_BUS_AUDIO_CODEC]   = { 0xa5c, BIT(16) },
1028     [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) },
1029 
1030     [RST_USB_PHY0]      = { 0xa70, BIT(30) },
1031     [RST_USB_PHY1]      = { 0xa74, BIT(30) },
1032     [RST_USB_PHY2]      = { 0xa78, BIT(30) },
1033     [RST_USB_PHY3]      = { 0xa7c, BIT(30) },
1034     [RST_BUS_OHCI0]     = { 0xa8c, BIT(16) },
1035     [RST_BUS_OHCI1]     = { 0xa8c, BIT(17) },
1036     [RST_BUS_OHCI2]     = { 0xa8c, BIT(18) },
1037     [RST_BUS_OHCI3]     = { 0xa8c, BIT(19) },
1038     [RST_BUS_EHCI0]     = { 0xa8c, BIT(20) },
1039     [RST_BUS_EHCI1]     = { 0xa8c, BIT(21) },
1040     [RST_BUS_EHCI2]     = { 0xa8c, BIT(22) },
1041     [RST_BUS_EHCI3]     = { 0xa8c, BIT(23) },
1042     [RST_BUS_OTG]       = { 0xa8c, BIT(24) },
1043     [RST_BUS_KEYADC]    = { 0xa9c, BIT(16) },
1044 
1045     [RST_BUS_HDMI]      = { 0xb1c, BIT(16) },
1046     [RST_BUS_HDMI_SUB]  = { 0xb1c, BIT(17) },
1047     [RST_BUS_TCON_TOP]  = { 0xb5c, BIT(16) },
1048     [RST_BUS_TCON_TV0]  = { 0xb9c, BIT(16) },
1049     [RST_BUS_TCON_TV1]  = { 0xb9c, BIT(17) },
1050     [RST_BUS_TVE_TOP]   = { 0xbbc, BIT(16) },
1051     [RST_BUS_TVE0]      = { 0xbbc, BIT(17) },
1052     [RST_BUS_HDCP]      = { 0xc4c, BIT(16) },
1053 };
1054 
1055 static const struct sunxi_ccu_desc sun50i_h616_ccu_desc = {
1056     .ccu_clks   = sun50i_h616_ccu_clks,
1057     .num_ccu_clks   = ARRAY_SIZE(sun50i_h616_ccu_clks),
1058 
1059     .hw_clks    = &sun50i_h616_hw_clks,
1060 
1061     .resets     = sun50i_h616_ccu_resets,
1062     .num_resets = ARRAY_SIZE(sun50i_h616_ccu_resets),
1063 };
1064 
1065 static const u32 pll_regs[] = {
1066     SUN50I_H616_PLL_CPUX_REG,
1067     SUN50I_H616_PLL_DDR0_REG,
1068     SUN50I_H616_PLL_DDR1_REG,
1069     SUN50I_H616_PLL_PERIPH0_REG,
1070     SUN50I_H616_PLL_PERIPH1_REG,
1071     SUN50I_H616_PLL_GPU_REG,
1072     SUN50I_H616_PLL_VIDEO0_REG,
1073     SUN50I_H616_PLL_VIDEO1_REG,
1074     SUN50I_H616_PLL_VIDEO2_REG,
1075     SUN50I_H616_PLL_VE_REG,
1076     SUN50I_H616_PLL_DE_REG,
1077     SUN50I_H616_PLL_AUDIO_REG,
1078 };
1079 
1080 static const u32 pll_video_regs[] = {
1081     SUN50I_H616_PLL_VIDEO0_REG,
1082     SUN50I_H616_PLL_VIDEO1_REG,
1083     SUN50I_H616_PLL_VIDEO2_REG,
1084 };
1085 
1086 static const u32 usb2_clk_regs[] = {
1087     SUN50I_H616_USB0_CLK_REG,
1088     SUN50I_H616_USB1_CLK_REG,
1089     SUN50I_H616_USB2_CLK_REG,
1090     SUN50I_H616_USB3_CLK_REG,
1091 };
1092 
1093 static int sun50i_h616_ccu_probe(struct platform_device *pdev)
1094 {
1095     void __iomem *reg;
1096     u32 val;
1097     int i;
1098 
1099     reg = devm_platform_ioremap_resource(pdev, 0);
1100     if (IS_ERR(reg))
1101         return PTR_ERR(reg);
1102 
1103     /* Enable the lock bits and the output enable bits on all PLLs */
1104     for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
1105         val = readl(reg + pll_regs[i]);
1106         val |= BIT(29) | BIT(27);
1107         writel(val, reg + pll_regs[i]);
1108     }
1109 
1110     /*
1111      * Force the output divider of video PLLs to 0.
1112      *
1113      * See the comment before pll-video0 definition for the reason.
1114      */
1115     for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
1116         val = readl(reg + pll_video_regs[i]);
1117         val &= ~BIT(0);
1118         writel(val, reg + pll_video_regs[i]);
1119     }
1120 
1121     /*
1122      * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
1123      *
1124      * This clock mux is still mysterious, and the code just enforces
1125      * it to have a valid clock parent.
1126      */
1127     for (i = 0; i < ARRAY_SIZE(usb2_clk_regs); i++) {
1128         val = readl(reg + usb2_clk_regs[i]);
1129         val &= ~GENMASK(25, 24);
1130         writel(val, reg + usb2_clk_regs[i]);
1131     }
1132 
1133     /*
1134      * Force the post-divider of pll-audio to 12 and the output divider
1135      * of it to 2, so 24576000 and 22579200 rates can be set exactly.
1136      */
1137     val = readl(reg + SUN50I_H616_PLL_AUDIO_REG);
1138     val &= ~(GENMASK(21, 16) | BIT(0));
1139     writel(val | (11 << 16) | BIT(0), reg + SUN50I_H616_PLL_AUDIO_REG);
1140 
1141     /*
1142      * First clock parent (osc32K) is unusable for CEC. But since there
1143      * is no good way to force parent switch (both run with same frequency),
1144      * just set second clock parent here.
1145      */
1146     val = readl(reg + SUN50I_H616_HDMI_CEC_CLK_REG);
1147     val |= BIT(24);
1148     writel(val, reg + SUN50I_H616_HDMI_CEC_CLK_REG);
1149 
1150     return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc);
1151 }
1152 
1153 static const struct of_device_id sun50i_h616_ccu_ids[] = {
1154     { .compatible = "allwinner,sun50i-h616-ccu" },
1155     { }
1156 };
1157 
1158 static struct platform_driver sun50i_h616_ccu_driver = {
1159     .probe  = sun50i_h616_ccu_probe,
1160     .driver = {
1161         .name           = "sun50i-h616-ccu",
1162         .suppress_bind_attrs    = true,
1163         .of_match_table     = sun50i_h616_ccu_ids,
1164     },
1165 };
1166 module_platform_driver(sun50i_h616_ccu_driver);
1167 
1168 MODULE_IMPORT_NS(SUNXI_CCU);
1169 MODULE_LICENSE("GPL");
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