clk/sunxi-ng/ccu-sun50i-h6.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2016 Icenowy Zheng <icenowy@aosc.io>
0004  */
0005
0006 #ifndef _CCU_SUN50I_H6_H_
0007 #define _CCU_SUN50I_H6_H_
0008
0009 #include <dt-bindings/clock/sun50i-h6-ccu.h>
0010 #include <dt-bindings/reset/sun50i-h6-ccu.h>
0011
0012 #define CLK_OSC12M      0
0013 #define CLK_PLL_CPUX        1
0014 #define CLK_PLL_DDR0        2
0015
0016 /* PLL_PERIPH0 exported for PRCM */
0017
0018 #define CLK_PLL_PERIPH0_2X  4
0019 #define CLK_PLL_PERIPH0_4X  5
0020 #define CLK_PLL_PERIPH1     6
0021 #define CLK_PLL_PERIPH1_2X  7
0022 #define CLK_PLL_PERIPH1_4X  8
0023 #define CLK_PLL_GPU     9
0024 #define CLK_PLL_VIDEO0      10
0025 #define CLK_PLL_VIDEO0_4X   11
0026 #define CLK_PLL_VIDEO1      12
0027 #define CLK_PLL_VIDEO1_4X   13
0028 #define CLK_PLL_VE      14
0029 #define CLK_PLL_DE      15
0030 #define CLK_PLL_HSIC        16
0031 #define CLK_PLL_AUDIO_BASE  17
0032 #define CLK_PLL_AUDIO       18
0033 #define CLK_PLL_AUDIO_2X    19
0034 #define CLK_PLL_AUDIO_4X    20
0035
0036 /* CPUX clock exported for DVFS */
0037
0038 #define CLK_AXI         22
0039 #define CLK_CPUX_APB        23
0040 #define CLK_PSI_AHB1_AHB2   24
0041 #define CLK_AHB3        25
0042
0043 /* APB1 clock exported for PIO */
0044
0045 #define CLK_APB2        27
0046 #define CLK_MBUS        28
0047
0048 /* All module clocks and bus gates are exported except DRAM */
0049
0050 #define CLK_DRAM        52
0051
0052 #define CLK_BUS_DRAM        60
0053
0054 #define CLK_NUMBER      (CLK_BUS_HDCP + 1)
0055
0056 #endif /* _CCU_SUN50I_H6_H_ */