clk/sunxi-ng/ccu-sun50i-a64.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2016 Maxime Ripard
0004  *
0005  * Maxime Ripard <maxime.ripard@free-electrons.com>
0006  */
0007
0008 #ifndef _CCU_SUN50I_A64_H_
0009 #define _CCU_SUN50I_A64_H_
0010
0011 #include <dt-bindings/clock/sun50i-a64-ccu.h>
0012 #include <dt-bindings/reset/sun50i-a64-ccu.h>
0013
0014 #define CLK_OSC_12M         0
0015 #define CLK_PLL_CPUX            1
0016 #define CLK_PLL_AUDIO_BASE      2
0017 #define CLK_PLL_AUDIO           3
0018 #define CLK_PLL_AUDIO_2X        4
0019 #define CLK_PLL_AUDIO_4X        5
0020 #define CLK_PLL_AUDIO_8X        6
0021
0022 /* PLL_VIDEO0 exported for HDMI PHY */
0023
0024 #define CLK_PLL_VIDEO0_2X       8
0025 #define CLK_PLL_VE          9
0026 #define CLK_PLL_DDR0            10
0027
0028 /* PLL_PERIPH0 exported for PRCM */
0029
0030 #define CLK_PLL_PERIPH0_2X      12
0031 #define CLK_PLL_PERIPH1         13
0032 #define CLK_PLL_PERIPH1_2X      14
0033 #define CLK_PLL_VIDEO1          15
0034 #define CLK_PLL_GPU         16
0035 #define CLK_PLL_MIPI            17
0036 #define CLK_PLL_HSIC            18
0037 #define CLK_PLL_DE          19
0038 #define CLK_PLL_DDR1            20
0039 #define CLK_AXI             22
0040 #define CLK_APB             23
0041 #define CLK_AHB1            24
0042 #define CLK_APB1            25
0043 #define CLK_APB2            26
0044 #define CLK_AHB2            27
0045
0046 /* All the bus gates are exported */
0047
0048 /* The first bunch of module clocks are exported */
0049
0050 #define CLK_USB_OHCI0_12M       90
0051
0052 #define CLK_USB_OHCI1_12M       92
0053
0054 /* All the DRAM gates are exported */
0055
0056 /* And the DSI and GPU module clock is exported */
0057
0058 #define CLK_NUMBER          (CLK_GPU + 1)
0059
0060 #endif /* _CCU_SUN50I_A64_H_ */