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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
0004  */
0005 
0006 #include <linux/clk-provider.h>
0007 #include <linux/io.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 
0011 #include "ccu_common.h"
0012 #include "ccu_reset.h"
0013 
0014 #include "ccu_div.h"
0015 #include "ccu_gate.h"
0016 #include "ccu_mp.h"
0017 #include "ccu_mult.h"
0018 #include "ccu_nk.h"
0019 #include "ccu_nkm.h"
0020 #include "ccu_nkmp.h"
0021 #include "ccu_nm.h"
0022 #include "ccu_phase.h"
0023 
0024 #include "ccu-sun50i-a64.h"
0025 
0026 static struct ccu_nkmp pll_cpux_clk = {
0027     .enable     = BIT(31),
0028     .lock       = BIT(28),
0029     .n      = _SUNXI_CCU_MULT(8, 5),
0030     .k      = _SUNXI_CCU_MULT(4, 2),
0031     .m      = _SUNXI_CCU_DIV(0, 2),
0032     .p      = _SUNXI_CCU_DIV_MAX(16, 2, 4),
0033     .common     = {
0034         .reg        = 0x000,
0035         .hw.init    = CLK_HW_INIT("pll-cpux",
0036                           "osc24M",
0037                           &ccu_nkmp_ops,
0038                           CLK_SET_RATE_UNGATE),
0039     },
0040 };
0041 
0042 /*
0043  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
0044  * the base (2x, 4x and 8x), and one variable divider (the one true
0045  * pll audio).
0046  *
0047  * With sigma-delta modulation for fractional-N on the audio PLL,
0048  * we have to use specific dividers. This means the variable divider
0049  * can no longer be used, as the audio codec requests the exact clock
0050  * rates we support through this mechanism. So we now hard code the
0051  * variable divider to 1. This means the clock rates will no longer
0052  * match the clock names.
0053  */
0054 #define SUN50I_A64_PLL_AUDIO_REG    0x008
0055 
0056 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
0057     { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
0058     { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
0059 };
0060 
0061 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
0062                        "osc24M", 0x008,
0063                        8, 7,    /* N */
0064                        0, 5,    /* M */
0065                        pll_audio_sdm_table, BIT(24),
0066                        0x284, BIT(31),
0067                        BIT(31), /* gate */
0068                        BIT(28), /* lock */
0069                        CLK_SET_RATE_UNGATE);
0070 
0071 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
0072                         "osc24M", 0x010,
0073                         192000000,  /* Minimum rate */
0074                         1008000000, /* Maximum rate */
0075                         8, 7,       /* N */
0076                         0, 4,       /* M */
0077                         BIT(24),    /* frac enable */
0078                         BIT(25),    /* frac select */
0079                         270000000,  /* frac rate 0 */
0080                         297000000,  /* frac rate 1 */
0081                         BIT(31),    /* gate */
0082                         BIT(28),    /* lock */
0083                         CLK_SET_RATE_UNGATE);
0084 
0085 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
0086                     "osc24M", 0x018,
0087                     8, 7,       /* N */
0088                     0, 4,       /* M */
0089                     BIT(24),    /* frac enable */
0090                     BIT(25),    /* frac select */
0091                     270000000,  /* frac rate 0 */
0092                     297000000,  /* frac rate 1 */
0093                     BIT(31),    /* gate */
0094                     BIT(28),    /* lock */
0095                     CLK_SET_RATE_UNGATE);
0096 
0097 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
0098                     "osc24M", 0x020,
0099                     8, 5,   /* N */
0100                     4, 2,   /* K */
0101                     0, 2,   /* M */
0102                     BIT(31),    /* gate */
0103                     BIT(28),    /* lock */
0104                     CLK_SET_RATE_UNGATE);
0105 
0106 static struct ccu_nk pll_periph0_clk = {
0107     .enable     = BIT(31),
0108     .lock       = BIT(28),
0109     .n      = _SUNXI_CCU_MULT(8, 5),
0110     .k      = _SUNXI_CCU_MULT_MIN(4, 2, 2),
0111     .fixed_post_div = 2,
0112     .common     = {
0113         .reg        = 0x028,
0114         .features   = CCU_FEATURE_FIXED_POSTDIV,
0115         .hw.init    = CLK_HW_INIT("pll-periph0", "osc24M",
0116                           &ccu_nk_ops, CLK_SET_RATE_UNGATE),
0117     },
0118 };
0119 
0120 static struct ccu_nk pll_periph1_clk = {
0121     .enable     = BIT(31),
0122     .lock       = BIT(28),
0123     .n      = _SUNXI_CCU_MULT(8, 5),
0124     .k      = _SUNXI_CCU_MULT_MIN(4, 2, 2),
0125     .fixed_post_div = 2,
0126     .common     = {
0127         .reg        = 0x02c,
0128         .features   = CCU_FEATURE_FIXED_POSTDIV,
0129         .hw.init    = CLK_HW_INIT("pll-periph1", "osc24M",
0130                           &ccu_nk_ops, CLK_SET_RATE_UNGATE),
0131     },
0132 };
0133 
0134 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
0135                         "osc24M", 0x030,
0136                         192000000,  /* Minimum rate */
0137                         1008000000, /* Maximum rate */
0138                         8, 7,       /* N */
0139                         0, 4,       /* M */
0140                         BIT(24),    /* frac enable */
0141                         BIT(25),    /* frac select */
0142                         270000000,  /* frac rate 0 */
0143                         297000000,  /* frac rate 1 */
0144                         BIT(31),    /* gate */
0145                         BIT(28),    /* lock */
0146                         CLK_SET_RATE_UNGATE);
0147 
0148 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
0149                     "osc24M", 0x038,
0150                     8, 7,       /* N */
0151                     0, 4,       /* M */
0152                     BIT(24),    /* frac enable */
0153                     BIT(25),    /* frac select */
0154                     270000000,  /* frac rate 0 */
0155                     297000000,  /* frac rate 1 */
0156                     BIT(31),    /* gate */
0157                     BIT(28),    /* lock */
0158                     CLK_SET_RATE_UNGATE);
0159 
0160 /*
0161  * The output function can be changed to something more complex that
0162  * we do not handle yet.
0163  *
0164  * Hardcode the mode so that we don't fall in that case.
0165  */
0166 #define SUN50I_A64_PLL_MIPI_REG     0x040
0167 
0168 static struct ccu_nkm pll_mipi_clk = {
0169     /*
0170      * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
0171      * user manual, and by experiments the PLL doesn't work without
0172      * these bits toggled.
0173      */
0174     .enable     = BIT(31) | BIT(23) | BIT(22),
0175     .lock       = BIT(28),
0176     .n      = _SUNXI_CCU_MULT(8, 4),
0177     .k      = _SUNXI_CCU_MULT_MIN(4, 2, 2),
0178     .m      = _SUNXI_CCU_DIV(0, 4),
0179     .common     = {
0180         .reg        = 0x040,
0181         .hw.init    = CLK_HW_INIT("pll-mipi", "pll-video0",
0182                           &ccu_nkm_ops, CLK_SET_RATE_UNGATE),
0183     },
0184 };
0185 
0186 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
0187                     "osc24M", 0x044,
0188                     8, 7,       /* N */
0189                     0, 4,       /* M */
0190                     BIT(24),    /* frac enable */
0191                     BIT(25),    /* frac select */
0192                     270000000,  /* frac rate 0 */
0193                     297000000,  /* frac rate 1 */
0194                     BIT(31),    /* gate */
0195                     BIT(28),    /* lock */
0196                     CLK_SET_RATE_UNGATE);
0197 
0198 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
0199                     "osc24M", 0x048,
0200                     8, 7,       /* N */
0201                     0, 4,       /* M */
0202                     BIT(24),    /* frac enable */
0203                     BIT(25),    /* frac select */
0204                     270000000,  /* frac rate 0 */
0205                     297000000,  /* frac rate 1 */
0206                     BIT(31),    /* gate */
0207                     BIT(28),    /* lock */
0208                     CLK_SET_RATE_UNGATE);
0209 
0210 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
0211                    "osc24M", 0x04c,
0212                    8, 7,    /* N */
0213                    0, 2,    /* M */
0214                    BIT(31), /* gate */
0215                    BIT(28), /* lock */
0216                    CLK_SET_RATE_UNGATE);
0217 
0218 static const char * const cpux_parents[] = { "osc32k", "osc24M",
0219                          "pll-cpux", "pll-cpux" };
0220 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0221              0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
0222 
0223 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
0224 
0225 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
0226                          "axi", "pll-periph0" };
0227 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
0228     { .index = 3, .shift = 6, .width = 2 },
0229 };
0230 static struct ccu_div ahb1_clk = {
0231     .div        = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
0232 
0233     .mux        = {
0234         .shift  = 12,
0235         .width  = 2,
0236 
0237         .var_predivs    = ahb1_predivs,
0238         .n_var_predivs  = ARRAY_SIZE(ahb1_predivs),
0239     },
0240 
0241     .common     = {
0242         .reg        = 0x054,
0243         .features   = CCU_FEATURE_VARIABLE_PREDIV,
0244         .hw.init    = CLK_HW_INIT_PARENTS("ahb1",
0245                               ahb1_parents,
0246                               &ccu_div_ops,
0247                               0),
0248     },
0249 };
0250 
0251 static struct clk_div_table apb1_div_table[] = {
0252     { .val = 0, .div = 2 },
0253     { .val = 1, .div = 2 },
0254     { .val = 2, .div = 4 },
0255     { .val = 3, .div = 8 },
0256     { /* Sentinel */ },
0257 };
0258 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0259                0x054, 8, 2, apb1_div_table, 0);
0260 
0261 static const char * const apb2_parents[] = { "osc32k", "osc24M",
0262                          "pll-periph0-2x",
0263                          "pll-periph0-2x" };
0264 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0265                  0, 5,  /* M */
0266                  16, 2, /* P */
0267                  24, 2, /* mux */
0268                  0);
0269 
0270 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
0271 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
0272     { .index = 1, .div = 2 },
0273 };
0274 static struct ccu_mux ahb2_clk = {
0275     .mux        = {
0276         .shift  = 0,
0277         .width  = 1,
0278         .fixed_predivs  = ahb2_fixed_predivs,
0279         .n_predivs  = ARRAY_SIZE(ahb2_fixed_predivs),
0280     },
0281 
0282     .common     = {
0283         .reg        = 0x05c,
0284         .features   = CCU_FEATURE_FIXED_PREDIV,
0285         .hw.init    = CLK_HW_INIT_PARENTS("ahb2",
0286                               ahb2_parents,
0287                               &ccu_mux_ops,
0288                               0),
0289     },
0290 };
0291 
0292 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
0293               0x060, BIT(1), 0);
0294 static SUNXI_CCU_GATE(bus_ce_clk,   "bus-ce",   "ahb1",
0295               0x060, BIT(5), 0);
0296 static SUNXI_CCU_GATE(bus_dma_clk,  "bus-dma",  "ahb1",
0297               0x060, BIT(6), 0);
0298 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0299               0x060, BIT(8), 0);
0300 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0301               0x060, BIT(9), 0);
0302 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0303               0x060, BIT(10), 0);
0304 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
0305               0x060, BIT(13), 0);
0306 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0307               0x060, BIT(14), 0);
0308 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
0309               0x060, BIT(17), 0);
0310 static SUNXI_CCU_GATE(bus_ts_clk,   "bus-ts",   "ahb1",
0311               0x060, BIT(18), 0);
0312 static SUNXI_CCU_GATE(bus_hstimer_clk,  "bus-hstimer",  "ahb1",
0313               0x060, BIT(19), 0);
0314 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0315               0x060, BIT(20), 0);
0316 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
0317               0x060, BIT(21), 0);
0318 static SUNXI_CCU_GATE(bus_otg_clk,  "bus-otg",  "ahb1",
0319               0x060, BIT(23), 0);
0320 static SUNXI_CCU_GATE(bus_ehci0_clk,    "bus-ehci0",    "ahb1",
0321               0x060, BIT(24), 0);
0322 static SUNXI_CCU_GATE(bus_ehci1_clk,    "bus-ehci1",    "ahb2",
0323               0x060, BIT(25), 0);
0324 static SUNXI_CCU_GATE(bus_ohci0_clk,    "bus-ohci0",    "ahb1",
0325               0x060, BIT(28), 0);
0326 static SUNXI_CCU_GATE(bus_ohci1_clk,    "bus-ohci1",    "ahb2",
0327               0x060, BIT(29), 0);
0328 
0329 static SUNXI_CCU_GATE(bus_ve_clk,   "bus-ve",   "ahb1",
0330               0x064, BIT(0), 0);
0331 static SUNXI_CCU_GATE(bus_tcon0_clk,    "bus-tcon0",    "ahb1",
0332               0x064, BIT(3), 0);
0333 static SUNXI_CCU_GATE(bus_tcon1_clk,    "bus-tcon1",    "ahb1",
0334               0x064, BIT(4), 0);
0335 static SUNXI_CCU_GATE(bus_deinterlace_clk,  "bus-deinterlace",  "ahb1",
0336               0x064, BIT(5), 0);
0337 static SUNXI_CCU_GATE(bus_csi_clk,  "bus-csi",  "ahb1",
0338               0x064, BIT(8), 0);
0339 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
0340               0x064, BIT(11), 0);
0341 static SUNXI_CCU_GATE(bus_de_clk,   "bus-de",   "ahb1",
0342               0x064, BIT(12), 0);
0343 static SUNXI_CCU_GATE(bus_gpu_clk,  "bus-gpu",  "ahb1",
0344               0x064, BIT(20), 0);
0345 static SUNXI_CCU_GATE(bus_msgbox_clk,   "bus-msgbox",   "ahb1",
0346               0x064, BIT(21), 0);
0347 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0348               0x064, BIT(22), 0);
0349 
0350 static SUNXI_CCU_GATE(bus_codec_clk,    "bus-codec",    "apb1",
0351               0x068, BIT(0), 0);
0352 static SUNXI_CCU_GATE(bus_spdif_clk,    "bus-spdif",    "apb1",
0353               0x068, BIT(1), 0);
0354 static SUNXI_CCU_GATE(bus_pio_clk,  "bus-pio",  "apb1",
0355               0x068, BIT(5), 0);
0356 static SUNXI_CCU_GATE(bus_ths_clk,  "bus-ths",  "apb1",
0357               0x068, BIT(8), 0);
0358 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0359               0x068, BIT(12), 0);
0360 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
0361               0x068, BIT(13), 0);
0362 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
0363               0x068, BIT(14), 0);
0364 
0365 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0366               0x06c, BIT(0), 0);
0367 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0368               0x06c, BIT(1), 0);
0369 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0370               0x06c, BIT(2), 0);
0371 static SUNXI_CCU_GATE(bus_scr_clk,  "bus-scr",  "apb2",
0372               0x06c, BIT(5), 0);
0373 static SUNXI_CCU_GATE(bus_uart0_clk,    "bus-uart0",    "apb2",
0374               0x06c, BIT(16), 0);
0375 static SUNXI_CCU_GATE(bus_uart1_clk,    "bus-uart1",    "apb2",
0376               0x06c, BIT(17), 0);
0377 static SUNXI_CCU_GATE(bus_uart2_clk,    "bus-uart2",    "apb2",
0378               0x06c, BIT(18), 0);
0379 static SUNXI_CCU_GATE(bus_uart3_clk,    "bus-uart3",    "apb2",
0380               0x06c, BIT(19), 0);
0381 static SUNXI_CCU_GATE(bus_uart4_clk,    "bus-uart4",    "apb2",
0382               0x06c, BIT(20), 0);
0383 
0384 static SUNXI_CCU_GATE(bus_dbg_clk,  "bus-dbg",  "ahb1",
0385               0x070, BIT(7), 0);
0386 
0387 static struct clk_div_table ths_div_table[] = {
0388     { .val = 0, .div = 1 },
0389     { .val = 1, .div = 2 },
0390     { .val = 2, .div = 4 },
0391     { .val = 3, .div = 6 },
0392     { /* Sentinel */ },
0393 };
0394 static const char * const ths_parents[] = { "osc24M" };
0395 static struct ccu_div ths_clk = {
0396     .enable = BIT(31),
0397     .div    = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
0398     .mux    = _SUNXI_CCU_MUX(24, 2),
0399     .common = {
0400         .reg        = 0x074,
0401         .hw.init    = CLK_HW_INIT_PARENTS("ths",
0402                               ths_parents,
0403                               &ccu_div_ops,
0404                               0),
0405     },
0406 };
0407 
0408 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
0409                              "pll-periph1" };
0410 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0411                   0, 4,     /* M */
0412                   16, 2,    /* P */
0413                   24, 2,    /* mux */
0414                   BIT(31),  /* gate */
0415                   0);
0416 
0417 /*
0418  * MMC clocks are the new timing mode (see A83T & H3) variety, but without
0419  * the mode switch. This means they have a 2x post divider between the clock
0420  * and the MMC module. This is not documented in the manual, but is taken
0421  * into consideration when setting the mmc module clocks in the BSP kernel.
0422  * Without it, MMC performance is degraded.
0423  *
0424  * We model it here to be consistent with other SoCs supporting this mode.
0425  * The alternative would be to add the 2x multiplier when setting the MMC
0426  * module clock in the MMC driver, just for the A64.
0427  */
0428 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
0429                             "pll-periph1-2x" };
0430 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",
0431                       mmc_default_parents, 0x088,
0432                       0, 4,     /* M */
0433                       16, 2,    /* P */
0434                       24, 2,    /* mux */
0435                       BIT(31),  /* gate */
0436                       2,        /* post-div */
0437                       0);
0438 
0439 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",
0440                       mmc_default_parents, 0x08c,
0441                       0, 4,     /* M */
0442                       16, 2,    /* P */
0443                       24, 2,    /* mux */
0444                       BIT(31),  /* gate */
0445                       2,        /* post-div */
0446                       0);
0447 
0448 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2",
0449                       mmc_default_parents, 0x090,
0450                       0, 4,     /* M */
0451                       16, 2,    /* P */
0452                       24, 2,    /* mux */
0453                       BIT(31),  /* gate */
0454                       2,        /* post-div */
0455                       0);
0456 
0457 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
0458 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
0459                   0, 4,     /* M */
0460                   16, 2,    /* P */
0461                   24, 4,    /* mux */
0462                   BIT(31),  /* gate */
0463                   0);
0464 
0465 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
0466                   0, 4,     /* M */
0467                   16, 2,    /* P */
0468                   24, 2,    /* mux */
0469                   BIT(31),  /* gate */
0470                   0);
0471 
0472 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0473                   0, 4,     /* M */
0474                   16, 2,    /* P */
0475                   24, 2,    /* mux */
0476                   BIT(31),  /* gate */
0477                   0);
0478 
0479 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0480                   0, 4,     /* M */
0481                   16, 2,    /* P */
0482                   24, 2,    /* mux */
0483                   BIT(31),  /* gate */
0484                   0);
0485 
0486 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
0487                         "pll-audio-2x", "pll-audio" };
0488 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
0489                    0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0490 
0491 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
0492                    0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0493 
0494 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
0495                    0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
0496 
0497 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
0498                  0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
0499 
0500 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0501               0x0cc, BIT(8), 0);
0502 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0503               0x0cc, BIT(9), 0);
0504 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
0505               0x0cc, BIT(10), 0);
0506 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
0507               0x0cc, BIT(11), 0);
0508 static SUNXI_CCU_GATE(usb_ohci0_clk,    "usb-ohci0",    "osc12M",
0509               0x0cc, BIT(16), 0);
0510 static SUNXI_CCU_GATE(usb_ohci1_clk,    "usb-ohci1",    "usb-ohci0",
0511               0x0cc, BIT(17), 0);
0512 
0513 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
0514 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
0515                 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
0516 
0517 static SUNXI_CCU_GATE(dram_ve_clk,  "dram-ve",  "dram",
0518               0x100, BIT(0), 0);
0519 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
0520               0x100, BIT(1), 0);
0521 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
0522               0x100, BIT(2), 0);
0523 static SUNXI_CCU_GATE(dram_ts_clk,  "dram-ts",  "dram",
0524               0x100, BIT(3), 0);
0525 
0526 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
0527 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0528                  0x104, 0, 4, 24, 3, BIT(31),
0529                  CLK_SET_RATE_PARENT);
0530 
0531 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
0532 static const u8 tcon0_table[] = { 0, 2, };
0533 static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
0534                      tcon0_table, 0x118, 24, 3, BIT(31),
0535                      CLK_SET_RATE_PARENT);
0536 
0537 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
0538 static const u8 tcon1_table[] = { 0, 2, };
0539 static struct ccu_div tcon1_clk = {
0540     .enable     = BIT(31),
0541     .div        = _SUNXI_CCU_DIV(0, 4),
0542     .mux        = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table),
0543     .common     = {
0544         .reg        = 0x11c,
0545         .hw.init    = CLK_HW_INIT_PARENTS("tcon1",
0546                               tcon1_parents,
0547                               &ccu_div_ops,
0548                               CLK_SET_RATE_PARENT),
0549     },
0550 };
0551 
0552 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
0553 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
0554                  0x124, 0, 4, 24, 3, BIT(31), 0);
0555 
0556 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
0557               0x130, BIT(31), 0);
0558 
0559 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
0560 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
0561                  0x134, 16, 4, 24, 3, BIT(31), 0);
0562 
0563 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
0564 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
0565                  0x134, 0, 5, 8, 3, BIT(15), 0);
0566 
0567 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0568                  0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
0569 
0570 static SUNXI_CCU_GATE(ac_dig_clk,   "ac-dig",   "pll-audio",
0571               0x140, BIT(31), CLK_SET_RATE_PARENT);
0572 
0573 static SUNXI_CCU_GATE(ac_dig_4x_clk,    "ac-dig-4x",    "pll-audio-4x",
0574               0x140, BIT(30), CLK_SET_RATE_PARENT);
0575 
0576 static SUNXI_CCU_GATE(avs_clk,      "avs",      "osc24M",
0577               0x144, BIT(31), 0);
0578 
0579 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
0580 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
0581                  0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
0582 
0583 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
0584               0x154, BIT(31), 0);
0585 
0586 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
0587                          "pll-ddr0", "pll-ddr1" };
0588 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0589                  0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
0590 
0591 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
0592 static const u8 dsi_dphy_table[] = { 0, 2, };
0593 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
0594                        dsi_dphy_parents, dsi_dphy_table,
0595                        0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
0596 
0597 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0598                  0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
0599 
0600 /* Fixed Factor clocks */
0601 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
0602 
0603 static const struct clk_hw *clk_parent_pll_audio[] = {
0604     &pll_audio_base_clk.common.hw
0605 };
0606 
0607 /* We hardcode the divider to 1 for now */
0608 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
0609                 clk_parent_pll_audio,
0610                 1, 1, CLK_SET_RATE_PARENT);
0611 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
0612                 clk_parent_pll_audio,
0613                 2, 1, CLK_SET_RATE_PARENT);
0614 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
0615                 clk_parent_pll_audio,
0616                 1, 1, CLK_SET_RATE_PARENT);
0617 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
0618                 clk_parent_pll_audio,
0619                 1, 2, CLK_SET_RATE_PARENT);
0620 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
0621                &pll_periph0_clk.common.hw,
0622                1, 2, 0);
0623 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
0624                &pll_periph1_clk.common.hw,
0625                1, 2, 0);
0626 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
0627                &pll_video0_clk.common.hw,
0628                1, 2, CLK_SET_RATE_PARENT);
0629 
0630 static struct ccu_common *sun50i_a64_ccu_clks[] = {
0631     &pll_cpux_clk.common,
0632     &pll_audio_base_clk.common,
0633     &pll_video0_clk.common,
0634     &pll_ve_clk.common,
0635     &pll_ddr0_clk.common,
0636     &pll_periph0_clk.common,
0637     &pll_periph1_clk.common,
0638     &pll_video1_clk.common,
0639     &pll_gpu_clk.common,
0640     &pll_mipi_clk.common,
0641     &pll_hsic_clk.common,
0642     &pll_de_clk.common,
0643     &pll_ddr1_clk.common,
0644     &cpux_clk.common,
0645     &axi_clk.common,
0646     &ahb1_clk.common,
0647     &apb1_clk.common,
0648     &apb2_clk.common,
0649     &ahb2_clk.common,
0650     &bus_mipi_dsi_clk.common,
0651     &bus_ce_clk.common,
0652     &bus_dma_clk.common,
0653     &bus_mmc0_clk.common,
0654     &bus_mmc1_clk.common,
0655     &bus_mmc2_clk.common,
0656     &bus_nand_clk.common,
0657     &bus_dram_clk.common,
0658     &bus_emac_clk.common,
0659     &bus_ts_clk.common,
0660     &bus_hstimer_clk.common,
0661     &bus_spi0_clk.common,
0662     &bus_spi1_clk.common,
0663     &bus_otg_clk.common,
0664     &bus_ehci0_clk.common,
0665     &bus_ehci1_clk.common,
0666     &bus_ohci0_clk.common,
0667     &bus_ohci1_clk.common,
0668     &bus_ve_clk.common,
0669     &bus_tcon0_clk.common,
0670     &bus_tcon1_clk.common,
0671     &bus_deinterlace_clk.common,
0672     &bus_csi_clk.common,
0673     &bus_hdmi_clk.common,
0674     &bus_de_clk.common,
0675     &bus_gpu_clk.common,
0676     &bus_msgbox_clk.common,
0677     &bus_spinlock_clk.common,
0678     &bus_codec_clk.common,
0679     &bus_spdif_clk.common,
0680     &bus_pio_clk.common,
0681     &bus_ths_clk.common,
0682     &bus_i2s0_clk.common,
0683     &bus_i2s1_clk.common,
0684     &bus_i2s2_clk.common,
0685     &bus_i2c0_clk.common,
0686     &bus_i2c1_clk.common,
0687     &bus_i2c2_clk.common,
0688     &bus_scr_clk.common,
0689     &bus_uart0_clk.common,
0690     &bus_uart1_clk.common,
0691     &bus_uart2_clk.common,
0692     &bus_uart3_clk.common,
0693     &bus_uart4_clk.common,
0694     &bus_dbg_clk.common,
0695     &ths_clk.common,
0696     &nand_clk.common,
0697     &mmc0_clk.common,
0698     &mmc1_clk.common,
0699     &mmc2_clk.common,
0700     &ts_clk.common,
0701     &ce_clk.common,
0702     &spi0_clk.common,
0703     &spi1_clk.common,
0704     &i2s0_clk.common,
0705     &i2s1_clk.common,
0706     &i2s2_clk.common,
0707     &spdif_clk.common,
0708     &usb_phy0_clk.common,
0709     &usb_phy1_clk.common,
0710     &usb_hsic_clk.common,
0711     &usb_hsic_12m_clk.common,
0712     &usb_ohci0_clk.common,
0713     &usb_ohci1_clk.common,
0714     &dram_clk.common,
0715     &dram_ve_clk.common,
0716     &dram_csi_clk.common,
0717     &dram_deinterlace_clk.common,
0718     &dram_ts_clk.common,
0719     &de_clk.common,
0720     &tcon0_clk.common,
0721     &tcon1_clk.common,
0722     &deinterlace_clk.common,
0723     &csi_misc_clk.common,
0724     &csi_sclk_clk.common,
0725     &csi_mclk_clk.common,
0726     &ve_clk.common,
0727     &ac_dig_clk.common,
0728     &ac_dig_4x_clk.common,
0729     &avs_clk.common,
0730     &hdmi_clk.common,
0731     &hdmi_ddc_clk.common,
0732     &mbus_clk.common,
0733     &dsi_dphy_clk.common,
0734     &gpu_clk.common,
0735 };
0736 
0737 static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
0738     .hws    = {
0739         [CLK_OSC_12M]       = &osc12M_clk.hw,
0740         [CLK_PLL_CPUX]      = &pll_cpux_clk.common.hw,
0741         [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
0742         [CLK_PLL_AUDIO]     = &pll_audio_clk.hw,
0743         [CLK_PLL_AUDIO_2X]  = &pll_audio_2x_clk.hw,
0744         [CLK_PLL_AUDIO_4X]  = &pll_audio_4x_clk.hw,
0745         [CLK_PLL_AUDIO_8X]  = &pll_audio_8x_clk.hw,
0746         [CLK_PLL_VIDEO0]    = &pll_video0_clk.common.hw,
0747         [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
0748         [CLK_PLL_VE]        = &pll_ve_clk.common.hw,
0749         [CLK_PLL_DDR0]      = &pll_ddr0_clk.common.hw,
0750         [CLK_PLL_PERIPH0]   = &pll_periph0_clk.common.hw,
0751         [CLK_PLL_PERIPH0_2X]    = &pll_periph0_2x_clk.hw,
0752         [CLK_PLL_PERIPH1]   = &pll_periph1_clk.common.hw,
0753         [CLK_PLL_PERIPH1_2X]    = &pll_periph1_2x_clk.hw,
0754         [CLK_PLL_VIDEO1]    = &pll_video1_clk.common.hw,
0755         [CLK_PLL_GPU]       = &pll_gpu_clk.common.hw,
0756         [CLK_PLL_MIPI]      = &pll_mipi_clk.common.hw,
0757         [CLK_PLL_HSIC]      = &pll_hsic_clk.common.hw,
0758         [CLK_PLL_DE]        = &pll_de_clk.common.hw,
0759         [CLK_PLL_DDR1]      = &pll_ddr1_clk.common.hw,
0760         [CLK_CPUX]      = &cpux_clk.common.hw,
0761         [CLK_AXI]       = &axi_clk.common.hw,
0762         [CLK_AHB1]      = &ahb1_clk.common.hw,
0763         [CLK_APB1]      = &apb1_clk.common.hw,
0764         [CLK_APB2]      = &apb2_clk.common.hw,
0765         [CLK_AHB2]      = &ahb2_clk.common.hw,
0766         [CLK_BUS_MIPI_DSI]  = &bus_mipi_dsi_clk.common.hw,
0767         [CLK_BUS_CE]        = &bus_ce_clk.common.hw,
0768         [CLK_BUS_DMA]       = &bus_dma_clk.common.hw,
0769         [CLK_BUS_MMC0]      = &bus_mmc0_clk.common.hw,
0770         [CLK_BUS_MMC1]      = &bus_mmc1_clk.common.hw,
0771         [CLK_BUS_MMC2]      = &bus_mmc2_clk.common.hw,
0772         [CLK_BUS_NAND]      = &bus_nand_clk.common.hw,
0773         [CLK_BUS_DRAM]      = &bus_dram_clk.common.hw,
0774         [CLK_BUS_EMAC]      = &bus_emac_clk.common.hw,
0775         [CLK_BUS_TS]        = &bus_ts_clk.common.hw,
0776         [CLK_BUS_HSTIMER]   = &bus_hstimer_clk.common.hw,
0777         [CLK_BUS_SPI0]      = &bus_spi0_clk.common.hw,
0778         [CLK_BUS_SPI1]      = &bus_spi1_clk.common.hw,
0779         [CLK_BUS_OTG]       = &bus_otg_clk.common.hw,
0780         [CLK_BUS_EHCI0]     = &bus_ehci0_clk.common.hw,
0781         [CLK_BUS_EHCI1]     = &bus_ehci1_clk.common.hw,
0782         [CLK_BUS_OHCI0]     = &bus_ohci0_clk.common.hw,
0783         [CLK_BUS_OHCI1]     = &bus_ohci1_clk.common.hw,
0784         [CLK_BUS_VE]        = &bus_ve_clk.common.hw,
0785         [CLK_BUS_TCON0]     = &bus_tcon0_clk.common.hw,
0786         [CLK_BUS_TCON1]     = &bus_tcon1_clk.common.hw,
0787         [CLK_BUS_DEINTERLACE]   = &bus_deinterlace_clk.common.hw,
0788         [CLK_BUS_CSI]       = &bus_csi_clk.common.hw,
0789         [CLK_BUS_HDMI]      = &bus_hdmi_clk.common.hw,
0790         [CLK_BUS_DE]        = &bus_de_clk.common.hw,
0791         [CLK_BUS_GPU]       = &bus_gpu_clk.common.hw,
0792         [CLK_BUS_MSGBOX]    = &bus_msgbox_clk.common.hw,
0793         [CLK_BUS_SPINLOCK]  = &bus_spinlock_clk.common.hw,
0794         [CLK_BUS_CODEC]     = &bus_codec_clk.common.hw,
0795         [CLK_BUS_SPDIF]     = &bus_spdif_clk.common.hw,
0796         [CLK_BUS_PIO]       = &bus_pio_clk.common.hw,
0797         [CLK_BUS_THS]       = &bus_ths_clk.common.hw,
0798         [CLK_BUS_I2S0]      = &bus_i2s0_clk.common.hw,
0799         [CLK_BUS_I2S1]      = &bus_i2s1_clk.common.hw,
0800         [CLK_BUS_I2S2]      = &bus_i2s2_clk.common.hw,
0801         [CLK_BUS_I2C0]      = &bus_i2c0_clk.common.hw,
0802         [CLK_BUS_I2C1]      = &bus_i2c1_clk.common.hw,
0803         [CLK_BUS_I2C2]      = &bus_i2c2_clk.common.hw,
0804         [CLK_BUS_UART0]     = &bus_uart0_clk.common.hw,
0805         [CLK_BUS_UART1]     = &bus_uart1_clk.common.hw,
0806         [CLK_BUS_UART2]     = &bus_uart2_clk.common.hw,
0807         [CLK_BUS_UART3]     = &bus_uart3_clk.common.hw,
0808         [CLK_BUS_UART4]     = &bus_uart4_clk.common.hw,
0809         [CLK_BUS_SCR]       = &bus_scr_clk.common.hw,
0810         [CLK_BUS_DBG]       = &bus_dbg_clk.common.hw,
0811         [CLK_THS]       = &ths_clk.common.hw,
0812         [CLK_NAND]      = &nand_clk.common.hw,
0813         [CLK_MMC0]      = &mmc0_clk.common.hw,
0814         [CLK_MMC1]      = &mmc1_clk.common.hw,
0815         [CLK_MMC2]      = &mmc2_clk.common.hw,
0816         [CLK_TS]        = &ts_clk.common.hw,
0817         [CLK_CE]        = &ce_clk.common.hw,
0818         [CLK_SPI0]      = &spi0_clk.common.hw,
0819         [CLK_SPI1]      = &spi1_clk.common.hw,
0820         [CLK_I2S0]      = &i2s0_clk.common.hw,
0821         [CLK_I2S1]      = &i2s1_clk.common.hw,
0822         [CLK_I2S2]      = &i2s2_clk.common.hw,
0823         [CLK_SPDIF]     = &spdif_clk.common.hw,
0824         [CLK_USB_PHY0]      = &usb_phy0_clk.common.hw,
0825         [CLK_USB_PHY1]      = &usb_phy1_clk.common.hw,
0826         [CLK_USB_HSIC]      = &usb_hsic_clk.common.hw,
0827         [CLK_USB_HSIC_12M]  = &usb_hsic_12m_clk.common.hw,
0828         [CLK_USB_OHCI0]     = &usb_ohci0_clk.common.hw,
0829         [CLK_USB_OHCI1]     = &usb_ohci1_clk.common.hw,
0830         [CLK_DRAM]      = &dram_clk.common.hw,
0831         [CLK_DRAM_VE]       = &dram_ve_clk.common.hw,
0832         [CLK_DRAM_CSI]      = &dram_csi_clk.common.hw,
0833         [CLK_DRAM_DEINTERLACE]  = &dram_deinterlace_clk.common.hw,
0834         [CLK_DRAM_TS]       = &dram_ts_clk.common.hw,
0835         [CLK_DE]        = &de_clk.common.hw,
0836         [CLK_TCON0]     = &tcon0_clk.common.hw,
0837         [CLK_TCON1]     = &tcon1_clk.common.hw,
0838         [CLK_DEINTERLACE]   = &deinterlace_clk.common.hw,
0839         [CLK_CSI_MISC]      = &csi_misc_clk.common.hw,
0840         [CLK_CSI_SCLK]      = &csi_sclk_clk.common.hw,
0841         [CLK_CSI_MCLK]      = &csi_mclk_clk.common.hw,
0842         [CLK_VE]        = &ve_clk.common.hw,
0843         [CLK_AC_DIG]        = &ac_dig_clk.common.hw,
0844         [CLK_AC_DIG_4X]     = &ac_dig_4x_clk.common.hw,
0845         [CLK_AVS]       = &avs_clk.common.hw,
0846         [CLK_HDMI]      = &hdmi_clk.common.hw,
0847         [CLK_HDMI_DDC]      = &hdmi_ddc_clk.common.hw,
0848         [CLK_MBUS]      = &mbus_clk.common.hw,
0849         [CLK_DSI_DPHY]      = &dsi_dphy_clk.common.hw,
0850         [CLK_GPU]       = &gpu_clk.common.hw,
0851     },
0852     .num    = CLK_NUMBER,
0853 };
0854 
0855 static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
0856     [RST_USB_PHY0]      =  { 0x0cc, BIT(0) },
0857     [RST_USB_PHY1]      =  { 0x0cc, BIT(1) },
0858     [RST_USB_HSIC]      =  { 0x0cc, BIT(2) },
0859 
0860     [RST_DRAM]      =  { 0x0f4, BIT(31) },
0861     [RST_MBUS]      =  { 0x0fc, BIT(31) },
0862 
0863     [RST_BUS_MIPI_DSI]  =  { 0x2c0, BIT(1) },
0864     [RST_BUS_CE]        =  { 0x2c0, BIT(5) },
0865     [RST_BUS_DMA]       =  { 0x2c0, BIT(6) },
0866     [RST_BUS_MMC0]      =  { 0x2c0, BIT(8) },
0867     [RST_BUS_MMC1]      =  { 0x2c0, BIT(9) },
0868     [RST_BUS_MMC2]      =  { 0x2c0, BIT(10) },
0869     [RST_BUS_NAND]      =  { 0x2c0, BIT(13) },
0870     [RST_BUS_DRAM]      =  { 0x2c0, BIT(14) },
0871     [RST_BUS_EMAC]      =  { 0x2c0, BIT(17) },
0872     [RST_BUS_TS]        =  { 0x2c0, BIT(18) },
0873     [RST_BUS_HSTIMER]   =  { 0x2c0, BIT(19) },
0874     [RST_BUS_SPI0]      =  { 0x2c0, BIT(20) },
0875     [RST_BUS_SPI1]      =  { 0x2c0, BIT(21) },
0876     [RST_BUS_OTG]       =  { 0x2c0, BIT(23) },
0877     [RST_BUS_EHCI0]     =  { 0x2c0, BIT(24) },
0878     [RST_BUS_EHCI1]     =  { 0x2c0, BIT(25) },
0879     [RST_BUS_OHCI0]     =  { 0x2c0, BIT(28) },
0880     [RST_BUS_OHCI1]     =  { 0x2c0, BIT(29) },
0881 
0882     [RST_BUS_VE]        =  { 0x2c4, BIT(0) },
0883     [RST_BUS_TCON0]     =  { 0x2c4, BIT(3) },
0884     [RST_BUS_TCON1]     =  { 0x2c4, BIT(4) },
0885     [RST_BUS_DEINTERLACE]   =  { 0x2c4, BIT(5) },
0886     [RST_BUS_CSI]       =  { 0x2c4, BIT(8) },
0887     [RST_BUS_HDMI0]     =  { 0x2c4, BIT(10) },
0888     [RST_BUS_HDMI1]     =  { 0x2c4, BIT(11) },
0889     [RST_BUS_DE]        =  { 0x2c4, BIT(12) },
0890     [RST_BUS_GPU]       =  { 0x2c4, BIT(20) },
0891     [RST_BUS_MSGBOX]    =  { 0x2c4, BIT(21) },
0892     [RST_BUS_SPINLOCK]  =  { 0x2c4, BIT(22) },
0893     [RST_BUS_DBG]       =  { 0x2c4, BIT(31) },
0894 
0895     [RST_BUS_LVDS]      =  { 0x2c8, BIT(0) },
0896 
0897     [RST_BUS_CODEC]     =  { 0x2d0, BIT(0) },
0898     [RST_BUS_SPDIF]     =  { 0x2d0, BIT(1) },
0899     [RST_BUS_THS]       =  { 0x2d0, BIT(8) },
0900     [RST_BUS_I2S0]      =  { 0x2d0, BIT(12) },
0901     [RST_BUS_I2S1]      =  { 0x2d0, BIT(13) },
0902     [RST_BUS_I2S2]      =  { 0x2d0, BIT(14) },
0903 
0904     [RST_BUS_I2C0]      =  { 0x2d8, BIT(0) },
0905     [RST_BUS_I2C1]      =  { 0x2d8, BIT(1) },
0906     [RST_BUS_I2C2]      =  { 0x2d8, BIT(2) },
0907     [RST_BUS_SCR]       =  { 0x2d8, BIT(5) },
0908     [RST_BUS_UART0]     =  { 0x2d8, BIT(16) },
0909     [RST_BUS_UART1]     =  { 0x2d8, BIT(17) },
0910     [RST_BUS_UART2]     =  { 0x2d8, BIT(18) },
0911     [RST_BUS_UART3]     =  { 0x2d8, BIT(19) },
0912     [RST_BUS_UART4]     =  { 0x2d8, BIT(20) },
0913 };
0914 
0915 static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
0916     .ccu_clks   = sun50i_a64_ccu_clks,
0917     .num_ccu_clks   = ARRAY_SIZE(sun50i_a64_ccu_clks),
0918 
0919     .hw_clks    = &sun50i_a64_hw_clks,
0920 
0921     .resets     = sun50i_a64_ccu_resets,
0922     .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
0923 };
0924 
0925 static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
0926     .common = &pll_cpux_clk.common,
0927     /* copy from pll_cpux_clk */
0928     .enable = BIT(31),
0929     .lock   = BIT(28),
0930 };
0931 
0932 static struct ccu_mux_nb sun50i_a64_cpu_nb = {
0933     .common     = &cpux_clk.common,
0934     .cm     = &cpux_clk.mux,
0935     .delay_us   = 1, /* > 8 clock cycles at 24 MHz */
0936     .bypass_index   = 1, /* index of 24 MHz oscillator */
0937 };
0938 
0939 static int sun50i_a64_ccu_probe(struct platform_device *pdev)
0940 {
0941     void __iomem *reg;
0942     u32 val;
0943     int ret;
0944 
0945     reg = devm_platform_ioremap_resource(pdev, 0);
0946     if (IS_ERR(reg))
0947         return PTR_ERR(reg);
0948 
0949     /* Force the PLL-Audio-1x divider to 1 */
0950     val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
0951     val &= ~GENMASK(19, 16);
0952     writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
0953 
0954     writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
0955 
0956     ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
0957     if (ret)
0958         return ret;
0959 
0960     /* Gate then ungate PLL CPU after any rate changes */
0961     ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);
0962 
0963     /* Reparent CPU during PLL CPU rate changes */
0964     ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
0965                   &sun50i_a64_cpu_nb);
0966 
0967     return 0;
0968 }
0969 
0970 static const struct of_device_id sun50i_a64_ccu_ids[] = {
0971     { .compatible = "allwinner,sun50i-a64-ccu" },
0972     { }
0973 };
0974 
0975 static struct platform_driver sun50i_a64_ccu_driver = {
0976     .probe  = sun50i_a64_ccu_probe,
0977     .driver = {
0978         .name   = "sun50i-a64-ccu",
0979         .suppress_bind_attrs = true,
0980         .of_match_table = sun50i_a64_ccu_ids,
0981     },
0982 };
0983 module_platform_driver(sun50i_a64_ccu_driver);
0984 
0985 MODULE_IMPORT_NS(SUNXI_CCU);
0986 MODULE_LICENSE("GPL");
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