clk/sunxi-ng/ccu-sun50i-a100.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
0004  */
0005
0006 #ifndef _CCU_SUN50I_A100_H_
0007 #define _CCU_SUN50I_A100_H_
0008
0009 #include <dt-bindings/clock/sun50i-a100-ccu.h>
0010 #include <dt-bindings/reset/sun50i-a100-ccu.h>
0011
0012 #define CLK_OSC12M      0
0013 #define CLK_PLL_CPUX        1
0014 #define CLK_PLL_DDR0        2
0015
0016 /* PLL_PERIPH0 exported for PRCM */
0017
0018 #define CLK_PLL_PERIPH0_2X  4
0019 #define CLK_PLL_PERIPH1     5
0020 #define CLK_PLL_PERIPH1_2X  6
0021 #define CLK_PLL_GPU     7
0022 #define CLK_PLL_VIDEO0      8
0023 #define CLK_PLL_VIDEO0_2X   9
0024 #define CLK_PLL_VIDEO0_4X   10
0025 #define CLK_PLL_VIDEO1      11
0026 #define CLK_PLL_VIDEO1_2X   12
0027 #define CLK_PLL_VIDEO1_4X   13
0028 #define CLK_PLL_VIDEO2      14
0029 #define CLK_PLL_VIDEO2_2X   15
0030 #define CLK_PLL_VIDEO2_4X   16
0031 #define CLK_PLL_VIDEO3      17
0032 #define CLK_PLL_VIDEO3_2X   18
0033 #define CLK_PLL_VIDEO3_4X   19
0034 #define CLK_PLL_VE      20
0035 #define CLK_PLL_COM     21
0036 #define CLK_PLL_COM_AUDIO   22
0037 #define CLK_PLL_AUDIO       23
0038
0039 /* CPUX clock exported for DVFS */
0040
0041 #define CLK_AXI         25
0042 #define CLK_CPUX_APB        26
0043 #define CLK_PSI_AHB1_AHB2   27
0044 #define CLK_AHB3        28
0045
0046 /* APB1 clock exported for PIO */
0047
0048 #define CLK_APB2        30
0049
0050 /* All module clocks and bus gates are exported except DRAM */
0051
0052 #define CLK_BUS_DRAM        58
0053
0054 #define CLK_NUMBER      (CLK_CSI_ISP + 1)
0055
0056 #endif /* _CCU_SUN50I_A100_H_ */