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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
0004  */
0005 
0006 #include <linux/clk-provider.h>
0007 #include <linux/io.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 
0011 #include "ccu_common.h"
0012 #include "ccu_reset.h"
0013 
0014 #include "ccu_div.h"
0015 #include "ccu_gate.h"
0016 #include "ccu_mp.h"
0017 #include "ccu_mult.h"
0018 #include "ccu_nk.h"
0019 #include "ccu_nkm.h"
0020 #include "ccu_nkmp.h"
0021 #include "ccu_nm.h"
0022 
0023 #include "ccu-sun50i-a100.h"
0024 
0025 #define SUN50I_A100_PLL_SDM_ENABLE      BIT(24)
0026 #define SUN50I_A100_PLL_OUTPUT_ENABLE       BIT(27)
0027 #define SUN50I_A100_PLL_LOCK            BIT(28)
0028 #define SUN50I_A100_PLL_LOCK_ENABLE     BIT(29)
0029 #define SUN50I_A100_PLL_ENABLE          BIT(31)
0030 
0031 #define SUN50I_A100_PLL_PERIPH1_PATTERN0    0xd1303333
0032 
0033 /*
0034  * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
0035  * P should only be used for output frequencies lower than 288 MHz.
0036  *
0037  * For now we can just model it as a multiplier clock, and force P to /1.
0038  *
0039  * The M factor is present in the register's description, but not in the
0040  * frequency formula, and it's documented as "M is only used for backdoor
0041  * testing", so it's not modelled and then force to 0.
0042  */
0043 #define SUN50I_A100_PLL_CPUX_REG        0x000
0044 static struct ccu_mult pll_cpux_clk = {
0045     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0046     .lock       = SUN50I_A100_PLL_LOCK,
0047     .mult       = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0048     .common     = {
0049         .reg        = 0x000,
0050         .hw.init    = CLK_HW_INIT("pll-cpux", "dcxo24M",
0051                           &ccu_mult_ops,
0052                           CLK_SET_RATE_UNGATE),
0053     },
0054 };
0055 
0056 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
0057 #define SUN50I_A100_PLL_DDR0_REG        0x010
0058 static struct ccu_nkmp pll_ddr0_clk = {
0059     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0060     .lock       = SUN50I_A100_PLL_LOCK,
0061     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0062     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0063     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0064     .common     = {
0065         .reg        = 0x010,
0066         .hw.init    = CLK_HW_INIT("pll-ddr0", "dcxo24M",
0067                           &ccu_nkmp_ops,
0068                           CLK_SET_RATE_UNGATE |
0069                           CLK_IS_CRITICAL),
0070     },
0071 };
0072 
0073 #define SUN50I_A100_PLL_PERIPH0_REG 0x020
0074 static struct ccu_nkmp pll_periph0_clk = {
0075     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0076     .lock       = SUN50I_A100_PLL_LOCK,
0077     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0078     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0079     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0080     .fixed_post_div = 2,
0081     .common     = {
0082         .reg        = 0x020,
0083         .features   = CCU_FEATURE_FIXED_POSTDIV,
0084         .hw.init    = CLK_HW_INIT("pll-periph0", "dcxo24M",
0085                           &ccu_nkmp_ops,
0086                           CLK_SET_RATE_UNGATE),
0087     },
0088 };
0089 
0090 #define SUN50I_A100_PLL_PERIPH1_REG 0x028
0091 static struct ccu_nkmp pll_periph1_clk = {
0092     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0093     .lock       = SUN50I_A100_PLL_LOCK,
0094     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0095     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0096     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0097     .fixed_post_div = 2,
0098     .common     = {
0099         .reg        = 0x028,
0100         .features   = CCU_FEATURE_FIXED_POSTDIV,
0101         .hw.init    = CLK_HW_INIT("pll-periph1", "dcxo24M",
0102                           &ccu_nkmp_ops,
0103                           CLK_SET_RATE_UNGATE),
0104     },
0105 };
0106 #define SUN50I_A100_PLL_PERIPH1_PATTERN0_REG    0x128
0107 
0108 #define SUN50I_A100_PLL_GPU_REG     0x030
0109 static struct ccu_nkmp pll_gpu_clk = {
0110     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0111     .lock       = SUN50I_A100_PLL_LOCK,
0112     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0113     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0114     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0115     .common     = {
0116         .reg        = 0x030,
0117         .hw.init    = CLK_HW_INIT("pll-gpu", "dcxo24M",
0118                           &ccu_nkmp_ops,
0119                           CLK_SET_RATE_UNGATE),
0120     },
0121 };
0122 
0123 /*
0124  * For Video PLLs, the output divider is described as "used for testing"
0125  * in the user manual. So it's not modelled and forced to 0.
0126  */
0127 #define SUN50I_A100_PLL_VIDEO0_REG  0x040
0128 static struct ccu_nm pll_video0_clk = {
0129     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0130     .lock       = SUN50I_A100_PLL_LOCK,
0131     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0132     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0133     .fixed_post_div = 4,
0134     .common     = {
0135         .reg        = 0x040,
0136         .features   = CCU_FEATURE_FIXED_POSTDIV,
0137         .hw.init    = CLK_HW_INIT("pll-video0", "dcxo24M",
0138                           &ccu_nm_ops,
0139                           CLK_SET_RATE_UNGATE),
0140     },
0141 };
0142 
0143 #define SUN50I_A100_PLL_VIDEO1_REG  0x048
0144 static struct ccu_nm pll_video1_clk = {
0145     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0146     .lock       = SUN50I_A100_PLL_LOCK,
0147     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0148     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0149     .fixed_post_div = 4,
0150     .common     = {
0151         .reg        = 0x048,
0152         .features   = CCU_FEATURE_FIXED_POSTDIV,
0153         .hw.init    = CLK_HW_INIT("pll-video1", "dcxo24M",
0154                           &ccu_nm_ops,
0155                           CLK_SET_RATE_UNGATE),
0156     },
0157 };
0158 
0159 #define SUN50I_A100_PLL_VIDEO2_REG  0x050
0160 static struct ccu_nm pll_video2_clk = {
0161     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0162     .lock       = SUN50I_A100_PLL_LOCK,
0163     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0164     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0165     .fixed_post_div = 4,
0166     .common     = {
0167         .reg        = 0x050,
0168         .features   = CCU_FEATURE_FIXED_POSTDIV,
0169         .hw.init    = CLK_HW_INIT("pll-video2", "dcxo24M",
0170                           &ccu_nm_ops,
0171                           CLK_SET_RATE_UNGATE),
0172     },
0173 };
0174 
0175 #define SUN50I_A100_PLL_VE_REG      0x058
0176 static struct ccu_nkmp pll_ve_clk = {
0177     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0178     .lock       = SUN50I_A100_PLL_LOCK,
0179     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0180     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0181     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0182     .common     = {
0183         .reg        = 0x058,
0184         .hw.init    = CLK_HW_INIT("pll-ve", "dcxo24M",
0185                           &ccu_nkmp_ops,
0186                           CLK_SET_RATE_UNGATE),
0187     },
0188 };
0189 
0190 /*
0191  * The COM PLL has m0 dividers in addition to the usual N, M
0192  * factors. Since we only need 1 frequencies from this PLL: 45.1584 MHz,
0193  * ignore it for now.
0194  */
0195 #define SUN50I_A100_PLL_COM_REG     0x060
0196 static struct ccu_sdm_setting pll_com_sdm_table[] = {
0197     { .rate = 451584000, .pattern = 0xc0014396, .m = 2, .n = 37 },
0198 };
0199 
0200 static struct ccu_nm pll_com_clk = {
0201     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0202     .lock       = SUN50I_A100_PLL_LOCK,
0203     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0204     .m      = _SUNXI_CCU_DIV(0, 1),
0205     .sdm        = _SUNXI_CCU_SDM(pll_com_sdm_table, BIT(24),
0206                      0x160, BIT(31)),
0207     .common     = {
0208         .reg        = 0x060,
0209         .features   = CCU_FEATURE_SIGMA_DELTA_MOD,
0210         .hw.init    = CLK_HW_INIT("pll-com", "dcxo24M",
0211                           &ccu_nm_ops,
0212                           CLK_SET_RATE_UNGATE),
0213     },
0214 };
0215 
0216 #define SUN50I_A100_PLL_VIDEO3_REG  0x068
0217 static struct ccu_nm pll_video3_clk = {
0218     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0219     .lock       = SUN50I_A100_PLL_LOCK,
0220     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0221     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0222     .fixed_post_div = 4,
0223     .common     = {
0224         .reg        = 0x068,
0225         .features   = CCU_FEATURE_FIXED_POSTDIV,
0226         .hw.init    = CLK_HW_INIT("pll-video3", "dcxo24M",
0227                           &ccu_nm_ops,
0228                           CLK_SET_RATE_UNGATE),
0229     },
0230 };
0231 
0232 /*
0233  * The Audio PLL has m0, m1 dividers in addition to the usual N, M
0234  * factors. Since we only need 4 frequencies from this PLL: 22.5792 MHz,
0235  * 24.576 MHz, 90.3168MHz and 98.304MHz ignore them for now.
0236  * Enforce the default for them, which is m0 = 1, m1 = 0.
0237  */
0238 #define SUN50I_A100_PLL_AUDIO_REG       0x078
0239 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
0240     { .rate = 45158400, .pattern = 0xc001bcd3, .m = 18, .n = 33 },
0241     { .rate = 49152000, .pattern = 0xc001eb85, .m = 20, .n = 40 },
0242     { .rate = 180633600, .pattern = 0xc001288d, .m = 3, .n = 22 },
0243     { .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
0244 };
0245 
0246 static struct ccu_nm pll_audio_clk = {
0247     .enable     = SUN50I_A100_PLL_OUTPUT_ENABLE,
0248     .lock       = SUN50I_A100_PLL_LOCK,
0249     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0250     .m      = _SUNXI_CCU_DIV(16, 6),
0251     .fixed_post_div = 2,
0252     .sdm        = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
0253                      0x178, BIT(31)),
0254     .common     = {
0255         .reg        = 0x078,
0256         .features   = CCU_FEATURE_FIXED_POSTDIV |
0257                   CCU_FEATURE_SIGMA_DELTA_MOD,
0258         .hw.init    = CLK_HW_INIT("pll-audio", "dcxo24M",
0259                           &ccu_nm_ops,
0260                           CLK_SET_RATE_UNGATE),
0261     },
0262 };
0263 
0264 static const char * const cpux_parents[] = { "dcxo24M", "osc32k",
0265                          "iosc", "pll-cpux",
0266                           "pll-periph0" };
0267 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0268              0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
0269 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
0270 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
0271 
0272 static const char * const psi_ahb1_ahb2_parents[] = { "dcxo24M", "osc32k",
0273                               "iosc", "pll-periph0",
0274                               "pll-periph0-2x" };
0275 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
0276                  psi_ahb1_ahb2_parents, 0x510,
0277                  0, 2,  /* M */
0278                  8, 2,  /* P */
0279                  24, 3, /* mux */
0280                  0);
0281 
0282 static const char * const ahb3_apb1_apb2_parents[] = { "dcxo24M", "osc32k",
0283                                "psi-ahb1-ahb2",
0284                                "pll-periph0",
0285                                "pll-periph0-2x" };
0286 static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
0287                  0, 2,  /* M */
0288                  8, 2,  /* P */
0289                  24, 3, /* mux */
0290                  0);
0291 
0292 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
0293                  0, 2,  /* M */
0294                  8, 2,  /* P */
0295                  24, 3, /* mux */
0296                  0);
0297 
0298 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
0299                  0, 2,  /* M */
0300                  8, 2,  /* P */
0301                  24, 3, /* mux */
0302                  0);
0303 
0304 static const char * const mbus_parents[] = { "dcxo24M", "pll-ddr0",
0305                          "pll-periph0",
0306                          "pll-periph0-2x" };
0307 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540,
0308                  0, 3,      /* M */
0309                  24, 2,     /* mux */
0310                  BIT(31),   /* gate */
0311                  CLK_IS_CRITICAL);
0312 
0313 static const char * const de_parents[] = { "pll-com", "pll-periph0-2x" };
0314 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de0", de_parents, 0x600,
0315                  0, 4,      /* M */
0316                  24, 1,     /* mux */
0317                  BIT(31),   /* gate */
0318                  CLK_SET_RATE_PARENT);
0319 
0320 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
0321               0x60c, BIT(0), 0);
0322 
0323 static const char * const g2d_parents[] = { "pll-com", "pll-periph0-2x",
0324                          "pll-video0-2x", "pll-video1-2x",
0325                          "pll-video2-2x"};
0326 static SUNXI_CCU_M_WITH_MUX_GATE(g2d_clk, "g2d",
0327                  g2d_parents,
0328                  0x630,
0329                  0, 4,      /* M */
0330                  24, 3,     /* mux */
0331                  BIT(31),   /* gate */
0332                  0);
0333 
0334 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
0335               0x63c, BIT(0), 0);
0336 
0337 static const char * const gpu_parents[] = { "pll-gpu" };
0338 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
0339                        0, 2,    /* M */
0340                        24, 1,   /* mux */
0341                        BIT(31), /* gate */
0342                        0);
0343 
0344 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
0345               0x67c, BIT(0), 0);
0346 
0347 static const char * const ce_parents[] = { "dcxo24M", "pll-periph0-2x" };
0348 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
0349                   0, 4,     /* M */
0350                   8, 2,     /* P */
0351                   24, 1,    /* mux */
0352                   BIT(31),  /* gate */
0353                   0);
0354 
0355 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
0356               0x68c, BIT(0), 0);
0357 
0358 static const char * const ve_parents[] = { "pll-ve" };
0359 static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
0360                  0, 3,      /* M */
0361                  24, 1,     /* mux */
0362                  BIT(31),   /* gate */
0363                  CLK_SET_RATE_PARENT);
0364 
0365 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
0366               0x69c, BIT(0), 0);
0367 
0368 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
0369               0x70c, BIT(0), 0);
0370 
0371 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
0372               0x71c, BIT(0), 0);
0373 
0374 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
0375               0x72c, BIT(0), 0);
0376 
0377 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
0378               0x73c, BIT(0), 0);
0379 
0380 static SUNXI_CCU_GATE(avs_clk, "avs", "dcxo24M", 0x740, BIT(31), 0);
0381 
0382 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
0383               0x78c, BIT(0), 0);
0384 
0385 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
0386               0x79c, BIT(0), 0);
0387 
0388 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
0389 
0390 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
0391 
0392 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
0393               0x804, BIT(0), 0);
0394 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
0395               0x804, BIT(1), 0);
0396 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
0397               0x804, BIT(2), 0);
0398 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
0399               0x804, BIT(5), 0);
0400 static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
0401               0x804, BIT(8), 0);
0402 static SUNXI_CCU_GATE(mbus_isp_clk, "mbus-isp", "mbus",
0403               0x804, BIT(9), 0);
0404 static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus",
0405               0x804, BIT(10), 0);
0406 
0407 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
0408               0x80c, BIT(0), CLK_IS_CRITICAL);
0409 
0410 static const char * const nand_spi_parents[] = { "dcxo24M",
0411                          "pll-periph0",
0412                          "pll-periph1",
0413                          "pll-periph0-2x",
0414                          "pll-periph1-2x" };
0415 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810,
0416                   0, 4,     /* M */
0417                   8, 2,     /* P */
0418                   24, 3,    /* mux */
0419                   BIT(31),  /* gate */
0420                   0);
0421 
0422 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814,
0423                   0, 4,     /* M */
0424                   8, 2,     /* P */
0425                   24, 3,    /* mux */
0426                   BIT(31),  /* gate */
0427                   0);
0428 
0429 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
0430 
0431 static const char * const mmc_parents[] = { "dcxo24M", "pll-periph0-2x",
0432                         "pll-periph1-2x" };
0433 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
0434                       0, 4,     /* M */
0435                       8, 2,     /* P */
0436                       24, 2,    /* mux */
0437                       BIT(31),  /* gate */
0438                       2,        /* post-div */
0439                       CLK_SET_RATE_NO_REPARENT);
0440 
0441 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
0442                       0, 4,     /* M */
0443                       8, 2,     /* P */
0444                       24, 2,    /* mux */
0445                       BIT(31),  /* gate */
0446                       2,        /* post-div */
0447                       CLK_SET_RATE_NO_REPARENT);
0448 
0449 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
0450                       0, 4,     /* M */
0451                       8, 2,     /* P */
0452                       24, 2,    /* mux */
0453                       BIT(31),  /* gate */
0454                       2,        /* post-div */
0455                       CLK_SET_RATE_NO_REPARENT);
0456 
0457 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
0458 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
0459 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
0460 
0461 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
0462 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
0463 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
0464 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
0465 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
0466 
0467 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
0468 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
0469 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
0470 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
0471 
0472 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940,
0473                   0, 4,     /* M */
0474                   8, 2,     /* P */
0475                   24, 3,    /* mux */
0476                   BIT(31),  /* gate */
0477                   0);
0478 
0479 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
0480                   0, 4,     /* M */
0481                   8, 2,     /* P */
0482                   24, 3,    /* mux */
0483                   BIT(31),  /* gate */
0484                   0);
0485 
0486 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", nand_spi_parents, 0x948,
0487                   0, 4,     /* M */
0488                   8, 2,     /* P */
0489                   24, 3,    /* mux */
0490                   BIT(31),  /* gate */
0491                   0);
0492 
0493 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
0494 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
0495 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb3", 0x96c, BIT(2), 0);
0496 
0497 static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
0498               BIT(31) | BIT(30), 0);
0499 
0500 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0);
0501 
0502 static const char * const ir_parents[] = { "osc32k", "iosc",
0503                        "pll-periph0", "pll-periph1" };
0504 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_rx_clk, "ir-rx", ir_parents, 0x990,
0505                   0, 4,     /* M */
0506                   8, 2,     /* P */
0507                   24, 3,    /* mux */
0508                   BIT(31),  /* gate */
0509                   0);
0510 
0511 static SUNXI_CCU_GATE(bus_ir_rx_clk, "bus-ir-rx", "ahb3", 0x99c, BIT(0), 0);
0512 
0513 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_parents, 0x9c0,
0514                   0, 4,     /* M */
0515                   8, 2,     /* P */
0516                   24, 3,    /* mux */
0517                   BIT(31),  /* gate */
0518                   0);
0519 
0520 static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0);
0521 
0522 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
0523 
0524 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
0525 
0526 static const char * const audio_parents[] = { "pll-audio", "pll-com-audio" };
0527 static struct ccu_div i2s0_clk = {
0528     .enable     = BIT(31),
0529     .div        = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
0530     .mux        = _SUNXI_CCU_MUX(24, 2),
0531     .common     = {
0532         .reg        = 0xa10,
0533         .hw.init    = CLK_HW_INIT_PARENTS("i2s0",
0534                               audio_parents,
0535                               &ccu_div_ops,
0536                               CLK_SET_RATE_PARENT),
0537     },
0538 };
0539 
0540 static struct ccu_div i2s1_clk = {
0541     .enable     = BIT(31),
0542     .div        = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
0543     .mux        = _SUNXI_CCU_MUX(24, 2),
0544     .common     = {
0545         .reg        = 0xa14,
0546         .hw.init    = CLK_HW_INIT_PARENTS("i2s1",
0547                               audio_parents,
0548                               &ccu_div_ops,
0549                               CLK_SET_RATE_PARENT),
0550     },
0551 };
0552 
0553 static struct ccu_div i2s2_clk = {
0554     .enable     = BIT(31),
0555     .div        = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
0556     .mux        = _SUNXI_CCU_MUX(24, 2),
0557     .common     = {
0558         .reg        = 0xa18,
0559         .hw.init    = CLK_HW_INIT_PARENTS("i2s2",
0560                               audio_parents,
0561                               &ccu_div_ops,
0562                               CLK_SET_RATE_PARENT),
0563     },
0564 };
0565 
0566 static struct ccu_div i2s3_clk = {
0567     .enable     = BIT(31),
0568     .div        = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
0569     .mux        = _SUNXI_CCU_MUX(24, 2),
0570     .common     = {
0571         .reg        = 0xa1c,
0572         .hw.init    = CLK_HW_INIT_PARENTS("i2s3",
0573                               audio_parents,
0574                               &ccu_div_ops,
0575                               CLK_SET_RATE_PARENT),
0576     },
0577 };
0578 
0579 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa20, BIT(0), 0);
0580 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa20, BIT(1), 0);
0581 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa20, BIT(2), 0);
0582 static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa20, BIT(3), 0);
0583 
0584 static struct ccu_div spdif_clk = {
0585     .enable     = BIT(31),
0586     .div        = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
0587     .mux        = _SUNXI_CCU_MUX(24, 2),
0588     .common     = {
0589         .reg        = 0xa24,
0590         .hw.init    = CLK_HW_INIT_PARENTS("spdif",
0591                               audio_parents,
0592                               &ccu_div_ops,
0593                               0),
0594     },
0595 };
0596 
0597 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
0598 
0599 static struct ccu_div dmic_clk = {
0600     .enable     = BIT(31),
0601     .div        = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
0602     .mux        = _SUNXI_CCU_MUX(24, 2),
0603     .common     = {
0604         .reg        = 0xa40,
0605         .hw.init    = CLK_HW_INIT_PARENTS("dmic",
0606                               audio_parents,
0607                               &ccu_div_ops,
0608                               0),
0609     },
0610 };
0611 
0612 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
0613 
0614 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_dac_clk, "audio-codec-dac",
0615                  audio_parents, 0xa50,
0616                  0, 4,      /* M */
0617                  24, 2,     /* mux */
0618                  BIT(31),   /* gate */
0619                  0);
0620 
0621 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_adc_clk, "audio-codec-adc",
0622                  audio_parents, 0xa54,
0623                  0, 4,      /* M */
0624                  24, 2,     /* mux */
0625                  BIT(31),   /* gate */
0626                  0);
0627 
0628 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x",
0629                  audio_parents, 0xa58,
0630                  0, 4,      /* M */
0631                  24, 2,     /* mux */
0632                  BIT(31),   /* gate */
0633                  0);
0634 
0635 static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c,
0636               BIT(0), 0);
0637 
0638 /*
0639  * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
0640  * We will force them to 0 (12M divided from 48M).
0641  */
0642 #define SUN50I_A100_USB0_CLK_REG        0xa70
0643 #define SUN50I_A100_USB1_CLK_REG        0xa74
0644 
0645 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
0646 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "dcxo24M", 0xa70, BIT(29), 0);
0647 
0648 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
0649 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "dcxo24M", 0xa74, BIT(29), 0);
0650 
0651 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
0652 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0);
0653 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
0654 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0);
0655 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
0656 
0657 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "ahb3", 0xa9c, BIT(0), 0);
0658 
0659 static SUNXI_CCU_GATE(bus_dpss_top0_clk, "bus-dpss-top0", "ahb3",
0660               0xabc, BIT(0), 0);
0661 
0662 static SUNXI_CCU_GATE(bus_dpss_top1_clk, "bus-dpss-top1", "ahb3",
0663               0xacc, BIT(0), 0);
0664 
0665 static const char * const mipi_dsi_parents[] = { "dcxo24M", "pll-periph0-2x",
0666                          "pll-periph0" };
0667 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi",
0668                  mipi_dsi_parents,
0669                  0xb24,
0670                  0, 4,      /* M */
0671                  24, 2,     /* mux */
0672                  BIT(31),   /* gate */
0673                  0);
0674 
0675 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb3",
0676               0xb4c, BIT(0), 0);
0677 
0678 static const char * const tcon_lcd_parents[] = { "pll-video0-4x",
0679                           "pll-video1-4x",
0680                           "pll-video2-4x",
0681                           "pll-video3-4x",
0682                           "pll-periph0-2x" };
0683 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_lcd_clk, "tcon-lcd0",
0684                   tcon_lcd_parents, 0xb60,
0685                   0, 4,     /* M */
0686                   8, 2,     /* P */
0687                   24, 3,    /* mux */
0688                   BIT(31),  /* gate */
0689                   0);
0690 
0691 static SUNXI_CCU_GATE(bus_tcon_lcd_clk, "bus-tcon-lcd0", "ahb3",
0692               0xb7c, BIT(0), 0);
0693 
0694 static const char * const ledc_parents[] = { "dcxo24M",
0695                          "pll-periph0" };
0696 static SUNXI_CCU_MP_WITH_MUX_GATE(ledc_clk, "ledc",
0697                   ledc_parents, 0xbf0,
0698                   0, 4,     /* M */
0699                   8, 2,     /* P */
0700                   24, 3,    /* mux */
0701                   BIT(31),  /* gate */
0702                   0);
0703 
0704 static SUNXI_CCU_GATE(bus_ledc_clk, "bus-ledc", "ahb3", 0xbfc, BIT(0), 0);
0705 
0706 static const char * const csi_top_parents[] = { "pll-periph0-2x",
0707                         "pll-video0-2x",
0708                         "pll-video1-2x",
0709                         "pll-video2-2x",
0710                         "pll-video3-2x" };
0711 static SUNXI_CCU_M_WITH_MUX_GATE(csi_top_clk, "csi-top",
0712                  csi_top_parents, 0xc04,
0713                  0, 4,      /* M */
0714                  24, 3,     /* mux */
0715                  BIT(31),   /* gate */
0716                  0);
0717 
0718 static const char * const csi0_mclk_parents[] = { "dcxo24M", "pll-video2",
0719                           "pll-video3", "pll-video0",
0720                           "pll-video1" };
0721 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk",
0722                  csi0_mclk_parents, 0xc08,
0723                  0, 5,      /* M */
0724                  24, 3,     /* mux */
0725                  BIT(31),   /* gate */
0726                  0);
0727 
0728 static const char * const csi1_mclk_parents[] = { "dcxo24M", "pll-video3",
0729                           "pll-video0", "pll-video1",
0730                           "pll-video2" };
0731 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk",
0732                  csi1_mclk_parents, 0xc0c,
0733                  0, 5,      /* M */
0734                  24, 3,     /* mux */
0735                  BIT(31),   /* gate */
0736                  0);
0737 
0738 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc1c, BIT(0), 0);
0739 
0740 static const char * const csi_isp_parents[] = { "pll-periph0-2x",
0741                         "pll-video0-2x",
0742                         "pll-video1-2x",
0743                         "pll-video2-2x",
0744                         "pll-video3-2x" };
0745 static SUNXI_CCU_M_WITH_MUX_GATE(csi_isp_clk, "csi-isp",
0746                  csi_isp_parents, 0xc20,
0747                  0, 5,      /* M */
0748                  24, 3,     /* mux */
0749                  BIT(31),   /* gate */
0750                  0);
0751 
0752 /* Fixed factor clocks */
0753 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
0754 
0755 static CLK_FIXED_FACTOR_HW(pll_com_audio_clk, "pll-com-audio",
0756                &pll_com_clk.common.hw,
0757                5, 1, CLK_SET_RATE_PARENT);
0758 
0759 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
0760                &pll_periph0_clk.common.hw,
0761                1, 2, 0);
0762 
0763 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
0764                &pll_periph1_clk.common.hw,
0765                1, 2, 0);
0766 
0767 static const struct clk_hw *pll_video0_parents[] = {
0768     &pll_video0_clk.common.hw
0769 };
0770 static CLK_FIXED_FACTOR_HWS(pll_video0_4x_clk, "pll-video0-4x",
0771                 pll_video0_parents,
0772                 1, 4, CLK_SET_RATE_PARENT);
0773 static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x",
0774                 pll_video0_parents,
0775                 1, 2, CLK_SET_RATE_PARENT);
0776 
0777 static const struct clk_hw *pll_video1_parents[] = {
0778     &pll_video1_clk.common.hw
0779 };
0780 static CLK_FIXED_FACTOR_HWS(pll_video1_4x_clk, "pll-video1-4x",
0781                 pll_video1_parents,
0782                 1, 4, CLK_SET_RATE_PARENT);
0783 static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x",
0784                 pll_video1_parents,
0785                 1, 2, CLK_SET_RATE_PARENT);
0786 
0787 static const struct clk_hw *pll_video2_parents[] = {
0788     &pll_video2_clk.common.hw
0789 };
0790 static CLK_FIXED_FACTOR_HWS(pll_video2_4x_clk, "pll-video2-4x",
0791                 pll_video2_parents,
0792                 1, 4, CLK_SET_RATE_PARENT);
0793 static CLK_FIXED_FACTOR_HWS(pll_video2_2x_clk, "pll-video2-2x",
0794                 pll_video2_parents,
0795                 1, 2, CLK_SET_RATE_PARENT);
0796 
0797 static const struct clk_hw *pll_video3_parents[] = {
0798     &pll_video3_clk.common.hw
0799 };
0800 static CLK_FIXED_FACTOR_HWS(pll_video3_4x_clk, "pll-video3-4x",
0801                 pll_video3_parents,
0802                 1, 4, CLK_SET_RATE_PARENT);
0803 static CLK_FIXED_FACTOR_HWS(pll_video3_2x_clk, "pll-video3-2x",
0804                 pll_video3_parents,
0805                 1, 2, CLK_SET_RATE_PARENT);
0806 
0807 static struct ccu_common *sun50i_a100_ccu_clks[] = {
0808     &pll_cpux_clk.common,
0809     &pll_ddr0_clk.common,
0810     &pll_periph0_clk.common,
0811     &pll_periph1_clk.common,
0812     &pll_gpu_clk.common,
0813     &pll_video0_clk.common,
0814     &pll_video1_clk.common,
0815     &pll_video2_clk.common,
0816     &pll_video3_clk.common,
0817     &pll_ve_clk.common,
0818     &pll_com_clk.common,
0819     &pll_audio_clk.common,
0820     &cpux_clk.common,
0821     &axi_clk.common,
0822     &cpux_apb_clk.common,
0823     &psi_ahb1_ahb2_clk.common,
0824     &ahb3_clk.common,
0825     &apb1_clk.common,
0826     &apb2_clk.common,
0827     &mbus_clk.common,
0828     &de_clk.common,
0829     &bus_de_clk.common,
0830     &g2d_clk.common,
0831     &bus_g2d_clk.common,
0832     &gpu_clk.common,
0833     &bus_gpu_clk.common,
0834     &ce_clk.common,
0835     &bus_ce_clk.common,
0836     &ve_clk.common,
0837     &bus_ve_clk.common,
0838     &bus_dma_clk.common,
0839     &bus_msgbox_clk.common,
0840     &bus_spinlock_clk.common,
0841     &bus_hstimer_clk.common,
0842     &avs_clk.common,
0843     &bus_dbg_clk.common,
0844     &bus_psi_clk.common,
0845     &bus_pwm_clk.common,
0846     &bus_iommu_clk.common,
0847     &mbus_dma_clk.common,
0848     &mbus_ve_clk.common,
0849     &mbus_ce_clk.common,
0850     &mbus_nand_clk.common,
0851     &mbus_csi_clk.common,
0852     &mbus_isp_clk.common,
0853     &mbus_g2d_clk.common,
0854     &bus_dram_clk.common,
0855     &nand0_clk.common,
0856     &nand1_clk.common,
0857     &bus_nand_clk.common,
0858     &mmc0_clk.common,
0859     &mmc1_clk.common,
0860     &mmc2_clk.common,
0861     &bus_mmc0_clk.common,
0862     &bus_mmc1_clk.common,
0863     &bus_mmc2_clk.common,
0864     &bus_uart0_clk.common,
0865     &bus_uart1_clk.common,
0866     &bus_uart2_clk.common,
0867     &bus_uart3_clk.common,
0868     &bus_uart4_clk.common,
0869     &bus_i2c0_clk.common,
0870     &bus_i2c1_clk.common,
0871     &bus_i2c2_clk.common,
0872     &bus_i2c3_clk.common,
0873     &spi0_clk.common,
0874     &spi1_clk.common,
0875     &spi2_clk.common,
0876     &bus_spi0_clk.common,
0877     &bus_spi1_clk.common,
0878     &bus_spi2_clk.common,
0879     &emac_25m_clk.common,
0880     &bus_emac_clk.common,
0881     &ir_rx_clk.common,
0882     &bus_ir_rx_clk.common,
0883     &ir_tx_clk.common,
0884     &bus_ir_tx_clk.common,
0885     &bus_gpadc_clk.common,
0886     &bus_ths_clk.common,
0887     &i2s0_clk.common,
0888     &i2s1_clk.common,
0889     &i2s2_clk.common,
0890     &i2s3_clk.common,
0891     &bus_i2s0_clk.common,
0892     &bus_i2s1_clk.common,
0893     &bus_i2s2_clk.common,
0894     &bus_i2s3_clk.common,
0895     &spdif_clk.common,
0896     &bus_spdif_clk.common,
0897     &dmic_clk.common,
0898     &bus_dmic_clk.common,
0899     &audio_codec_dac_clk.common,
0900     &audio_codec_adc_clk.common,
0901     &audio_codec_4x_clk.common,
0902     &bus_audio_codec_clk.common,
0903     &usb_ohci0_clk.common,
0904     &usb_phy0_clk.common,
0905     &usb_ohci1_clk.common,
0906     &usb_phy1_clk.common,
0907     &bus_ohci0_clk.common,
0908     &bus_ohci1_clk.common,
0909     &bus_ehci0_clk.common,
0910     &bus_ehci1_clk.common,
0911     &bus_otg_clk.common,
0912     &bus_lradc_clk.common,
0913     &bus_dpss_top0_clk.common,
0914     &bus_dpss_top1_clk.common,
0915     &mipi_dsi_clk.common,
0916     &bus_mipi_dsi_clk.common,
0917     &tcon_lcd_clk.common,
0918     &bus_tcon_lcd_clk.common,
0919     &ledc_clk.common,
0920     &bus_ledc_clk.common,
0921     &csi_top_clk.common,
0922     &csi0_mclk_clk.common,
0923     &csi1_mclk_clk.common,
0924     &bus_csi_clk.common,
0925     &csi_isp_clk.common,
0926 };
0927 
0928 static struct clk_hw_onecell_data sun50i_a100_hw_clks = {
0929     .hws    = {
0930         [CLK_OSC12M]        = &osc12M_clk.hw,
0931         [CLK_PLL_CPUX]      = &pll_cpux_clk.common.hw,
0932         [CLK_PLL_DDR0]      = &pll_ddr0_clk.common.hw,
0933         [CLK_PLL_PERIPH0]   = &pll_periph0_clk.common.hw,
0934         [CLK_PLL_PERIPH0_2X]    = &pll_periph0_2x_clk.hw,
0935         [CLK_PLL_PERIPH1]   = &pll_periph1_clk.common.hw,
0936         [CLK_PLL_PERIPH1_2X]    = &pll_periph1_2x_clk.hw,
0937         [CLK_PLL_GPU]       = &pll_gpu_clk.common.hw,
0938         [CLK_PLL_VIDEO0]    = &pll_video0_clk.common.hw,
0939         [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
0940         [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw,
0941         [CLK_PLL_VIDEO1]    = &pll_video1_clk.common.hw,
0942         [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
0943         [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw,
0944         [CLK_PLL_VIDEO2]    = &pll_video2_clk.common.hw,
0945         [CLK_PLL_VIDEO2_2X] = &pll_video2_2x_clk.hw,
0946         [CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.hw,
0947         [CLK_PLL_VIDEO3]    = &pll_video3_clk.common.hw,
0948         [CLK_PLL_VIDEO3_2X] = &pll_video3_2x_clk.hw,
0949         [CLK_PLL_VIDEO3_4X] = &pll_video3_4x_clk.hw,
0950         [CLK_PLL_VE]        = &pll_ve_clk.common.hw,
0951         [CLK_PLL_COM]       = &pll_com_clk.common.hw,
0952         [CLK_PLL_COM_AUDIO] = &pll_com_audio_clk.hw,
0953         [CLK_PLL_AUDIO]     = &pll_audio_clk.common.hw,
0954         [CLK_CPUX]      = &cpux_clk.common.hw,
0955         [CLK_AXI]       = &axi_clk.common.hw,
0956         [CLK_CPUX_APB]      = &cpux_apb_clk.common.hw,
0957         [CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw,
0958         [CLK_AHB3]      = &ahb3_clk.common.hw,
0959         [CLK_APB1]      = &apb1_clk.common.hw,
0960         [CLK_APB2]      = &apb2_clk.common.hw,
0961         [CLK_MBUS]      = &mbus_clk.common.hw,
0962         [CLK_DE]        = &de_clk.common.hw,
0963         [CLK_BUS_DE]        = &bus_de_clk.common.hw,
0964         [CLK_G2D]       = &g2d_clk.common.hw,
0965         [CLK_BUS_G2D]       = &bus_g2d_clk.common.hw,
0966         [CLK_GPU]       = &gpu_clk.common.hw,
0967         [CLK_BUS_GPU]       = &bus_gpu_clk.common.hw,
0968         [CLK_CE]        = &ce_clk.common.hw,
0969         [CLK_BUS_CE]        = &bus_ce_clk.common.hw,
0970         [CLK_VE]        = &ve_clk.common.hw,
0971         [CLK_BUS_VE]        = &bus_ve_clk.common.hw,
0972         [CLK_BUS_DMA]       = &bus_dma_clk.common.hw,
0973         [CLK_BUS_MSGBOX]    = &bus_msgbox_clk.common.hw,
0974         [CLK_BUS_SPINLOCK]  = &bus_spinlock_clk.common.hw,
0975         [CLK_BUS_HSTIMER]   = &bus_hstimer_clk.common.hw,
0976         [CLK_AVS]       = &avs_clk.common.hw,
0977         [CLK_BUS_DBG]       = &bus_dbg_clk.common.hw,
0978         [CLK_BUS_PSI]       = &bus_psi_clk.common.hw,
0979         [CLK_BUS_PWM]       = &bus_pwm_clk.common.hw,
0980         [CLK_BUS_IOMMU]     = &bus_iommu_clk.common.hw,
0981         [CLK_MBUS_DMA]      = &mbus_dma_clk.common.hw,
0982         [CLK_MBUS_VE]       = &mbus_ve_clk.common.hw,
0983         [CLK_MBUS_CE]       = &mbus_ce_clk.common.hw,
0984         [CLK_MBUS_NAND]     = &mbus_nand_clk.common.hw,
0985         [CLK_MBUS_CSI]      = &mbus_csi_clk.common.hw,
0986         [CLK_MBUS_ISP]      = &mbus_isp_clk.common.hw,
0987         [CLK_MBUS_G2D]      = &mbus_g2d_clk.common.hw,
0988         [CLK_BUS_DRAM]      = &bus_dram_clk.common.hw,
0989         [CLK_NAND0]     = &nand0_clk.common.hw,
0990         [CLK_NAND1]     = &nand1_clk.common.hw,
0991         [CLK_BUS_NAND]      = &bus_nand_clk.common.hw,
0992         [CLK_MMC0]      = &mmc0_clk.common.hw,
0993         [CLK_MMC1]      = &mmc1_clk.common.hw,
0994         [CLK_MMC2]      = &mmc2_clk.common.hw,
0995         [CLK_BUS_MMC0]      = &bus_mmc0_clk.common.hw,
0996         [CLK_BUS_MMC1]      = &bus_mmc1_clk.common.hw,
0997         [CLK_BUS_MMC2]      = &bus_mmc2_clk.common.hw,
0998         [CLK_BUS_UART0]     = &bus_uart0_clk.common.hw,
0999         [CLK_BUS_UART1]     = &bus_uart1_clk.common.hw,
1000         [CLK_BUS_UART2]     = &bus_uart2_clk.common.hw,
1001         [CLK_BUS_UART3]     = &bus_uart3_clk.common.hw,
1002         [CLK_BUS_UART4]     = &bus_uart4_clk.common.hw,
1003         [CLK_BUS_I2C0]      = &bus_i2c0_clk.common.hw,
1004         [CLK_BUS_I2C1]      = &bus_i2c1_clk.common.hw,
1005         [CLK_BUS_I2C2]      = &bus_i2c2_clk.common.hw,
1006         [CLK_BUS_I2C3]      = &bus_i2c3_clk.common.hw,
1007         [CLK_SPI0]      = &spi0_clk.common.hw,
1008         [CLK_SPI1]      = &spi1_clk.common.hw,
1009         [CLK_SPI2]      = &spi2_clk.common.hw,
1010         [CLK_BUS_SPI0]      = &bus_spi0_clk.common.hw,
1011         [CLK_BUS_SPI1]      = &bus_spi1_clk.common.hw,
1012         [CLK_BUS_SPI2]      = &bus_spi2_clk.common.hw,
1013         [CLK_EMAC_25M]      = &emac_25m_clk.common.hw,
1014         [CLK_BUS_EMAC]      = &bus_emac_clk.common.hw,
1015         [CLK_IR_RX]     = &ir_rx_clk.common.hw,
1016         [CLK_BUS_IR_RX]     = &bus_ir_rx_clk.common.hw,
1017         [CLK_IR_TX]     = &ir_tx_clk.common.hw,
1018         [CLK_BUS_IR_TX]     = &bus_ir_tx_clk.common.hw,
1019         [CLK_BUS_GPADC]     = &bus_gpadc_clk.common.hw,
1020         [CLK_BUS_THS]       = &bus_ths_clk.common.hw,
1021         [CLK_I2S0]      = &i2s0_clk.common.hw,
1022         [CLK_I2S1]      = &i2s1_clk.common.hw,
1023         [CLK_I2S2]      = &i2s2_clk.common.hw,
1024         [CLK_I2S3]      = &i2s3_clk.common.hw,
1025         [CLK_BUS_I2S0]      = &bus_i2s0_clk.common.hw,
1026         [CLK_BUS_I2S1]      = &bus_i2s1_clk.common.hw,
1027         [CLK_BUS_I2S2]      = &bus_i2s2_clk.common.hw,
1028         [CLK_BUS_I2S3]      = &bus_i2s3_clk.common.hw,
1029         [CLK_SPDIF]     = &spdif_clk.common.hw,
1030         [CLK_BUS_SPDIF]     = &bus_spdif_clk.common.hw,
1031         [CLK_DMIC]      = &dmic_clk.common.hw,
1032         [CLK_BUS_DMIC]      = &bus_dmic_clk.common.hw,
1033         [CLK_AUDIO_DAC]     = &audio_codec_dac_clk.common.hw,
1034         [CLK_AUDIO_ADC]     = &audio_codec_adc_clk.common.hw,
1035         [CLK_AUDIO_4X]      = &audio_codec_4x_clk.common.hw,
1036         [CLK_BUS_AUDIO_CODEC]   = &bus_audio_codec_clk.common.hw,
1037         [CLK_USB_OHCI0]     = &usb_ohci0_clk.common.hw,
1038         [CLK_USB_PHY0]      = &usb_phy0_clk.common.hw,
1039         [CLK_USB_OHCI1]     = &usb_ohci1_clk.common.hw,
1040         [CLK_USB_PHY1]      = &usb_phy1_clk.common.hw,
1041         [CLK_BUS_OHCI0]     = &bus_ohci0_clk.common.hw,
1042         [CLK_BUS_OHCI1]     = &bus_ohci1_clk.common.hw,
1043         [CLK_BUS_EHCI0]     = &bus_ehci0_clk.common.hw,
1044         [CLK_BUS_EHCI1]     = &bus_ehci1_clk.common.hw,
1045         [CLK_BUS_OTG]       = &bus_otg_clk.common.hw,
1046         [CLK_BUS_LRADC]     = &bus_lradc_clk.common.hw,
1047         [CLK_BUS_DPSS_TOP0] = &bus_dpss_top0_clk.common.hw,
1048         [CLK_BUS_DPSS_TOP1] = &bus_dpss_top1_clk.common.hw,
1049         [CLK_MIPI_DSI]      = &mipi_dsi_clk.common.hw,
1050         [CLK_BUS_MIPI_DSI]  = &bus_mipi_dsi_clk.common.hw,
1051         [CLK_TCON_LCD]      = &tcon_lcd_clk.common.hw,
1052         [CLK_BUS_TCON_LCD]  = &bus_tcon_lcd_clk.common.hw,
1053         [CLK_LEDC]      = &ledc_clk.common.hw,
1054         [CLK_BUS_LEDC]      = &bus_ledc_clk.common.hw,
1055         [CLK_CSI_TOP]       = &csi_top_clk.common.hw,
1056         [CLK_CSI0_MCLK]     = &csi0_mclk_clk.common.hw,
1057         [CLK_CSI1_MCLK]     = &csi1_mclk_clk.common.hw,
1058         [CLK_BUS_CSI]       = &bus_csi_clk.common.hw,
1059         [CLK_CSI_ISP]       = &csi_isp_clk.common.hw,
1060     },
1061     .num = CLK_NUMBER,
1062 };
1063 
1064 static struct ccu_reset_map sun50i_a100_ccu_resets[] = {
1065     [RST_MBUS]      = { 0x540, BIT(30) },
1066 
1067     [RST_BUS_DE]        = { 0x60c, BIT(16) },
1068     [RST_BUS_G2D]       = { 0x63c, BIT(16) },
1069     [RST_BUS_GPU]       = { 0x67c, BIT(16) },
1070     [RST_BUS_CE]        = { 0x68c, BIT(16) },
1071     [RST_BUS_VE]        = { 0x69c, BIT(16) },
1072     [RST_BUS_DMA]       = { 0x70c, BIT(16) },
1073     [RST_BUS_MSGBOX]    = { 0x71c, BIT(16) },
1074     [RST_BUS_SPINLOCK]  = { 0x72c, BIT(16) },
1075     [RST_BUS_HSTIMER]   = { 0x73c, BIT(16) },
1076     [RST_BUS_DBG]       = { 0x78c, BIT(16) },
1077     [RST_BUS_PSI]       = { 0x79c, BIT(16) },
1078     [RST_BUS_PWM]       = { 0x7ac, BIT(16) },
1079     [RST_BUS_DRAM]      = { 0x80c, BIT(16) },
1080     [RST_BUS_NAND]      = { 0x82c, BIT(16) },
1081     [RST_BUS_MMC0]      = { 0x84c, BIT(16) },
1082     [RST_BUS_MMC1]      = { 0x84c, BIT(17) },
1083     [RST_BUS_MMC2]      = { 0x84c, BIT(18) },
1084     [RST_BUS_UART0]     = { 0x90c, BIT(16) },
1085     [RST_BUS_UART1]     = { 0x90c, BIT(17) },
1086     [RST_BUS_UART2]     = { 0x90c, BIT(18) },
1087     [RST_BUS_UART3]     = { 0x90c, BIT(19) },
1088     [RST_BUS_UART4]     = { 0x90c, BIT(20) },
1089     [RST_BUS_I2C0]      = { 0x91c, BIT(16) },
1090     [RST_BUS_I2C1]      = { 0x91c, BIT(17) },
1091     [RST_BUS_I2C2]      = { 0x91c, BIT(18) },
1092     [RST_BUS_I2C3]      = { 0x91c, BIT(19) },
1093     [RST_BUS_SPI0]      = { 0x96c, BIT(16) },
1094     [RST_BUS_SPI1]      = { 0x96c, BIT(17) },
1095     [RST_BUS_SPI2]      = { 0x96c, BIT(18) },
1096     [RST_BUS_EMAC]      = { 0x97c, BIT(16) },
1097     [RST_BUS_IR_RX]     = { 0x99c, BIT(16) },
1098     [RST_BUS_IR_TX]     = { 0x9cc, BIT(16) },
1099     [RST_BUS_GPADC]     = { 0x9ec, BIT(16) },
1100     [RST_BUS_THS]       = { 0x9fc, BIT(16) },
1101     [RST_BUS_I2S0]      = { 0xa20, BIT(16) },
1102     [RST_BUS_I2S1]      = { 0xa20, BIT(17) },
1103     [RST_BUS_I2S2]      = { 0xa20, BIT(18) },
1104     [RST_BUS_I2S3]      = { 0xa20, BIT(19) },
1105     [RST_BUS_SPDIF]     = { 0xa2c, BIT(16) },
1106     [RST_BUS_DMIC]      = { 0xa4c, BIT(16) },
1107     [RST_BUS_AUDIO_CODEC]   = { 0xa5c, BIT(16) },
1108 
1109     [RST_USB_PHY0]      = { 0xa70, BIT(30) },
1110     [RST_USB_PHY1]      = { 0xa74, BIT(30) },
1111 
1112     [RST_BUS_OHCI0]     = { 0xa8c, BIT(16) },
1113     [RST_BUS_OHCI1]     = { 0xa8c, BIT(17) },
1114     [RST_BUS_EHCI0]     = { 0xa8c, BIT(20) },
1115     [RST_BUS_EHCI1]     = { 0xa8c, BIT(21) },
1116     [RST_BUS_OTG]       = { 0xa8c, BIT(24) },
1117 
1118     [RST_BUS_LRADC]     = { 0xa9c, BIT(16) },
1119     [RST_BUS_DPSS_TOP0] = { 0xabc, BIT(16) },
1120     [RST_BUS_DPSS_TOP1] = { 0xacc, BIT(16) },
1121     [RST_BUS_MIPI_DSI]  = { 0xb4c, BIT(16) },
1122     [RST_BUS_TCON_LCD]  = { 0xb7c, BIT(16) },
1123     [RST_BUS_LVDS]      = { 0xbac, BIT(16) },
1124     [RST_BUS_LEDC]      = { 0xbfc, BIT(16) },
1125     [RST_BUS_CSI]       = { 0xc1c, BIT(16) },
1126     [RST_BUS_CSI_ISP]   = { 0xc2c, BIT(16) },
1127 };
1128 
1129 static const struct sunxi_ccu_desc sun50i_a100_ccu_desc = {
1130     .ccu_clks   = sun50i_a100_ccu_clks,
1131     .num_ccu_clks   = ARRAY_SIZE(sun50i_a100_ccu_clks),
1132 
1133     .hw_clks    = &sun50i_a100_hw_clks,
1134 
1135     .resets     = sun50i_a100_ccu_resets,
1136     .num_resets = ARRAY_SIZE(sun50i_a100_ccu_resets),
1137 };
1138 
1139 static const u32 sun50i_a100_pll_regs[] = {
1140     SUN50I_A100_PLL_CPUX_REG,
1141     SUN50I_A100_PLL_DDR0_REG,
1142     SUN50I_A100_PLL_PERIPH0_REG,
1143     SUN50I_A100_PLL_PERIPH1_REG,
1144     SUN50I_A100_PLL_GPU_REG,
1145     SUN50I_A100_PLL_VIDEO0_REG,
1146     SUN50I_A100_PLL_VIDEO1_REG,
1147     SUN50I_A100_PLL_VIDEO2_REG,
1148     SUN50I_A100_PLL_VIDEO3_REG,
1149     SUN50I_A100_PLL_VE_REG,
1150     SUN50I_A100_PLL_COM_REG,
1151     SUN50I_A100_PLL_AUDIO_REG,
1152 };
1153 
1154 static const u32 sun50i_a100_pll_video_regs[] = {
1155     SUN50I_A100_PLL_VIDEO0_REG,
1156     SUN50I_A100_PLL_VIDEO1_REG,
1157     SUN50I_A100_PLL_VIDEO2_REG,
1158     SUN50I_A100_PLL_VIDEO3_REG,
1159 };
1160 
1161 static const u32 sun50i_a100_usb2_clk_regs[] = {
1162     SUN50I_A100_USB0_CLK_REG,
1163     SUN50I_A100_USB1_CLK_REG,
1164 };
1165 
1166 static struct ccu_pll_nb sun50i_a100_pll_cpu_nb = {
1167     .common = &pll_cpux_clk.common,
1168     /* copy from pll_cpux_clk */
1169     .enable = BIT(27),
1170     .lock   = BIT(28),
1171 };
1172 
1173 static struct ccu_mux_nb sun50i_a100_cpu_nb = {
1174     .common         = &cpux_clk.common,
1175     .cm             = &cpux_clk.mux,
1176     .delay_us       = 1,
1177     .bypass_index   = 4, /* index of pll periph0 */
1178 };
1179 
1180 static int sun50i_a100_ccu_probe(struct platform_device *pdev)
1181 {
1182     void __iomem *reg;
1183     u32 val;
1184     int i, ret;
1185 
1186     reg = devm_platform_ioremap_resource(pdev, 0);
1187     if (IS_ERR(reg))
1188         return PTR_ERR(reg);
1189 
1190     /*
1191      * Enable lock and enable bits on all PLLs.
1192      *
1193      * Due to the current design, multiple PLLs share one power switch,
1194      * so switching PLL is easy to cause stability problems.
1195      * When initializing, we enable them by default. When disable,
1196      * we only turn off the output of PLL.
1197      */
1198     for (i = 0; i < ARRAY_SIZE(sun50i_a100_pll_regs); i++) {
1199         val = readl(reg + sun50i_a100_pll_regs[i]);
1200         val |= SUN50I_A100_PLL_LOCK_ENABLE | SUN50I_A100_PLL_ENABLE;
1201         writel(val, reg + sun50i_a100_pll_regs[i]);
1202     }
1203 
1204     /*
1205      * In order to pass the EMI certification, the SDM function of
1206      * the peripheral 1 bus is enabled, and the frequency is still
1207      * calculated using the previous division factor.
1208      */
1209     writel(SUN50I_A100_PLL_PERIPH1_PATTERN0,
1210            reg + SUN50I_A100_PLL_PERIPH1_PATTERN0_REG);
1211 
1212     val = readl(reg + SUN50I_A100_PLL_PERIPH1_REG);
1213     val |= SUN50I_A100_PLL_SDM_ENABLE;
1214     writel(val, reg + SUN50I_A100_PLL_PERIPH1_REG);
1215 
1216     /*
1217      * Force the output divider of video PLLs to 0.
1218      *
1219      * See the comment before pll-video0 definition for the reason.
1220      */
1221     for (i = 0; i < ARRAY_SIZE(sun50i_a100_pll_video_regs); i++) {
1222         val = readl(reg + sun50i_a100_pll_video_regs[i]);
1223         val &= ~BIT(0);
1224         writel(val, reg + sun50i_a100_pll_video_regs[i]);
1225     }
1226 
1227     /*
1228      * Enforce m1 = 0, m0 = 1 for Audio PLL
1229      *
1230      * See the comment before pll-audio definition for the reason.
1231      */
1232     val = readl(reg + SUN50I_A100_PLL_AUDIO_REG);
1233     val &= ~BIT(1);
1234     val |= BIT(0);
1235     writel(val, reg + SUN50I_A100_PLL_AUDIO_REG);
1236 
1237     /*
1238      * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
1239      *
1240      * This clock mux is still mysterious, and the code just enforces
1241      * it to have a valid clock parent.
1242      */
1243     for (i = 0; i < ARRAY_SIZE(sun50i_a100_usb2_clk_regs); i++) {
1244         val = readl(reg + sun50i_a100_usb2_clk_regs[i]);
1245         val &= ~GENMASK(25, 24);
1246         writel(val, reg + sun50i_a100_usb2_clk_regs[i]);
1247     }
1248 
1249     ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a100_ccu_desc);
1250     if (ret)
1251         return ret;
1252 
1253     /* Gate then ungate PLL CPU after any rate changes */
1254     ccu_pll_notifier_register(&sun50i_a100_pll_cpu_nb);
1255 
1256     /* Reparent CPU during PLL CPU rate changes */
1257     ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
1258                   &sun50i_a100_cpu_nb);
1259 
1260     return 0;
1261 }
1262 
1263 static const struct of_device_id sun50i_a100_ccu_ids[] = {
1264     { .compatible = "allwinner,sun50i-a100-ccu" },
1265     { }
1266 };
1267 
1268 static struct platform_driver sun50i_a100_ccu_driver = {
1269     .probe  = sun50i_a100_ccu_probe,
1270     .driver = {
1271         .name   = "sun50i-a100-ccu",
1272         .suppress_bind_attrs = true,
1273         .of_match_table = sun50i_a100_ccu_ids,
1274     },
1275 };
1276 module_platform_driver(sun50i_a100_ccu_driver);
1277 
1278 MODULE_IMPORT_NS(SUNXI_CCU);
1279 MODULE_LICENSE("GPL");
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