clk/sunxi-ng/ccu-sun4i-a10.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2017 Priit Laes
0004  *
0005  * Priit Laes <plaes@plaes.org>
0006  */
0007
0008 #ifndef _CCU_SUN4I_A10_H_
0009 #define _CCU_SUN4I_A10_H_
0010
0011 #include <dt-bindings/clock/sun4i-a10-ccu.h>
0012 #include <dt-bindings/clock/sun7i-a20-ccu.h>
0013 #include <dt-bindings/reset/sun4i-a10-ccu.h>
0014
0015 /* The HOSC is exported */
0016 #define CLK_PLL_CORE        2
0017 #define CLK_PLL_AUDIO_BASE  3
0018 #define CLK_PLL_AUDIO       4
0019 #define CLK_PLL_AUDIO_2X    5
0020 #define CLK_PLL_AUDIO_4X    6
0021 #define CLK_PLL_AUDIO_8X    7
0022 #define CLK_PLL_VIDEO0      8
0023 /* The PLL_VIDEO0_2X clock is exported */
0024 #define CLK_PLL_VE      10
0025 #define CLK_PLL_DDR_BASE    11
0026 #define CLK_PLL_DDR     12
0027 #define CLK_PLL_DDR_OTHER   13
0028 #define CLK_PLL_PERIPH_BASE 14
0029 #define CLK_PLL_PERIPH      15
0030 #define CLK_PLL_PERIPH_SATA 16
0031 #define CLK_PLL_VIDEO1      17
0032 /* The PLL_VIDEO1_2X clock is exported */
0033 #define CLK_PLL_GPU     19
0034
0035 /* The CPU clock is exported */
0036 #define CLK_AXI         21
0037 #define CLK_AXI_DRAM        22
0038 #define CLK_AHB         23
0039 #define CLK_APB0        24
0040 #define CLK_APB1        25
0041
0042 /* AHB gates are exported (23..68) */
0043 /* APB0 gates are exported (69..78) */
0044 /* APB1 gates are exported (79..95) */
0045 /* IP module clocks are exported (96..128) */
0046 /* DRAM gates are exported (129..142)*/
0047 /* Media (display engine clocks & etc) are exported (143..169) */
0048
0049 #define CLK_NUMBER_SUN4I    (CLK_MBUS + 1)
0050 #define CLK_NUMBER_SUN7I    (CLK_OUT_B + 1)
0051
0052 #endif /* _CCU_SUN4I_A10_H_ */