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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020 huangzhenwei@allwinnertech.com
0004  * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
0005  */
0006 
0007 #include <linux/clk-provider.h>
0008 #include <linux/io.h>
0009 #include <linux/module.h>
0010 #include <linux/platform_device.h>
0011 
0012 #include "../clk.h"
0013 
0014 #include "ccu_common.h"
0015 #include "ccu_reset.h"
0016 
0017 #include "ccu_div.h"
0018 #include "ccu_gate.h"
0019 #include "ccu_mp.h"
0020 #include "ccu_mult.h"
0021 #include "ccu_nk.h"
0022 #include "ccu_nkm.h"
0023 #include "ccu_nkmp.h"
0024 #include "ccu_nm.h"
0025 
0026 #include "ccu-sun20i-d1.h"
0027 
0028 static const struct clk_parent_data osc24M[] = {
0029     { .fw_name = "hosc" }
0030 };
0031 
0032 /*
0033  * For the CPU PLL, the output divider is described as "only for testing"
0034  * in the user manual. So it's not modelled and forced to 0.
0035  */
0036 #define SUN20I_D1_PLL_CPUX_REG      0x000
0037 static struct ccu_mult pll_cpux_clk = {
0038     .enable     = BIT(27),
0039     .lock       = BIT(28),
0040     .mult       = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0041     .common     = {
0042         .reg        = 0x000,
0043         .hw.init    = CLK_HW_INIT_PARENTS_DATA("pll-cpux", osc24M,
0044                                &ccu_mult_ops,
0045                                CLK_SET_RATE_UNGATE),
0046     },
0047 };
0048 
0049 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
0050 #define SUN20I_D1_PLL_DDR0_REG      0x010
0051 static struct ccu_nkmp pll_ddr0_clk = {
0052     .enable     = BIT(27),
0053     .lock       = BIT(28),
0054     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0055     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0056     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0057     .common     = {
0058         .reg        = 0x010,
0059         .hw.init    = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
0060                                &ccu_nkmp_ops,
0061                                CLK_SET_RATE_UNGATE),
0062     },
0063 };
0064 
0065 #define SUN20I_D1_PLL_PERIPH0_REG   0x020
0066 static struct ccu_nm pll_periph0_4x_clk = {
0067     .enable     = BIT(27),
0068     .lock       = BIT(28),
0069     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0070     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0071     .common     = {
0072         .reg        = 0x020,
0073         .hw.init    = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x", osc24M,
0074                                &ccu_nm_ops,
0075                                CLK_SET_RATE_UNGATE),
0076     },
0077 };
0078 
0079 static const struct clk_hw *pll_periph0_4x_hws[] = {
0080     &pll_periph0_4x_clk.common.hw
0081 };
0082 static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
0083                pll_periph0_4x_hws, 0x020, 16, 3, 0);
0084 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
0085                pll_periph0_4x_hws, 0x020, 20, 3, 0);
0086 
0087 static const struct clk_hw *pll_periph0_2x_hws[] = {
0088     &pll_periph0_2x_clk.common.hw
0089 };
0090 static CLK_FIXED_FACTOR_HWS(pll_periph0_clk, "pll-periph0",
0091                 pll_periph0_2x_hws, 2, 1, 0);
0092 
0093 static const struct clk_hw *pll_periph0_hws[] = { &pll_periph0_clk.hw };
0094 static CLK_FIXED_FACTOR_HWS(pll_periph0_div3_clk, "pll-periph0-div3",
0095                 pll_periph0_2x_hws, 6, 1, 0);
0096 
0097 /*
0098  * For Video PLLs, the output divider is described as "only for testing"
0099  * in the user manual. So it's not modelled and forced to 0.
0100  */
0101 #define SUN20I_D1_PLL_VIDEO0_REG    0x040
0102 static struct ccu_nm pll_video0_4x_clk = {
0103     .enable     = BIT(27),
0104     .lock       = BIT(28),
0105     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0106     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0107     .common     = {
0108         .reg        = 0x040,
0109         .hw.init    = CLK_HW_INIT_PARENTS_DATA("pll-video0-4x", osc24M,
0110                                &ccu_nm_ops,
0111                                CLK_SET_RATE_UNGATE),
0112     },
0113 };
0114 
0115 static const struct clk_hw *pll_video0_4x_hws[] = {
0116     &pll_video0_4x_clk.common.hw
0117 };
0118 static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x",
0119                 pll_video0_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
0120 static CLK_FIXED_FACTOR_HWS(pll_video0_clk, "pll-video0",
0121                 pll_video0_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
0122 
0123 #define SUN20I_D1_PLL_VIDEO1_REG    0x048
0124 static struct ccu_nm pll_video1_4x_clk = {
0125     .enable     = BIT(27),
0126     .lock       = BIT(28),
0127     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0128     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0129     .common     = {
0130         .reg        = 0x048,
0131         .hw.init    = CLK_HW_INIT_PARENTS_DATA("pll-video1-4x", osc24M,
0132                                &ccu_nm_ops,
0133                                CLK_SET_RATE_UNGATE),
0134     },
0135 };
0136 
0137 static const struct clk_hw *pll_video1_4x_hws[] = {
0138     &pll_video1_4x_clk.common.hw
0139 };
0140 static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x",
0141                 pll_video1_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
0142 static CLK_FIXED_FACTOR_HWS(pll_video1_clk, "pll-video1",
0143                 pll_video1_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
0144 
0145 #define SUN20I_D1_PLL_VE_REG        0x058
0146 static struct ccu_nkmp pll_ve_clk = {
0147     .enable     = BIT(27),
0148     .lock       = BIT(28),
0149     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0150     .m      = _SUNXI_CCU_DIV(1, 1), /* input divider */
0151     .p      = _SUNXI_CCU_DIV(0, 1), /* output divider */
0152     .common     = {
0153         .reg        = 0x058,
0154         .hw.init    = CLK_HW_INIT_PARENTS_DATA("pll-ve", osc24M,
0155                                &ccu_nkmp_ops,
0156                                CLK_SET_RATE_UNGATE),
0157     },
0158 };
0159 
0160 /*
0161  * PLL_AUDIO0 has m0, m1 dividers in addition to the usual N, M factors.
0162  * Since we only need one frequency from this PLL (22.5792 x 4 == 90.3168 MHz),
0163  * ignore them for now. Enforce the default for them, which is m1 = 0, m0 = 0.
0164  * The M factor must be an even number to produce a 50% duty cycle output.
0165  */
0166 #define SUN20I_D1_PLL_AUDIO0_REG        0x078
0167 static struct ccu_sdm_setting pll_audio0_sdm_table[] = {
0168     { .rate = 90316800, .pattern = 0xc001288d, .m = 6, .n = 22 },
0169 };
0170 
0171 static struct ccu_nm pll_audio0_4x_clk = {
0172     .enable     = BIT(27),
0173     .lock       = BIT(28),
0174     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0175     .m      = _SUNXI_CCU_DIV(16, 6),
0176     .sdm        = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
0177                      0x178, BIT(31)),
0178     .common     = {
0179         .reg        = 0x078,
0180         .features   = CCU_FEATURE_SIGMA_DELTA_MOD,
0181         .hw.init    = CLK_HW_INIT_PARENTS_DATA("pll-audio0-4x", osc24M,
0182                                &ccu_nm_ops,
0183                                CLK_SET_RATE_UNGATE),
0184     },
0185 };
0186 
0187 static const struct clk_hw *pll_audio0_4x_hws[] = {
0188     &pll_audio0_4x_clk.common.hw
0189 };
0190 static CLK_FIXED_FACTOR_HWS(pll_audio0_2x_clk, "pll-audio0-2x",
0191                 pll_audio0_4x_hws, 2, 1, 0);
0192 static CLK_FIXED_FACTOR_HWS(pll_audio0_clk, "pll-audio0",
0193                 pll_audio0_4x_hws, 4, 1, 0);
0194 
0195 /*
0196  * PLL_AUDIO1 doesn't need Fractional-N. The output is usually 614.4 MHz for
0197  * audio. The ADC or DAC should divide the PLL output further to 24.576 MHz.
0198  */
0199 #define SUN20I_D1_PLL_AUDIO1_REG        0x080
0200 static struct ccu_nm pll_audio1_clk = {
0201     .enable     = BIT(27),
0202     .lock       = BIT(28),
0203     .n      = _SUNXI_CCU_MULT_MIN(8, 8, 12),
0204     .m      = _SUNXI_CCU_DIV(1, 1),
0205     .common     = {
0206         .reg        = 0x080,
0207         .hw.init    = CLK_HW_INIT_PARENTS_DATA("pll-audio1", osc24M,
0208                                &ccu_nm_ops,
0209                                CLK_SET_RATE_UNGATE),
0210     },
0211 };
0212 
0213 static const struct clk_hw *pll_audio1_hws[] = {
0214     &pll_audio1_clk.common.hw
0215 };
0216 static SUNXI_CCU_M_HWS(pll_audio1_div2_clk, "pll-audio1-div2",
0217                pll_audio1_hws, 0x080, 16, 3, 0);
0218 static SUNXI_CCU_M_HWS(pll_audio1_div5_clk, "pll-audio1-div5",
0219                pll_audio1_hws, 0x080, 20, 3, 0);
0220 
0221 /*
0222  * The CPUX gate is not modelled - it is in a separate register (0x504)
0223  * and has a special key field. The clock does not need to be ungated anyway.
0224  */
0225 static const struct clk_parent_data cpux_parents[] = {
0226     { .fw_name = "hosc" },
0227     { .fw_name = "losc" },
0228     { .fw_name = "iosc" },
0229     { .hw = &pll_cpux_clk.common.hw },
0230     { .hw = &pll_periph0_clk.hw },
0231     { .hw = &pll_periph0_2x_clk.common.hw },
0232     { .hw = &pll_periph0_800M_clk.common.hw },
0233 };
0234 static SUNXI_CCU_MUX_DATA(cpux_clk, "cpux", cpux_parents,
0235               0x500, 24, 3, CLK_SET_RATE_PARENT);
0236 
0237 static const struct clk_hw *cpux_hws[] = { &cpux_clk.common.hw };
0238 static SUNXI_CCU_M_HWS(cpux_axi_clk, "cpux-axi",
0239                cpux_hws, 0x500, 0, 2, 0);
0240 static SUNXI_CCU_M_HWS(cpux_apb_clk, "cpux-apb",
0241                cpux_hws, 0x500, 8, 2, 0);
0242 
0243 static const struct clk_parent_data psi_ahb_parents[] = {
0244     { .fw_name = "hosc" },
0245     { .fw_name = "losc" },
0246     { .fw_name = "iosc" },
0247     { .hw = &pll_periph0_clk.hw },
0248 };
0249 static SUNXI_CCU_MP_DATA_WITH_MUX(psi_ahb_clk, "psi-ahb", psi_ahb_parents, 0x510,
0250                   0, 2,     /* M */
0251                   8, 2,     /* P */
0252                   24, 2,    /* mux */
0253                   0);
0254 
0255 static const struct clk_parent_data apb0_apb1_parents[] = {
0256     { .fw_name = "hosc" },
0257     { .fw_name = "losc" },
0258     { .hw = &psi_ahb_clk.common.hw },
0259     { .hw = &pll_periph0_clk.hw },
0260 };
0261 static SUNXI_CCU_MP_DATA_WITH_MUX(apb0_clk, "apb0", apb0_apb1_parents, 0x520,
0262                   0, 5,     /* M */
0263                   8, 2,     /* P */
0264                   24, 2,    /* mux */
0265                   0);
0266 
0267 static SUNXI_CCU_MP_DATA_WITH_MUX(apb1_clk, "apb1", apb0_apb1_parents, 0x524,
0268                   0, 5,     /* M */
0269                   8, 2,     /* P */
0270                   24, 2,    /* mux */
0271                   0);
0272 
0273 static const struct clk_hw *psi_ahb_hws[] = { &psi_ahb_clk.common.hw };
0274 static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw };
0275 static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };
0276 
0277 static const struct clk_hw *de_di_g2d_parents[] = {
0278     &pll_periph0_2x_clk.common.hw,
0279     &pll_video0_4x_clk.common.hw,
0280     &pll_video1_4x_clk.common.hw,
0281     &pll_audio1_div2_clk.common.hw,
0282 };
0283 static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_di_g2d_parents, 0x600,
0284                     0, 5,   /* M */
0285                     24, 3,  /* mux */
0286                     BIT(31),    /* gate */
0287                     CLK_SET_RATE_PARENT);
0288 
0289 static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", psi_ahb_hws,
0290               0x60c, BIT(0), 0);
0291 
0292 static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", de_di_g2d_parents, 0x620,
0293                     0, 5,   /* M */
0294                     24, 3,  /* mux */
0295                     BIT(31),    /* gate */
0296                     CLK_SET_RATE_PARENT);
0297 
0298 static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", psi_ahb_hws,
0299               0x62c, BIT(0), 0);
0300 
0301 static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", de_di_g2d_parents, 0x630,
0302                     0, 5,   /* M */
0303                     24, 3,  /* mux */
0304                     BIT(31),    /* gate */
0305                     0);
0306 
0307 static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", psi_ahb_hws,
0308               0x63c, BIT(0), 0);
0309 
0310 static const struct clk_parent_data ce_parents[] = {
0311     { .fw_name = "hosc" },
0312     { .hw = &pll_periph0_2x_clk.common.hw },
0313     { .hw = &pll_periph0_clk.hw },
0314 };
0315 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
0316                        0, 4,    /* M */
0317                        8, 2,    /* P */
0318                        24, 3,   /* mux */
0319                        BIT(31), /* gate */
0320                        0);
0321 
0322 static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", psi_ahb_hws,
0323               0x68c, BIT(0), 0);
0324 
0325 static const struct clk_hw *ve_parents[] = {
0326     &pll_ve_clk.common.hw,
0327     &pll_periph0_2x_clk.common.hw,
0328 };
0329 static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
0330                     0, 5,   /* M */
0331                     24, 1,  /* mux */
0332                     BIT(31),    /* gate */
0333                     CLK_SET_RATE_PARENT);
0334 
0335 static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", psi_ahb_hws,
0336               0x69c, BIT(0), 0);
0337 
0338 static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", psi_ahb_hws,
0339               0x70c, BIT(0), 0);
0340 
0341 static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", psi_ahb_hws,
0342               0x71c, BIT(0), 0);
0343 static SUNXI_CCU_GATE_HWS(bus_msgbox1_clk, "bus-msgbox1", psi_ahb_hws,
0344               0x71c, BIT(1), 0);
0345 static SUNXI_CCU_GATE_HWS(bus_msgbox2_clk, "bus-msgbox2", psi_ahb_hws,
0346               0x71c, BIT(2), 0);
0347 
0348 static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", psi_ahb_hws,
0349               0x72c, BIT(0), 0);
0350 
0351 static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", psi_ahb_hws,
0352               0x73c, BIT(0), 0);
0353 
0354 static SUNXI_CCU_GATE_DATA(avs_clk, "avs", osc24M,
0355                0x740, BIT(31), 0);
0356 
0357 static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", psi_ahb_hws,
0358               0x78c, BIT(0), 0);
0359 
0360 static SUNXI_CCU_GATE_HWS(bus_pwm_clk, "bus-pwm", apb0_hws,
0361               0x7ac, BIT(0), 0);
0362 
0363 static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws,
0364               0x7bc, BIT(0), 0);
0365 
0366 static const struct clk_hw *dram_parents[] = {
0367     &pll_ddr0_clk.common.hw,
0368     &pll_audio1_div2_clk.common.hw,
0369     &pll_periph0_2x_clk.common.hw,
0370     &pll_periph0_800M_clk.common.hw,
0371 };
0372 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x800,
0373                      0, 2,  /* M */
0374                      8, 2,  /* P */
0375                      24, 2, /* mux */
0376                      BIT(31), CLK_IS_CRITICAL);
0377 
0378 static CLK_FIXED_FACTOR_HW(mbus_clk, "mbus",
0379                &dram_clk.common.hw, 4, 1, 0);
0380 
0381 static const struct clk_hw *mbus_hws[] = { &mbus_clk.hw };
0382 
0383 static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
0384               0x804, BIT(0), 0);
0385 static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
0386               0x804, BIT(1), 0);
0387 static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
0388               0x804, BIT(2), 0);
0389 static SUNXI_CCU_GATE_HWS(mbus_tvin_clk, "mbus-tvin", mbus_hws,
0390               0x804, BIT(7), 0);
0391 static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
0392               0x804, BIT(8), 0);
0393 static SUNXI_CCU_GATE_HWS(mbus_g2d_clk, "mbus-g2d", mbus_hws,
0394               0x804, BIT(10), 0);
0395 static SUNXI_CCU_GATE_HWS(mbus_riscv_clk, "mbus-riscv", mbus_hws,
0396               0x804, BIT(11), 0);
0397 
0398 static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", psi_ahb_hws,
0399               0x80c, BIT(0), CLK_IS_CRITICAL);
0400 
0401 static const struct clk_parent_data mmc0_mmc1_parents[] = {
0402     { .fw_name = "hosc" },
0403     { .hw = &pll_periph0_clk.hw },
0404     { .hw = &pll_periph0_2x_clk.common.hw },
0405     { .hw = &pll_audio1_div2_clk.common.hw },
0406 };
0407 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
0408                        0, 4,    /* M */
0409                        8, 2,    /* P */
0410                        24, 3,   /* mux */
0411                        BIT(31), /* gate */
0412                        0);
0413 
0414 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
0415                        0, 4,    /* M */
0416                        8, 2,    /* P */
0417                        24, 3,   /* mux */
0418                        BIT(31), /* gate */
0419                        0);
0420 
0421 static const struct clk_parent_data mmc2_parents[] = {
0422     { .fw_name = "hosc" },
0423     { .hw = &pll_periph0_clk.hw },
0424     { .hw = &pll_periph0_2x_clk.common.hw },
0425     { .hw = &pll_periph0_800M_clk.common.hw },
0426     { .hw = &pll_audio1_div2_clk.common.hw },
0427 };
0428 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
0429                        0, 4,    /* M */
0430                        8, 2,    /* P */
0431                        24, 3,   /* mux */
0432                        BIT(31), /* gate */
0433                        0);
0434 
0435 static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", psi_ahb_hws,
0436               0x84c, BIT(0), 0);
0437 static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", psi_ahb_hws,
0438               0x84c, BIT(1), 0);
0439 static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", psi_ahb_hws,
0440               0x84c, BIT(2), 0);
0441 
0442 static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws,
0443               0x90c, BIT(0), 0);
0444 static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws,
0445               0x90c, BIT(1), 0);
0446 static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws,
0447               0x90c, BIT(2), 0);
0448 static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws,
0449               0x90c, BIT(3), 0);
0450 static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb1_hws,
0451               0x90c, BIT(4), 0);
0452 static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb1_hws,
0453               0x90c, BIT(5), 0);
0454 
0455 static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws,
0456               0x91c, BIT(0), 0);
0457 static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws,
0458               0x91c, BIT(1), 0);
0459 static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws,
0460               0x91c, BIT(2), 0);
0461 static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws,
0462               0x91c, BIT(3), 0);
0463 
0464 static const struct clk_parent_data spi_parents[] = {
0465     { .fw_name = "hosc" },
0466     { .hw = &pll_periph0_clk.hw },
0467     { .hw = &pll_periph0_2x_clk.common.hw },
0468     { .hw = &pll_audio1_div2_clk.common.hw },
0469     { .hw = &pll_audio1_div5_clk.common.hw },
0470 };
0471 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
0472                        0, 4,    /* M */
0473                        8, 2,    /* P */
0474                        24, 3,   /* mux */
0475                        BIT(31), /* gate */
0476                        0);
0477 
0478 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
0479                        0, 4,    /* M */
0480                        8, 2,    /* P */
0481                        24, 3,   /* mux */
0482                        BIT(31), /* gate */
0483                        0);
0484 
0485 static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", psi_ahb_hws,
0486               0x96c, BIT(0), 0);
0487 static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", psi_ahb_hws,
0488               0x96c, BIT(1), 0);
0489 
0490 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph0_hws,
0491                       0x970, BIT(31) | BIT(30), 24, 0);
0492 
0493 static SUNXI_CCU_GATE_HWS(bus_emac_clk, "bus-emac", psi_ahb_hws,
0494               0x97c, BIT(0), 0);
0495 
0496 static const struct clk_parent_data ir_tx_ledc_parents[] = {
0497     { .fw_name = "hosc" },
0498     { .hw = &pll_periph0_clk.hw },
0499 };
0500 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents, 0x9c0,
0501                        0, 4,    /* M */
0502                        8, 2,    /* P */
0503                        24, 3,   /* mux */
0504                        BIT(31), /* gate */
0505                        0);
0506 
0507 static SUNXI_CCU_GATE_HWS(bus_ir_tx_clk, "bus-ir-tx", apb0_hws,
0508               0x9cc, BIT(0), 0);
0509 
0510 static SUNXI_CCU_GATE_HWS(bus_gpadc_clk, "bus-gpadc", apb0_hws,
0511               0x9ec, BIT(0), 0);
0512 
0513 static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", apb0_hws,
0514               0x9fc, BIT(0), 0);
0515 
0516 static const struct clk_hw *i2s_spdif_tx_parents[] = {
0517     &pll_audio0_clk.hw,
0518     &pll_audio0_4x_clk.common.hw,
0519     &pll_audio1_div2_clk.common.hw,
0520     &pll_audio1_div5_clk.common.hw,
0521 };
0522 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s0_clk, "i2s0", i2s_spdif_tx_parents, 0xa10,
0523                      0, 5,  /* M */
0524                      8, 2,  /* P */
0525                      24, 3, /* mux */
0526                      BIT(31),   /* gate */
0527                      0);
0528 
0529 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s1_clk, "i2s1", i2s_spdif_tx_parents, 0xa14,
0530                      0, 5,  /* M */
0531                      8, 2,  /* P */
0532                      24, 3, /* mux */
0533                      BIT(31),   /* gate */
0534                      0);
0535 
0536 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_clk, "i2s2", i2s_spdif_tx_parents, 0xa18,
0537                      0, 5,  /* M */
0538                      8, 2,  /* P */
0539                      24, 3, /* mux */
0540                      BIT(31),   /* gate */
0541                      0);
0542 
0543 static const struct clk_hw *i2s2_asrc_parents[] = {
0544     &pll_audio0_4x_clk.common.hw,
0545     &pll_periph0_clk.hw,
0546     &pll_audio1_div2_clk.common.hw,
0547     &pll_audio1_div5_clk.common.hw,
0548 };
0549 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_asrc_clk, "i2s2-asrc", i2s2_asrc_parents, 0xa1c,
0550                      0, 5,  /* M */
0551                      8, 2,  /* P */
0552                      24, 3, /* mux */
0553                      BIT(31),   /* gate */
0554                      0);
0555 
0556 static SUNXI_CCU_GATE_HWS(bus_i2s0_clk, "bus-i2s0", apb0_hws,
0557               0xa20, BIT(0), 0);
0558 static SUNXI_CCU_GATE_HWS(bus_i2s1_clk, "bus-i2s1", apb0_hws,
0559               0xa20, BIT(1), 0);
0560 static SUNXI_CCU_GATE_HWS(bus_i2s2_clk, "bus-i2s2", apb0_hws,
0561               0xa20, BIT(2), 0);
0562 
0563 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_tx_clk, "spdif-tx", i2s_spdif_tx_parents, 0xa24,
0564                      0, 5,  /* M */
0565                      8, 2,  /* P */
0566                      24, 3, /* mux */
0567                      BIT(31),   /* gate */
0568                      0);
0569 
0570 static const struct clk_hw *spdif_rx_parents[] = {
0571     &pll_periph0_clk.hw,
0572     &pll_audio1_div2_clk.common.hw,
0573     &pll_audio1_div5_clk.common.hw,
0574 };
0575 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, 0xa28,
0576                      0, 5,  /* M */
0577                      8, 2,  /* P */
0578                      24, 3, /* mux */
0579                      BIT(31),   /* gate */
0580                      0);
0581 
0582 static SUNXI_CCU_GATE_HWS(bus_spdif_clk, "bus-spdif", apb0_hws,
0583               0xa2c, BIT(0), 0);
0584 
0585 static const struct clk_hw *dmic_codec_parents[] = {
0586     &pll_audio0_clk.hw,
0587     &pll_audio1_div2_clk.common.hw,
0588     &pll_audio1_div5_clk.common.hw,
0589 };
0590 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_codec_parents, 0xa40,
0591                      0, 5,  /* M */
0592                      8, 2,  /* P */
0593                      24, 3, /* mux */
0594                      BIT(31),   /* gate */
0595                      0);
0596 
0597 static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", apb0_hws,
0598               0xa4c, BIT(0), 0);
0599 
0600 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_dac_clk, "audio-dac", dmic_codec_parents, 0xa50,
0601                      0, 5,  /* M */
0602                      8, 2,  /* P */
0603                      24, 3, /* mux */
0604                      BIT(31),   /* gate */
0605                      0);
0606 
0607 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_adc_clk, "audio-adc", dmic_codec_parents, 0xa54,
0608                      0, 5,  /* M */
0609                      8, 2,  /* P */
0610                      24, 3, /* mux */
0611                      BIT(31),   /* gate */
0612                      0);
0613 
0614 static SUNXI_CCU_GATE_HWS(bus_audio_clk, "bus-audio", apb0_hws,
0615               0xa5c, BIT(0), 0);
0616 
0617 
0618 /*
0619  * The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is
0620  * a 2x multiplier from osc24M synchronized by pll-periph0, and is also used by
0621  * the OHCI module.
0622  */
0623 static const struct clk_parent_data usb_ohci_parents[] = {
0624     { .hw = &pll_periph0_clk.hw },
0625     { .fw_name = "hosc" },
0626     { .fw_name = "losc" },
0627 };
0628 static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] = {
0629     { .index = 0, .div = 50 },
0630     { .index = 1, .div = 2 },
0631 };
0632 
0633 static struct ccu_mux usb_ohci0_clk = {
0634     .enable     = BIT(31),
0635     .mux        = {
0636         .shift      = 24,
0637         .width      = 2,
0638         .fixed_predivs  = usb_ohci_predivs,
0639         .n_predivs  = ARRAY_SIZE(usb_ohci_predivs),
0640     },
0641     .common     = {
0642         .reg        = 0xa70,
0643         .features   = CCU_FEATURE_FIXED_PREDIV,
0644         .hw.init    = CLK_HW_INIT_PARENTS_DATA("usb-ohci0",
0645                                usb_ohci_parents,
0646                                &ccu_mux_ops,
0647                                0),
0648     },
0649 };
0650 
0651 static struct ccu_mux usb_ohci1_clk = {
0652     .enable     = BIT(31),
0653     .mux        = {
0654         .shift      = 24,
0655         .width      = 2,
0656         .fixed_predivs  = usb_ohci_predivs,
0657         .n_predivs  = ARRAY_SIZE(usb_ohci_predivs),
0658     },
0659     .common     = {
0660         .reg        = 0xa74,
0661         .features   = CCU_FEATURE_FIXED_PREDIV,
0662         .hw.init    = CLK_HW_INIT_PARENTS_DATA("usb-ohci1",
0663                                usb_ohci_parents,
0664                                &ccu_mux_ops,
0665                                0),
0666     },
0667 };
0668 
0669 static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", psi_ahb_hws,
0670               0xa8c, BIT(0), 0);
0671 static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", psi_ahb_hws,
0672               0xa8c, BIT(1), 0);
0673 static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", psi_ahb_hws,
0674               0xa8c, BIT(4), 0);
0675 static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", psi_ahb_hws,
0676               0xa8c, BIT(5), 0);
0677 static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", psi_ahb_hws,
0678               0xa8c, BIT(8), 0);
0679 
0680 static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws,
0681               0xa9c, BIT(0), 0);
0682 
0683 static SUNXI_CCU_GATE_HWS(bus_dpss_top_clk, "bus-dpss-top", psi_ahb_hws,
0684               0xabc, BIT(0), 0);
0685 
0686 static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M,
0687                0xb04, BIT(31), 0);
0688 
0689 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k",
0690                       pll_periph0_2x_hws,
0691                       0xb10, BIT(30), 36621, 0);
0692 
0693 static const struct clk_parent_data hdmi_cec_parents[] = {
0694     { .fw_name = "losc" },
0695     { .hw = &hdmi_cec_32k_clk.common.hw },
0696 };
0697 static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents, 0xb10,
0698                     24, 1,  /* mux */
0699                     BIT(31),    /* gate */
0700                     0);
0701 
0702 static SUNXI_CCU_GATE_HWS(bus_hdmi_clk, "bus-hdmi", psi_ahb_hws,
0703               0xb1c, BIT(0), 0);
0704 
0705 static const struct clk_parent_data mipi_dsi_parents[] = {
0706     { .fw_name = "hosc" },
0707     { .hw = &pll_periph0_clk.hw },
0708     { .hw = &pll_video0_2x_clk.hw },
0709     { .hw = &pll_video1_2x_clk.hw },
0710     { .hw = &pll_audio1_div2_clk.common.hw },
0711 };
0712 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 0xb24,
0713                       0, 4, /* M */
0714                       24, 3,    /* mux */
0715                       BIT(31),  /* gate */
0716                       CLK_SET_RATE_PARENT);
0717 
0718 static SUNXI_CCU_GATE_HWS(bus_mipi_dsi_clk, "bus-mipi-dsi", psi_ahb_hws,
0719               0xb4c, BIT(0), 0);
0720 
0721 static const struct clk_hw *tcon_tve_parents[] = {
0722     &pll_video0_clk.hw,
0723     &pll_video0_4x_clk.common.hw,
0724     &pll_video1_clk.hw,
0725     &pll_video1_4x_clk.common.hw,
0726     &pll_periph0_2x_clk.common.hw,
0727     &pll_audio1_div2_clk.common.hw,
0728 };
0729 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_tve_parents, 0xb60,
0730                      0, 4,  /* M */
0731                      8, 2,  /* P */
0732                      24, 3, /* mux */
0733                      BIT(31),   /* gate */
0734                      CLK_SET_RATE_PARENT);
0735 
0736 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", psi_ahb_hws,
0737               0xb7c, BIT(0), 0);
0738 
0739 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_tv_clk, "tcon-tv", tcon_tve_parents, 0xb80,
0740                      0, 4,  /* M */
0741                      8, 2,  /* P */
0742                      24, 3, /* mux */
0743                      BIT(31),   /* gate */
0744                      CLK_SET_RATE_PARENT);
0745 
0746 static SUNXI_CCU_GATE_HWS(bus_tcon_tv_clk, "bus-tcon-tv", psi_ahb_hws,
0747               0xb9c, BIT(0), 0);
0748 
0749 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tve_clk, "tve", tcon_tve_parents, 0xbb0,
0750                      0, 4,  /* M */
0751                      8, 2,  /* P */
0752                      24, 3, /* mux */
0753                      BIT(31),   /* gate */
0754                      0);
0755 
0756 static SUNXI_CCU_GATE_HWS(bus_tve_top_clk, "bus-tve-top", psi_ahb_hws,
0757               0xbbc, BIT(0), 0);
0758 static SUNXI_CCU_GATE_HWS(bus_tve_clk, "bus-tve", psi_ahb_hws,
0759               0xbbc, BIT(1), 0);
0760 
0761 static const struct clk_parent_data tvd_parents[] = {
0762     { .fw_name = "hosc" },
0763     { .hw = &pll_video0_clk.hw },
0764     { .hw = &pll_video1_clk.hw },
0765     { .hw = &pll_periph0_clk.hw },
0766 };
0767 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents, 0xbc0,
0768                       0, 5, /* M */
0769                       24, 3,    /* mux */
0770                       BIT(31),  /* gate */
0771                       0);
0772 
0773 static SUNXI_CCU_GATE_HWS(bus_tvd_top_clk, "bus-tvd-top", psi_ahb_hws,
0774               0xbdc, BIT(0), 0);
0775 static SUNXI_CCU_GATE_HWS(bus_tvd_clk, "bus-tvd", psi_ahb_hws,
0776               0xbdc, BIT(1), 0);
0777 
0778 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ir_tx_ledc_parents, 0xbf0,
0779                        0, 4,    /* M */
0780                        8, 2,    /* P */
0781                        24, 1,   /* mux */
0782                        BIT(31), /* gate */
0783                        0);
0784 
0785 static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", psi_ahb_hws,
0786               0xbfc, BIT(0), 0);
0787 
0788 static const struct clk_hw *csi_top_parents[] = {
0789     &pll_periph0_2x_clk.common.hw,
0790     &pll_video0_2x_clk.hw,
0791     &pll_video1_2x_clk.hw,
0792 };
0793 static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04,
0794                     0, 4,   /* M */
0795                     24, 3,  /* mux */
0796                     BIT(31),    /* gate */
0797                     0);
0798 
0799 static const struct clk_parent_data csi_mclk_parents[] = {
0800     { .fw_name = "hosc" },
0801     { .hw = &pll_periph0_clk.hw },
0802     { .hw = &pll_video0_clk.hw },
0803     { .hw = &pll_video1_clk.hw },
0804     { .hw = &pll_audio1_div2_clk.common.hw },
0805     { .hw = &pll_audio1_div5_clk.common.hw },
0806 };
0807 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0xc08,
0808                       0, 5, /* M */
0809                       24, 3,    /* mux */
0810                       BIT(31),  /* gate */
0811                       0);
0812 
0813 static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", psi_ahb_hws,
0814               0xc1c, BIT(0), 0);
0815 
0816 static const struct clk_parent_data tpadc_parents[] = {
0817     { .fw_name = "hosc" },
0818     { .hw = &pll_audio0_clk.hw },
0819 };
0820 static SUNXI_CCU_MUX_DATA_WITH_GATE(tpadc_clk, "tpadc", tpadc_parents, 0xc50,
0821                     24, 3,  /* mux */
0822                     BIT(31),    /* gate */
0823                     0);
0824 
0825 static SUNXI_CCU_GATE_HWS(bus_tpadc_clk, "bus-tpadc", apb0_hws,
0826               0xc5c, BIT(0), 0);
0827 
0828 static SUNXI_CCU_GATE_HWS(bus_tzma_clk, "bus-tzma", apb0_hws,
0829               0xc6c, BIT(0), 0);
0830 
0831 static const struct clk_parent_data dsp_parents[] = {
0832     { .fw_name = "hosc" },
0833     { .fw_name = "losc" },
0834     { .fw_name = "iosc" },
0835     { .hw = &pll_periph0_2x_clk.common.hw },
0836     { .hw = &pll_audio1_div2_clk.common.hw },
0837 };
0838 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "dsp", dsp_parents, 0xc70,
0839                       0, 5, /* M */
0840                       24, 3,    /* mux */
0841                       BIT(31),  /* gate */
0842                       0);
0843 
0844 static SUNXI_CCU_GATE_HWS(bus_dsp_cfg_clk, "bus-dsp-cfg", psi_ahb_hws,
0845               0xc7c, BIT(1), 0);
0846 
0847 /*
0848  * The RISC-V gate is not modelled - it is in a separate register (0xd04)
0849  * and has a special key field. The clock is critical anyway.
0850  */
0851 static const struct clk_parent_data riscv_parents[] = {
0852     { .fw_name = "hosc" },
0853     { .fw_name = "losc" },
0854     { .fw_name = "iosc" },
0855     { .hw = &pll_periph0_800M_clk.common.hw },
0856     { .hw = &pll_periph0_clk.hw },
0857     { .hw = &pll_cpux_clk.common.hw },
0858     { .hw = &pll_audio1_div2_clk.common.hw },
0859 };
0860 static SUNXI_CCU_M_DATA_WITH_MUX(riscv_clk, "riscv", riscv_parents, 0xd00,
0861                  0, 5,  /* M */
0862                  24, 3, /* mux */
0863                  CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
0864 
0865 /* The riscv-axi clk must be divided by at least 2. */
0866 static struct clk_div_table riscv_axi_table[] = {
0867     { .val = 1, .div = 2 },
0868     { .val = 2, .div = 3 },
0869     { .val = 3, .div = 4 },
0870     { /* Sentinel */ }
0871 };
0872 static SUNXI_CCU_DIV_TABLE_HW(riscv_axi_clk, "riscv-axi", &riscv_clk.common.hw,
0873                   0xd00, 8, 2, riscv_axi_table, 0);
0874 
0875 static SUNXI_CCU_GATE_HWS(bus_riscv_cfg_clk, "bus-riscv-cfg", psi_ahb_hws,
0876               0xd0c, BIT(0), CLK_IS_CRITICAL);
0877 
0878 static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
0879                0xf30, BIT(0), 0);
0880 static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
0881                        0xf30, BIT(1), 2, 0);
0882 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph0_2x_hws,
0883                       0xf30, BIT(2), 75, 0);
0884 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph0_hws,
0885                       0xf30, BIT(3), 24, 0);
0886 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_32k_clk, "fanout-32k", pll_periph0_2x_hws,
0887                       0xf30, BIT(4), 36621, 0);
0888 
0889 /* This clock has a second divider that is not modelled and forced to 0. */
0890 #define SUN20I_D1_FANOUT_27M_REG    0xf34
0891 static const struct clk_hw *fanout_27M_parents[] = {
0892     &pll_video0_clk.hw,
0893     &pll_video1_clk.hw,
0894 };
0895 static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0xf34,
0896                     0, 5,   /* M */
0897                     24, 2,  /* mux */
0898                     BIT(31),    /* gate */
0899                     0);
0900 
0901 static SUNXI_CCU_M_HWS_WITH_GATE(fanout_pclk_clk, "fanout-pclk", apb0_hws, 0xf38,
0902                  0, 5,      /* M */
0903                  BIT(31),   /* gate */
0904                  0);
0905 
0906 static const struct clk_hw *fanout_parents[] = {
0907     &fanout_32k_clk.common.hw,
0908     &fanout_12M_clk.common.hw,
0909     &fanout_16M_clk.common.hw,
0910     &fanout_24M_clk.common.hw,
0911     &fanout_25M_clk.common.hw,
0912     &fanout_27M_clk.common.hw,
0913     &fanout_pclk_clk.common.hw,
0914 };
0915 static SUNXI_CCU_MUX_HW_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0xf3c,
0916                   0, 3,     /* mux */
0917                   BIT(21),  /* gate */
0918                   0);
0919 static SUNXI_CCU_MUX_HW_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0xf3c,
0920                   3, 3,     /* mux */
0921                   BIT(22),  /* gate */
0922                   0);
0923 static SUNXI_CCU_MUX_HW_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0xf3c,
0924                   6, 3,     /* mux */
0925                   BIT(23),  /* gate */
0926                   0);
0927 
0928 static struct ccu_common *sun20i_d1_ccu_clks[] = {
0929     &pll_cpux_clk.common,
0930     &pll_ddr0_clk.common,
0931     &pll_periph0_4x_clk.common,
0932     &pll_periph0_2x_clk.common,
0933     &pll_periph0_800M_clk.common,
0934     &pll_video0_4x_clk.common,
0935     &pll_video1_4x_clk.common,
0936     &pll_ve_clk.common,
0937     &pll_audio0_4x_clk.common,
0938     &pll_audio1_clk.common,
0939     &pll_audio1_div2_clk.common,
0940     &pll_audio1_div5_clk.common,
0941     &cpux_clk.common,
0942     &cpux_axi_clk.common,
0943     &cpux_apb_clk.common,
0944     &psi_ahb_clk.common,
0945     &apb0_clk.common,
0946     &apb1_clk.common,
0947     &de_clk.common,
0948     &bus_de_clk.common,
0949     &di_clk.common,
0950     &bus_di_clk.common,
0951     &g2d_clk.common,
0952     &bus_g2d_clk.common,
0953     &ce_clk.common,
0954     &bus_ce_clk.common,
0955     &ve_clk.common,
0956     &bus_ve_clk.common,
0957     &bus_dma_clk.common,
0958     &bus_msgbox0_clk.common,
0959     &bus_msgbox1_clk.common,
0960     &bus_msgbox2_clk.common,
0961     &bus_spinlock_clk.common,
0962     &bus_hstimer_clk.common,
0963     &avs_clk.common,
0964     &bus_dbg_clk.common,
0965     &bus_pwm_clk.common,
0966     &bus_iommu_clk.common,
0967     &dram_clk.common,
0968     &mbus_dma_clk.common,
0969     &mbus_ve_clk.common,
0970     &mbus_ce_clk.common,
0971     &mbus_tvin_clk.common,
0972     &mbus_csi_clk.common,
0973     &mbus_g2d_clk.common,
0974     &mbus_riscv_clk.common,
0975     &bus_dram_clk.common,
0976     &mmc0_clk.common,
0977     &mmc1_clk.common,
0978     &mmc2_clk.common,
0979     &bus_mmc0_clk.common,
0980     &bus_mmc1_clk.common,
0981     &bus_mmc2_clk.common,
0982     &bus_uart0_clk.common,
0983     &bus_uart1_clk.common,
0984     &bus_uart2_clk.common,
0985     &bus_uart3_clk.common,
0986     &bus_uart4_clk.common,
0987     &bus_uart5_clk.common,
0988     &bus_i2c0_clk.common,
0989     &bus_i2c1_clk.common,
0990     &bus_i2c2_clk.common,
0991     &bus_i2c3_clk.common,
0992     &spi0_clk.common,
0993     &spi1_clk.common,
0994     &bus_spi0_clk.common,
0995     &bus_spi1_clk.common,
0996     &emac_25M_clk.common,
0997     &bus_emac_clk.common,
0998     &ir_tx_clk.common,
0999     &bus_ir_tx_clk.common,
1000     &bus_gpadc_clk.common,
1001     &bus_ths_clk.common,
1002     &i2s0_clk.common,
1003     &i2s1_clk.common,
1004     &i2s2_clk.common,
1005     &i2s2_asrc_clk.common,
1006     &bus_i2s0_clk.common,
1007     &bus_i2s1_clk.common,
1008     &bus_i2s2_clk.common,
1009     &spdif_tx_clk.common,
1010     &spdif_rx_clk.common,
1011     &bus_spdif_clk.common,
1012     &dmic_clk.common,
1013     &bus_dmic_clk.common,
1014     &audio_dac_clk.common,
1015     &audio_adc_clk.common,
1016     &bus_audio_clk.common,
1017     &usb_ohci0_clk.common,
1018     &usb_ohci1_clk.common,
1019     &bus_ohci0_clk.common,
1020     &bus_ohci1_clk.common,
1021     &bus_ehci0_clk.common,
1022     &bus_ehci1_clk.common,
1023     &bus_otg_clk.common,
1024     &bus_lradc_clk.common,
1025     &bus_dpss_top_clk.common,
1026     &hdmi_24M_clk.common,
1027     &hdmi_cec_32k_clk.common,
1028     &hdmi_cec_clk.common,
1029     &bus_hdmi_clk.common,
1030     &mipi_dsi_clk.common,
1031     &bus_mipi_dsi_clk.common,
1032     &tcon_lcd0_clk.common,
1033     &bus_tcon_lcd0_clk.common,
1034     &tcon_tv_clk.common,
1035     &bus_tcon_tv_clk.common,
1036     &tve_clk.common,
1037     &bus_tve_top_clk.common,
1038     &bus_tve_clk.common,
1039     &tvd_clk.common,
1040     &bus_tvd_top_clk.common,
1041     &bus_tvd_clk.common,
1042     &ledc_clk.common,
1043     &bus_ledc_clk.common,
1044     &csi_top_clk.common,
1045     &csi_mclk_clk.common,
1046     &bus_csi_clk.common,
1047     &tpadc_clk.common,
1048     &bus_tpadc_clk.common,
1049     &bus_tzma_clk.common,
1050     &dsp_clk.common,
1051     &bus_dsp_cfg_clk.common,
1052     &riscv_clk.common,
1053     &riscv_axi_clk.common,
1054     &bus_riscv_cfg_clk.common,
1055     &fanout_24M_clk.common,
1056     &fanout_12M_clk.common,
1057     &fanout_16M_clk.common,
1058     &fanout_25M_clk.common,
1059     &fanout_32k_clk.common,
1060     &fanout_27M_clk.common,
1061     &fanout_pclk_clk.common,
1062     &fanout0_clk.common,
1063     &fanout1_clk.common,
1064     &fanout2_clk.common,
1065 };
1066 
1067 static struct clk_hw_onecell_data sun20i_d1_hw_clks = {
1068     .num    = CLK_NUMBER,
1069     .hws    = {
1070         [CLK_PLL_CPUX]      = &pll_cpux_clk.common.hw,
1071         [CLK_PLL_DDR0]      = &pll_ddr0_clk.common.hw,
1072         [CLK_PLL_PERIPH0_4X]    = &pll_periph0_4x_clk.common.hw,
1073         [CLK_PLL_PERIPH0_2X]    = &pll_periph0_2x_clk.common.hw,
1074         [CLK_PLL_PERIPH0_800M]  = &pll_periph0_800M_clk.common.hw,
1075         [CLK_PLL_PERIPH0]   = &pll_periph0_clk.hw,
1076         [CLK_PLL_PERIPH0_DIV3]  = &pll_periph0_div3_clk.hw,
1077         [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.common.hw,
1078         [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
1079         [CLK_PLL_VIDEO0]    = &pll_video0_clk.hw,
1080         [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.common.hw,
1081         [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
1082         [CLK_PLL_VIDEO1]    = &pll_video1_clk.hw,
1083         [CLK_PLL_VE]        = &pll_ve_clk.common.hw,
1084         [CLK_PLL_AUDIO0_4X] = &pll_audio0_4x_clk.common.hw,
1085         [CLK_PLL_AUDIO0_2X] = &pll_audio0_2x_clk.hw,
1086         [CLK_PLL_AUDIO0]    = &pll_audio0_clk.hw,
1087         [CLK_PLL_AUDIO1]    = &pll_audio1_clk.common.hw,
1088         [CLK_PLL_AUDIO1_DIV2]   = &pll_audio1_div2_clk.common.hw,
1089         [CLK_PLL_AUDIO1_DIV5]   = &pll_audio1_div5_clk.common.hw,
1090         [CLK_CPUX]      = &cpux_clk.common.hw,
1091         [CLK_CPUX_AXI]      = &cpux_axi_clk.common.hw,
1092         [CLK_CPUX_APB]      = &cpux_apb_clk.common.hw,
1093         [CLK_PSI_AHB]       = &psi_ahb_clk.common.hw,
1094         [CLK_APB0]      = &apb0_clk.common.hw,
1095         [CLK_APB1]      = &apb1_clk.common.hw,
1096         [CLK_MBUS]      = &mbus_clk.hw,
1097         [CLK_DE]        = &de_clk.common.hw,
1098         [CLK_BUS_DE]        = &bus_de_clk.common.hw,
1099         [CLK_DI]        = &di_clk.common.hw,
1100         [CLK_BUS_DI]        = &bus_di_clk.common.hw,
1101         [CLK_G2D]       = &g2d_clk.common.hw,
1102         [CLK_BUS_G2D]       = &bus_g2d_clk.common.hw,
1103         [CLK_CE]        = &ce_clk.common.hw,
1104         [CLK_BUS_CE]        = &bus_ce_clk.common.hw,
1105         [CLK_VE]        = &ve_clk.common.hw,
1106         [CLK_BUS_VE]        = &bus_ve_clk.common.hw,
1107         [CLK_BUS_DMA]       = &bus_dma_clk.common.hw,
1108         [CLK_BUS_MSGBOX0]   = &bus_msgbox0_clk.common.hw,
1109         [CLK_BUS_MSGBOX1]   = &bus_msgbox1_clk.common.hw,
1110         [CLK_BUS_MSGBOX2]   = &bus_msgbox2_clk.common.hw,
1111         [CLK_BUS_SPINLOCK]  = &bus_spinlock_clk.common.hw,
1112         [CLK_BUS_HSTIMER]   = &bus_hstimer_clk.common.hw,
1113         [CLK_AVS]       = &avs_clk.common.hw,
1114         [CLK_BUS_DBG]       = &bus_dbg_clk.common.hw,
1115         [CLK_BUS_PWM]       = &bus_pwm_clk.common.hw,
1116         [CLK_BUS_IOMMU]     = &bus_iommu_clk.common.hw,
1117         [CLK_DRAM]      = &dram_clk.common.hw,
1118         [CLK_MBUS_DMA]      = &mbus_dma_clk.common.hw,
1119         [CLK_MBUS_VE]       = &mbus_ve_clk.common.hw,
1120         [CLK_MBUS_CE]       = &mbus_ce_clk.common.hw,
1121         [CLK_MBUS_TVIN]     = &mbus_tvin_clk.common.hw,
1122         [CLK_MBUS_CSI]      = &mbus_csi_clk.common.hw,
1123         [CLK_MBUS_G2D]      = &mbus_g2d_clk.common.hw,
1124         [CLK_MBUS_RISCV]    = &mbus_riscv_clk.common.hw,
1125         [CLK_BUS_DRAM]      = &bus_dram_clk.common.hw,
1126         [CLK_MMC0]      = &mmc0_clk.common.hw,
1127         [CLK_MMC1]      = &mmc1_clk.common.hw,
1128         [CLK_MMC2]      = &mmc2_clk.common.hw,
1129         [CLK_BUS_MMC0]      = &bus_mmc0_clk.common.hw,
1130         [CLK_BUS_MMC1]      = &bus_mmc1_clk.common.hw,
1131         [CLK_BUS_MMC2]      = &bus_mmc2_clk.common.hw,
1132         [CLK_BUS_UART0]     = &bus_uart0_clk.common.hw,
1133         [CLK_BUS_UART1]     = &bus_uart1_clk.common.hw,
1134         [CLK_BUS_UART2]     = &bus_uart2_clk.common.hw,
1135         [CLK_BUS_UART3]     = &bus_uart3_clk.common.hw,
1136         [CLK_BUS_UART4]     = &bus_uart4_clk.common.hw,
1137         [CLK_BUS_UART5]     = &bus_uart5_clk.common.hw,
1138         [CLK_BUS_I2C0]      = &bus_i2c0_clk.common.hw,
1139         [CLK_BUS_I2C1]      = &bus_i2c1_clk.common.hw,
1140         [CLK_BUS_I2C2]      = &bus_i2c2_clk.common.hw,
1141         [CLK_BUS_I2C3]      = &bus_i2c3_clk.common.hw,
1142         [CLK_SPI0]      = &spi0_clk.common.hw,
1143         [CLK_SPI1]      = &spi1_clk.common.hw,
1144         [CLK_BUS_SPI0]      = &bus_spi0_clk.common.hw,
1145         [CLK_BUS_SPI1]      = &bus_spi1_clk.common.hw,
1146         [CLK_EMAC_25M]      = &emac_25M_clk.common.hw,
1147         [CLK_BUS_EMAC]      = &bus_emac_clk.common.hw,
1148         [CLK_IR_TX]     = &ir_tx_clk.common.hw,
1149         [CLK_BUS_IR_TX]     = &bus_ir_tx_clk.common.hw,
1150         [CLK_BUS_GPADC]     = &bus_gpadc_clk.common.hw,
1151         [CLK_BUS_THS]       = &bus_ths_clk.common.hw,
1152         [CLK_I2S0]      = &i2s0_clk.common.hw,
1153         [CLK_I2S1]      = &i2s1_clk.common.hw,
1154         [CLK_I2S2]      = &i2s2_clk.common.hw,
1155         [CLK_I2S2_ASRC]     = &i2s2_asrc_clk.common.hw,
1156         [CLK_BUS_I2S0]      = &bus_i2s0_clk.common.hw,
1157         [CLK_BUS_I2S1]      = &bus_i2s1_clk.common.hw,
1158         [CLK_BUS_I2S2]      = &bus_i2s2_clk.common.hw,
1159         [CLK_SPDIF_TX]      = &spdif_tx_clk.common.hw,
1160         [CLK_SPDIF_RX]      = &spdif_rx_clk.common.hw,
1161         [CLK_BUS_SPDIF]     = &bus_spdif_clk.common.hw,
1162         [CLK_DMIC]      = &dmic_clk.common.hw,
1163         [CLK_BUS_DMIC]      = &bus_dmic_clk.common.hw,
1164         [CLK_AUDIO_DAC]     = &audio_dac_clk.common.hw,
1165         [CLK_AUDIO_ADC]     = &audio_adc_clk.common.hw,
1166         [CLK_BUS_AUDIO]     = &bus_audio_clk.common.hw,
1167         [CLK_USB_OHCI0]     = &usb_ohci0_clk.common.hw,
1168         [CLK_USB_OHCI1]     = &usb_ohci1_clk.common.hw,
1169         [CLK_BUS_OHCI0]     = &bus_ohci0_clk.common.hw,
1170         [CLK_BUS_OHCI1]     = &bus_ohci1_clk.common.hw,
1171         [CLK_BUS_EHCI0]     = &bus_ehci0_clk.common.hw,
1172         [CLK_BUS_EHCI1]     = &bus_ehci1_clk.common.hw,
1173         [CLK_BUS_OTG]       = &bus_otg_clk.common.hw,
1174         [CLK_BUS_LRADC]     = &bus_lradc_clk.common.hw,
1175         [CLK_BUS_DPSS_TOP]  = &bus_dpss_top_clk.common.hw,
1176         [CLK_HDMI_24M]      = &hdmi_24M_clk.common.hw,
1177         [CLK_HDMI_CEC_32K]  = &hdmi_cec_32k_clk.common.hw,
1178         [CLK_HDMI_CEC]      = &hdmi_cec_clk.common.hw,
1179         [CLK_BUS_HDMI]      = &bus_hdmi_clk.common.hw,
1180         [CLK_MIPI_DSI]      = &mipi_dsi_clk.common.hw,
1181         [CLK_BUS_MIPI_DSI]  = &bus_mipi_dsi_clk.common.hw,
1182         [CLK_TCON_LCD0]     = &tcon_lcd0_clk.common.hw,
1183         [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
1184         [CLK_TCON_TV]       = &tcon_tv_clk.common.hw,
1185         [CLK_BUS_TCON_TV]   = &bus_tcon_tv_clk.common.hw,
1186         [CLK_TVE]       = &tve_clk.common.hw,
1187         [CLK_BUS_TVE_TOP]   = &bus_tve_top_clk.common.hw,
1188         [CLK_BUS_TVE]       = &bus_tve_clk.common.hw,
1189         [CLK_TVD]       = &tvd_clk.common.hw,
1190         [CLK_BUS_TVD_TOP]   = &bus_tvd_top_clk.common.hw,
1191         [CLK_BUS_TVD]       = &bus_tvd_clk.common.hw,
1192         [CLK_LEDC]      = &ledc_clk.common.hw,
1193         [CLK_BUS_LEDC]      = &bus_ledc_clk.common.hw,
1194         [CLK_CSI_TOP]       = &csi_top_clk.common.hw,
1195         [CLK_CSI_MCLK]      = &csi_mclk_clk.common.hw,
1196         [CLK_BUS_CSI]       = &bus_csi_clk.common.hw,
1197         [CLK_TPADC]     = &tpadc_clk.common.hw,
1198         [CLK_BUS_TPADC]     = &bus_tpadc_clk.common.hw,
1199         [CLK_BUS_TZMA]      = &bus_tzma_clk.common.hw,
1200         [CLK_DSP]       = &dsp_clk.common.hw,
1201         [CLK_BUS_DSP_CFG]   = &bus_dsp_cfg_clk.common.hw,
1202         [CLK_RISCV]     = &riscv_clk.common.hw,
1203         [CLK_RISCV_AXI]     = &riscv_axi_clk.common.hw,
1204         [CLK_BUS_RISCV_CFG] = &bus_riscv_cfg_clk.common.hw,
1205         [CLK_FANOUT_24M]    = &fanout_24M_clk.common.hw,
1206         [CLK_FANOUT_12M]    = &fanout_12M_clk.common.hw,
1207         [CLK_FANOUT_16M]    = &fanout_16M_clk.common.hw,
1208         [CLK_FANOUT_25M]    = &fanout_25M_clk.common.hw,
1209         [CLK_FANOUT_32K]    = &fanout_32k_clk.common.hw,
1210         [CLK_FANOUT_27M]    = &fanout_27M_clk.common.hw,
1211         [CLK_FANOUT_PCLK]   = &fanout_pclk_clk.common.hw,
1212         [CLK_FANOUT0]       = &fanout0_clk.common.hw,
1213         [CLK_FANOUT1]       = &fanout1_clk.common.hw,
1214         [CLK_FANOUT2]       = &fanout2_clk.common.hw,
1215     },
1216 };
1217 
1218 static struct ccu_reset_map sun20i_d1_ccu_resets[] = {
1219     [RST_MBUS]      = { 0x540, BIT(30) },
1220     [RST_BUS_DE]        = { 0x60c, BIT(16) },
1221     [RST_BUS_DI]        = { 0x62c, BIT(16) },
1222     [RST_BUS_G2D]       = { 0x63c, BIT(16) },
1223     [RST_BUS_CE]        = { 0x68c, BIT(16) },
1224     [RST_BUS_VE]        = { 0x69c, BIT(16) },
1225     [RST_BUS_DMA]       = { 0x70c, BIT(16) },
1226     [RST_BUS_MSGBOX0]   = { 0x71c, BIT(16) },
1227     [RST_BUS_MSGBOX1]   = { 0x71c, BIT(17) },
1228     [RST_BUS_MSGBOX2]   = { 0x71c, BIT(18) },
1229     [RST_BUS_SPINLOCK]  = { 0x72c, BIT(16) },
1230     [RST_BUS_HSTIMER]   = { 0x73c, BIT(16) },
1231     [RST_BUS_DBG]       = { 0x78c, BIT(16) },
1232     [RST_BUS_PWM]       = { 0x7ac, BIT(16) },
1233     [RST_BUS_DRAM]      = { 0x80c, BIT(16) },
1234     [RST_BUS_MMC0]      = { 0x84c, BIT(16) },
1235     [RST_BUS_MMC1]      = { 0x84c, BIT(17) },
1236     [RST_BUS_MMC2]      = { 0x84c, BIT(18) },
1237     [RST_BUS_UART0]     = { 0x90c, BIT(16) },
1238     [RST_BUS_UART1]     = { 0x90c, BIT(17) },
1239     [RST_BUS_UART2]     = { 0x90c, BIT(18) },
1240     [RST_BUS_UART3]     = { 0x90c, BIT(19) },
1241     [RST_BUS_UART4]     = { 0x90c, BIT(20) },
1242     [RST_BUS_UART5]     = { 0x90c, BIT(21) },
1243     [RST_BUS_I2C0]      = { 0x91c, BIT(16) },
1244     [RST_BUS_I2C1]      = { 0x91c, BIT(17) },
1245     [RST_BUS_I2C2]      = { 0x91c, BIT(18) },
1246     [RST_BUS_I2C3]      = { 0x91c, BIT(19) },
1247     [RST_BUS_SPI0]      = { 0x96c, BIT(16) },
1248     [RST_BUS_SPI1]      = { 0x96c, BIT(17) },
1249     [RST_BUS_EMAC]      = { 0x97c, BIT(16) },
1250     [RST_BUS_IR_TX]     = { 0x9cc, BIT(16) },
1251     [RST_BUS_GPADC]     = { 0x9ec, BIT(16) },
1252     [RST_BUS_THS]       = { 0x9fc, BIT(16) },
1253     [RST_BUS_I2S0]      = { 0xa20, BIT(16) },
1254     [RST_BUS_I2S1]      = { 0xa20, BIT(17) },
1255     [RST_BUS_I2S2]      = { 0xa20, BIT(18) },
1256     [RST_BUS_SPDIF]     = { 0xa2c, BIT(16) },
1257     [RST_BUS_DMIC]      = { 0xa4c, BIT(16) },
1258     [RST_BUS_AUDIO]     = { 0xa5c, BIT(16) },
1259     [RST_USB_PHY0]      = { 0xa70, BIT(30) },
1260     [RST_USB_PHY1]      = { 0xa74, BIT(30) },
1261     [RST_BUS_OHCI0]     = { 0xa8c, BIT(16) },
1262     [RST_BUS_OHCI1]     = { 0xa8c, BIT(17) },
1263     [RST_BUS_EHCI0]     = { 0xa8c, BIT(20) },
1264     [RST_BUS_EHCI1]     = { 0xa8c, BIT(21) },
1265     [RST_BUS_OTG]       = { 0xa8c, BIT(24) },
1266     [RST_BUS_LRADC]     = { 0xa9c, BIT(16) },
1267     [RST_BUS_DPSS_TOP]  = { 0xabc, BIT(16) },
1268     [RST_BUS_HDMI_MAIN] = { 0xb1c, BIT(16) },
1269     [RST_BUS_HDMI_SUB]  = { 0xb1c, BIT(17) },
1270     [RST_BUS_MIPI_DSI]  = { 0xb4c, BIT(16) },
1271     [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1272     [RST_BUS_TCON_TV]   = { 0xb9c, BIT(16) },
1273     [RST_BUS_LVDS0]     = { 0xbac, BIT(16) },
1274     [RST_BUS_TVE_TOP]   = { 0xbbc, BIT(16) },
1275     [RST_BUS_TVE]       = { 0xbbc, BIT(17) },
1276     [RST_BUS_TVD_TOP]   = { 0xbdc, BIT(16) },
1277     [RST_BUS_TVD]       = { 0xbdc, BIT(17) },
1278     [RST_BUS_LEDC]      = { 0xbfc, BIT(16) },
1279     [RST_BUS_CSI]       = { 0xc1c, BIT(16) },
1280     [RST_BUS_TPADC]     = { 0xc5c, BIT(16) },
1281     [RST_DSP]       = { 0xc7c, BIT(16) },
1282     [RST_BUS_DSP_CFG]   = { 0xc7c, BIT(17) },
1283     [RST_BUS_DSP_DBG]   = { 0xc7c, BIT(18) },
1284     [RST_BUS_RISCV_CFG] = { 0xd0c, BIT(16) },
1285 };
1286 
1287 static const struct sunxi_ccu_desc sun20i_d1_ccu_desc = {
1288     .ccu_clks   = sun20i_d1_ccu_clks,
1289     .num_ccu_clks   = ARRAY_SIZE(sun20i_d1_ccu_clks),
1290 
1291     .hw_clks    = &sun20i_d1_hw_clks,
1292 
1293     .resets     = sun20i_d1_ccu_resets,
1294     .num_resets = ARRAY_SIZE(sun20i_d1_ccu_resets),
1295 };
1296 
1297 static const u32 pll_regs[] = {
1298     SUN20I_D1_PLL_CPUX_REG,
1299     SUN20I_D1_PLL_DDR0_REG,
1300     SUN20I_D1_PLL_PERIPH0_REG,
1301     SUN20I_D1_PLL_VIDEO0_REG,
1302     SUN20I_D1_PLL_VIDEO1_REG,
1303     SUN20I_D1_PLL_VE_REG,
1304     SUN20I_D1_PLL_AUDIO0_REG,
1305     SUN20I_D1_PLL_AUDIO1_REG,
1306 };
1307 
1308 static const u32 pll_video_regs[] = {
1309     SUN20I_D1_PLL_VIDEO0_REG,
1310     SUN20I_D1_PLL_VIDEO1_REG,
1311 };
1312 
1313 static struct ccu_mux_nb sun20i_d1_riscv_nb = {
1314     .common     = &riscv_clk.common,
1315     .cm     = &riscv_clk.mux,
1316     .delay_us       = 1,
1317     .bypass_index   = 4, /* index of pll-periph0 */
1318 };
1319 
1320 static int sun20i_d1_ccu_probe(struct platform_device *pdev)
1321 {
1322     void __iomem *reg;
1323     u32 val;
1324     int i, ret;
1325 
1326     reg = devm_platform_ioremap_resource(pdev, 0);
1327     if (IS_ERR(reg))
1328         return PTR_ERR(reg);
1329 
1330     /* Enable the enable, LDO, and lock bits on all PLLs. */
1331     for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
1332         val = readl(reg + pll_regs[i]);
1333         val |= BIT(31) | BIT(30) | BIT(29);
1334         writel(val, reg + pll_regs[i]);
1335     }
1336 
1337     /* Force PLL_CPUX factor M to 0. */
1338     val = readl(reg + SUN20I_D1_PLL_CPUX_REG);
1339     val &= ~GENMASK(1, 0);
1340     writel(val, reg + SUN20I_D1_PLL_CPUX_REG);
1341 
1342     /*
1343      * Force the output divider of video PLLs to 0.
1344      *
1345      * See the comment before pll-video0 definition for the reason.
1346      */
1347     for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
1348         val = readl(reg + pll_video_regs[i]);
1349         val &= ~BIT(0);
1350         writel(val, reg + pll_video_regs[i]);
1351     }
1352 
1353     /* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */
1354     val = readl(reg + SUN20I_D1_PLL_AUDIO0_REG);
1355     val &= ~BIT(1) | BIT(0);
1356     writel(val, reg + SUN20I_D1_PLL_AUDIO0_REG);
1357 
1358     /* Force fanout-27M factor N to 0. */
1359     val = readl(reg + SUN20I_D1_FANOUT_27M_REG);
1360     val &= ~GENMASK(9, 8);
1361     writel(val, reg + SUN20I_D1_FANOUT_27M_REG);
1362 
1363     ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun20i_d1_ccu_desc);
1364     if (ret)
1365         return ret;
1366 
1367     /* Reparent CPU during PLL CPUX rate changes */
1368     ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
1369                   &sun20i_d1_riscv_nb);
1370 
1371     return 0;
1372 }
1373 
1374 static const struct of_device_id sun20i_d1_ccu_ids[] = {
1375     { .compatible = "allwinner,sun20i-d1-ccu" },
1376     { }
1377 };
1378 
1379 static struct platform_driver sun20i_d1_ccu_driver = {
1380     .probe  = sun20i_d1_ccu_probe,
1381     .driver = {
1382         .name           = "sun20i-d1-ccu",
1383         .suppress_bind_attrs    = true,
1384         .of_match_table     = sun20i_d1_ccu_ids,
1385     },
1386 };
1387 module_platform_driver(sun20i_d1_ccu_driver);
1388 
1389 MODULE_IMPORT_NS(SUNXI_CCU);
1390 MODULE_LICENSE("GPL");
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