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0007 #include <linux/clk.h>
0008 #include <linux/module.h>
0009 #include <linux/of_address.h>
0010 #include <linux/platform_device.h>
0011 #include <dt-bindings/clock/stm32mp13-clks.h>
0012 #include "clk-stm32-core.h"
0013 #include "stm32mp13_rcc.h"
0014
0015 #define RCC_CLR_OFFSET 0x4
0016
0017
0018 enum enum_gate_cfg {
0019 GATE_MCO1,
0020 GATE_MCO2,
0021 GATE_DBGCK,
0022 GATE_TRACECK,
0023 GATE_DDRC1,
0024 GATE_DDRC1LP,
0025 GATE_DDRPHYC,
0026 GATE_DDRPHYCLP,
0027 GATE_DDRCAPB,
0028 GATE_DDRCAPBLP,
0029 GATE_AXIDCG,
0030 GATE_DDRPHYCAPB,
0031 GATE_DDRPHYCAPBLP,
0032 GATE_TIM2,
0033 GATE_TIM3,
0034 GATE_TIM4,
0035 GATE_TIM5,
0036 GATE_TIM6,
0037 GATE_TIM7,
0038 GATE_LPTIM1,
0039 GATE_SPI2,
0040 GATE_SPI3,
0041 GATE_USART3,
0042 GATE_UART4,
0043 GATE_UART5,
0044 GATE_UART7,
0045 GATE_UART8,
0046 GATE_I2C1,
0047 GATE_I2C2,
0048 GATE_SPDIF,
0049 GATE_TIM1,
0050 GATE_TIM8,
0051 GATE_SPI1,
0052 GATE_USART6,
0053 GATE_SAI1,
0054 GATE_SAI2,
0055 GATE_DFSDM,
0056 GATE_ADFSDM,
0057 GATE_FDCAN,
0058 GATE_LPTIM2,
0059 GATE_LPTIM3,
0060 GATE_LPTIM4,
0061 GATE_LPTIM5,
0062 GATE_VREF,
0063 GATE_DTS,
0064 GATE_PMBCTRL,
0065 GATE_HDP,
0066 GATE_SYSCFG,
0067 GATE_DCMIPP,
0068 GATE_DDRPERFM,
0069 GATE_IWDG2APB,
0070 GATE_USBPHY,
0071 GATE_STGENRO,
0072 GATE_LTDC,
0073 GATE_RTCAPB,
0074 GATE_TZC,
0075 GATE_ETZPC,
0076 GATE_IWDG1APB,
0077 GATE_BSEC,
0078 GATE_STGENC,
0079 GATE_USART1,
0080 GATE_USART2,
0081 GATE_SPI4,
0082 GATE_SPI5,
0083 GATE_I2C3,
0084 GATE_I2C4,
0085 GATE_I2C5,
0086 GATE_TIM12,
0087 GATE_TIM13,
0088 GATE_TIM14,
0089 GATE_TIM15,
0090 GATE_TIM16,
0091 GATE_TIM17,
0092 GATE_DMA1,
0093 GATE_DMA2,
0094 GATE_DMAMUX1,
0095 GATE_DMA3,
0096 GATE_DMAMUX2,
0097 GATE_ADC1,
0098 GATE_ADC2,
0099 GATE_USBO,
0100 GATE_TSC,
0101 GATE_GPIOA,
0102 GATE_GPIOB,
0103 GATE_GPIOC,
0104 GATE_GPIOD,
0105 GATE_GPIOE,
0106 GATE_GPIOF,
0107 GATE_GPIOG,
0108 GATE_GPIOH,
0109 GATE_GPIOI,
0110 GATE_PKA,
0111 GATE_SAES,
0112 GATE_CRYP1,
0113 GATE_HASH1,
0114 GATE_RNG1,
0115 GATE_BKPSRAM,
0116 GATE_AXIMC,
0117 GATE_MCE,
0118 GATE_ETH1CK,
0119 GATE_ETH1TX,
0120 GATE_ETH1RX,
0121 GATE_ETH1MAC,
0122 GATE_FMC,
0123 GATE_QSPI,
0124 GATE_SDMMC1,
0125 GATE_SDMMC2,
0126 GATE_CRC1,
0127 GATE_USBH,
0128 GATE_ETH2CK,
0129 GATE_ETH2TX,
0130 GATE_ETH2RX,
0131 GATE_ETH2MAC,
0132 GATE_ETH1STP,
0133 GATE_ETH2STP,
0134 GATE_MDMA,
0135 GATE_NB
0136 };
0137
0138 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\
0139 [(_id)] = {\
0140 .offset = (_offset),\
0141 .bit_idx = (_bit_idx),\
0142 .set_clr = (_offset_clr),\
0143 }
0144
0145 #define CFG_GATE(_id, _offset, _bit_idx)\
0146 _CFG_GATE(_id, _offset, _bit_idx, 0)
0147
0148 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\
0149 _CFG_GATE(_id, _offset, _bit_idx, RCC_CLR_OFFSET)
0150
0151 static struct stm32_gate_cfg stm32mp13_gates[] = {
0152 CFG_GATE(GATE_MCO1, RCC_MCO1CFGR, 12),
0153 CFG_GATE(GATE_MCO2, RCC_MCO2CFGR, 12),
0154 CFG_GATE(GATE_DBGCK, RCC_DBGCFGR, 8),
0155 CFG_GATE(GATE_TRACECK, RCC_DBGCFGR, 9),
0156 CFG_GATE(GATE_DDRC1, RCC_DDRITFCR, 0),
0157 CFG_GATE(GATE_DDRC1LP, RCC_DDRITFCR, 1),
0158 CFG_GATE(GATE_DDRPHYC, RCC_DDRITFCR, 4),
0159 CFG_GATE(GATE_DDRPHYCLP, RCC_DDRITFCR, 5),
0160 CFG_GATE(GATE_DDRCAPB, RCC_DDRITFCR, 6),
0161 CFG_GATE(GATE_DDRCAPBLP, RCC_DDRITFCR, 7),
0162 CFG_GATE(GATE_AXIDCG, RCC_DDRITFCR, 8),
0163 CFG_GATE(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9),
0164 CFG_GATE(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10),
0165 CFG_GATE_SETCLR(GATE_TIM2, RCC_MP_APB1ENSETR, 0),
0166 CFG_GATE_SETCLR(GATE_TIM3, RCC_MP_APB1ENSETR, 1),
0167 CFG_GATE_SETCLR(GATE_TIM4, RCC_MP_APB1ENSETR, 2),
0168 CFG_GATE_SETCLR(GATE_TIM5, RCC_MP_APB1ENSETR, 3),
0169 CFG_GATE_SETCLR(GATE_TIM6, RCC_MP_APB1ENSETR, 4),
0170 CFG_GATE_SETCLR(GATE_TIM7, RCC_MP_APB1ENSETR, 5),
0171 CFG_GATE_SETCLR(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9),
0172 CFG_GATE_SETCLR(GATE_SPI2, RCC_MP_APB1ENSETR, 11),
0173 CFG_GATE_SETCLR(GATE_SPI3, RCC_MP_APB1ENSETR, 12),
0174 CFG_GATE_SETCLR(GATE_USART3, RCC_MP_APB1ENSETR, 15),
0175 CFG_GATE_SETCLR(GATE_UART4, RCC_MP_APB1ENSETR, 16),
0176 CFG_GATE_SETCLR(GATE_UART5, RCC_MP_APB1ENSETR, 17),
0177 CFG_GATE_SETCLR(GATE_UART7, RCC_MP_APB1ENSETR, 18),
0178 CFG_GATE_SETCLR(GATE_UART8, RCC_MP_APB1ENSETR, 19),
0179 CFG_GATE_SETCLR(GATE_I2C1, RCC_MP_APB1ENSETR, 21),
0180 CFG_GATE_SETCLR(GATE_I2C2, RCC_MP_APB1ENSETR, 22),
0181 CFG_GATE_SETCLR(GATE_SPDIF, RCC_MP_APB1ENSETR, 26),
0182 CFG_GATE_SETCLR(GATE_TIM1, RCC_MP_APB2ENSETR, 0),
0183 CFG_GATE_SETCLR(GATE_TIM8, RCC_MP_APB2ENSETR, 1),
0184 CFG_GATE_SETCLR(GATE_SPI1, RCC_MP_APB2ENSETR, 8),
0185 CFG_GATE_SETCLR(GATE_USART6, RCC_MP_APB2ENSETR, 13),
0186 CFG_GATE_SETCLR(GATE_SAI1, RCC_MP_APB2ENSETR, 16),
0187 CFG_GATE_SETCLR(GATE_SAI2, RCC_MP_APB2ENSETR, 17),
0188 CFG_GATE_SETCLR(GATE_DFSDM, RCC_MP_APB2ENSETR, 20),
0189 CFG_GATE_SETCLR(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21),
0190 CFG_GATE_SETCLR(GATE_FDCAN, RCC_MP_APB2ENSETR, 24),
0191 CFG_GATE_SETCLR(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0),
0192 CFG_GATE_SETCLR(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1),
0193 CFG_GATE_SETCLR(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2),
0194 CFG_GATE_SETCLR(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3),
0195 CFG_GATE_SETCLR(GATE_VREF, RCC_MP_APB3ENSETR, 13),
0196 CFG_GATE_SETCLR(GATE_DTS, RCC_MP_APB3ENSETR, 16),
0197 CFG_GATE_SETCLR(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17),
0198 CFG_GATE_SETCLR(GATE_HDP, RCC_MP_APB3ENSETR, 20),
0199 CFG_GATE_SETCLR(GATE_SYSCFG, RCC_MP_NS_APB3ENSETR, 0),
0200 CFG_GATE_SETCLR(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1),
0201 CFG_GATE_SETCLR(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8),
0202 CFG_GATE_SETCLR(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15),
0203 CFG_GATE_SETCLR(GATE_USBPHY, RCC_MP_APB4ENSETR, 16),
0204 CFG_GATE_SETCLR(GATE_STGENRO, RCC_MP_APB4ENSETR, 20),
0205 CFG_GATE_SETCLR(GATE_LTDC, RCC_MP_NS_APB4ENSETR, 0),
0206 CFG_GATE_SETCLR(GATE_RTCAPB, RCC_MP_APB5ENSETR, 8),
0207 CFG_GATE_SETCLR(GATE_TZC, RCC_MP_APB5ENSETR, 11),
0208 CFG_GATE_SETCLR(GATE_ETZPC, RCC_MP_APB5ENSETR, 13),
0209 CFG_GATE_SETCLR(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15),
0210 CFG_GATE_SETCLR(GATE_BSEC, RCC_MP_APB5ENSETR, 16),
0211 CFG_GATE_SETCLR(GATE_STGENC, RCC_MP_APB5ENSETR, 20),
0212 CFG_GATE_SETCLR(GATE_USART1, RCC_MP_APB6ENSETR, 0),
0213 CFG_GATE_SETCLR(GATE_USART2, RCC_MP_APB6ENSETR, 1),
0214 CFG_GATE_SETCLR(GATE_SPI4, RCC_MP_APB6ENSETR, 2),
0215 CFG_GATE_SETCLR(GATE_SPI5, RCC_MP_APB6ENSETR, 3),
0216 CFG_GATE_SETCLR(GATE_I2C3, RCC_MP_APB6ENSETR, 4),
0217 CFG_GATE_SETCLR(GATE_I2C4, RCC_MP_APB6ENSETR, 5),
0218 CFG_GATE_SETCLR(GATE_I2C5, RCC_MP_APB6ENSETR, 6),
0219 CFG_GATE_SETCLR(GATE_TIM12, RCC_MP_APB6ENSETR, 7),
0220 CFG_GATE_SETCLR(GATE_TIM13, RCC_MP_APB6ENSETR, 8),
0221 CFG_GATE_SETCLR(GATE_TIM14, RCC_MP_APB6ENSETR, 9),
0222 CFG_GATE_SETCLR(GATE_TIM15, RCC_MP_APB6ENSETR, 10),
0223 CFG_GATE_SETCLR(GATE_TIM16, RCC_MP_APB6ENSETR, 11),
0224 CFG_GATE_SETCLR(GATE_TIM17, RCC_MP_APB6ENSETR, 12),
0225 CFG_GATE_SETCLR(GATE_DMA1, RCC_MP_AHB2ENSETR, 0),
0226 CFG_GATE_SETCLR(GATE_DMA2, RCC_MP_AHB2ENSETR, 1),
0227 CFG_GATE_SETCLR(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2),
0228 CFG_GATE_SETCLR(GATE_DMA3, RCC_MP_AHB2ENSETR, 3),
0229 CFG_GATE_SETCLR(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4),
0230 CFG_GATE_SETCLR(GATE_ADC1, RCC_MP_AHB2ENSETR, 5),
0231 CFG_GATE_SETCLR(GATE_ADC2, RCC_MP_AHB2ENSETR, 6),
0232 CFG_GATE_SETCLR(GATE_USBO, RCC_MP_AHB2ENSETR, 8),
0233 CFG_GATE_SETCLR(GATE_TSC, RCC_MP_AHB4ENSETR, 15),
0234 CFG_GATE_SETCLR(GATE_GPIOA, RCC_MP_NS_AHB4ENSETR, 0),
0235 CFG_GATE_SETCLR(GATE_GPIOB, RCC_MP_NS_AHB4ENSETR, 1),
0236 CFG_GATE_SETCLR(GATE_GPIOC, RCC_MP_NS_AHB4ENSETR, 2),
0237 CFG_GATE_SETCLR(GATE_GPIOD, RCC_MP_NS_AHB4ENSETR, 3),
0238 CFG_GATE_SETCLR(GATE_GPIOE, RCC_MP_NS_AHB4ENSETR, 4),
0239 CFG_GATE_SETCLR(GATE_GPIOF, RCC_MP_NS_AHB4ENSETR, 5),
0240 CFG_GATE_SETCLR(GATE_GPIOG, RCC_MP_NS_AHB4ENSETR, 6),
0241 CFG_GATE_SETCLR(GATE_GPIOH, RCC_MP_NS_AHB4ENSETR, 7),
0242 CFG_GATE_SETCLR(GATE_GPIOI, RCC_MP_NS_AHB4ENSETR, 8),
0243 CFG_GATE_SETCLR(GATE_PKA, RCC_MP_AHB5ENSETR, 2),
0244 CFG_GATE_SETCLR(GATE_SAES, RCC_MP_AHB5ENSETR, 3),
0245 CFG_GATE_SETCLR(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4),
0246 CFG_GATE_SETCLR(GATE_HASH1, RCC_MP_AHB5ENSETR, 5),
0247 CFG_GATE_SETCLR(GATE_RNG1, RCC_MP_AHB5ENSETR, 6),
0248 CFG_GATE_SETCLR(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8),
0249 CFG_GATE_SETCLR(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16),
0250 CFG_GATE_SETCLR(GATE_MCE, RCC_MP_AHB6ENSETR, 1),
0251 CFG_GATE_SETCLR(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7),
0252 CFG_GATE_SETCLR(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8),
0253 CFG_GATE_SETCLR(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9),
0254 CFG_GATE_SETCLR(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10),
0255 CFG_GATE_SETCLR(GATE_FMC, RCC_MP_AHB6ENSETR, 12),
0256 CFG_GATE_SETCLR(GATE_QSPI, RCC_MP_AHB6ENSETR, 14),
0257 CFG_GATE_SETCLR(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16),
0258 CFG_GATE_SETCLR(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17),
0259 CFG_GATE_SETCLR(GATE_CRC1, RCC_MP_AHB6ENSETR, 20),
0260 CFG_GATE_SETCLR(GATE_USBH, RCC_MP_AHB6ENSETR, 24),
0261 CFG_GATE_SETCLR(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27),
0262 CFG_GATE_SETCLR(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28),
0263 CFG_GATE_SETCLR(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29),
0264 CFG_GATE_SETCLR(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30),
0265 CFG_GATE_SETCLR(GATE_ETH1STP, RCC_MP_AHB6LPENSETR, 11),
0266 CFG_GATE_SETCLR(GATE_ETH2STP, RCC_MP_AHB6LPENSETR, 31),
0267 CFG_GATE_SETCLR(GATE_MDMA, RCC_MP_NS_AHB6ENSETR, 0),
0268 };
0269
0270
0271 enum enum_div_cfg {
0272 DIV_RTC,
0273 DIV_HSI,
0274 DIV_MCO1,
0275 DIV_MCO2,
0276 DIV_TRACE,
0277 DIV_ETH1PTP,
0278 DIV_ETH2PTP,
0279 DIV_NB
0280 };
0281
0282 static const struct clk_div_table ck_trace_div_table[] = {
0283 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
0284 { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
0285 { 0 },
0286 };
0287
0288 #define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\
0289 [(_id)] = {\
0290 .offset = (_offset),\
0291 .shift = (_shift),\
0292 .width = (_width),\
0293 .flags = (_flags),\
0294 .table = (_table),\
0295 .ready = (_ready),\
0296 }
0297
0298 static const struct stm32_div_cfg stm32mp13_dividers[DIV_NB] = {
0299 CFG_DIV(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_RDY),
0300 CFG_DIV(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL, DIV_NO_RDY),
0301 CFG_DIV(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL, DIV_NO_RDY),
0302 CFG_DIV(DIV_TRACE, RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table, DIV_NO_RDY),
0303 CFG_DIV(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL, DIV_NO_RDY),
0304 CFG_DIV(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL, DIV_NO_RDY),
0305 };
0306
0307
0308 enum enum_mux_cfg {
0309 MUX_ADC1,
0310 MUX_ADC2,
0311 MUX_DCMIPP,
0312 MUX_ETH1,
0313 MUX_ETH2,
0314 MUX_FDCAN,
0315 MUX_FMC,
0316 MUX_I2C12,
0317 MUX_I2C3,
0318 MUX_I2C4,
0319 MUX_I2C5,
0320 MUX_LPTIM1,
0321 MUX_LPTIM2,
0322 MUX_LPTIM3,
0323 MUX_LPTIM45,
0324 MUX_MCO1,
0325 MUX_MCO2,
0326 MUX_QSPI,
0327 MUX_RNG1,
0328 MUX_SAES,
0329 MUX_SAI1,
0330 MUX_SAI2,
0331 MUX_SDMMC1,
0332 MUX_SDMMC2,
0333 MUX_SPDIF,
0334 MUX_SPI1,
0335 MUX_SPI23,
0336 MUX_SPI4,
0337 MUX_SPI5,
0338 MUX_STGEN,
0339 MUX_UART1,
0340 MUX_UART2,
0341 MUX_UART4,
0342 MUX_UART6,
0343 MUX_UART35,
0344 MUX_UART78,
0345 MUX_USBO,
0346 MUX_USBPHY,
0347 MUX_NB
0348 };
0349
0350 #define _CFG_MUX(_id, _offset, _shift, _witdh, _ready, _flags)\
0351 [_id] = {\
0352 .offset = (_offset),\
0353 .shift = (_shift),\
0354 .width = (_witdh),\
0355 .ready = (_ready),\
0356 .flags = (_flags),\
0357 }
0358
0359 #define CFG_MUX(_id, _offset, _shift, _witdh)\
0360 _CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, 0)
0361
0362 #define CFG_MUX_SAFE(_id, _offset, _shift, _witdh)\
0363 _CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, MUX_SAFE)
0364
0365 static const struct stm32_mux_cfg stm32mp13_muxes[] = {
0366 CFG_MUX(MUX_I2C12, RCC_I2C12CKSELR, 0, 3),
0367 CFG_MUX(MUX_LPTIM45, RCC_LPTIM45CKSELR, 0, 3),
0368 CFG_MUX(MUX_SPI23, RCC_SPI2S23CKSELR, 0, 3),
0369 CFG_MUX(MUX_UART35, RCC_UART35CKSELR, 0, 3),
0370 CFG_MUX(MUX_UART78, RCC_UART78CKSELR, 0, 3),
0371 CFG_MUX(MUX_ADC1, RCC_ADC12CKSELR, 0, 2),
0372 CFG_MUX(MUX_ADC2, RCC_ADC12CKSELR, 2, 2),
0373 CFG_MUX(MUX_DCMIPP, RCC_DCMIPPCKSELR, 0, 2),
0374 CFG_MUX(MUX_ETH1, RCC_ETH12CKSELR, 0, 2),
0375 CFG_MUX(MUX_ETH2, RCC_ETH12CKSELR, 8, 2),
0376 CFG_MUX(MUX_FDCAN, RCC_FDCANCKSELR, 0, 2),
0377 CFG_MUX(MUX_I2C3, RCC_I2C345CKSELR, 0, 3),
0378 CFG_MUX(MUX_I2C4, RCC_I2C345CKSELR, 3, 3),
0379 CFG_MUX(MUX_I2C5, RCC_I2C345CKSELR, 6, 3),
0380 CFG_MUX(MUX_LPTIM1, RCC_LPTIM1CKSELR, 0, 3),
0381 CFG_MUX(MUX_LPTIM2, RCC_LPTIM23CKSELR, 0, 3),
0382 CFG_MUX(MUX_LPTIM3, RCC_LPTIM23CKSELR, 3, 3),
0383 CFG_MUX(MUX_MCO1, RCC_MCO1CFGR, 0, 3),
0384 CFG_MUX(MUX_MCO2, RCC_MCO2CFGR, 0, 3),
0385 CFG_MUX(MUX_RNG1, RCC_RNG1CKSELR, 0, 2),
0386 CFG_MUX(MUX_SAES, RCC_SAESCKSELR, 0, 2),
0387 CFG_MUX(MUX_SAI1, RCC_SAI1CKSELR, 0, 3),
0388 CFG_MUX(MUX_SAI2, RCC_SAI2CKSELR, 0, 3),
0389 CFG_MUX(MUX_SPDIF, RCC_SPDIFCKSELR, 0, 2),
0390 CFG_MUX(MUX_SPI1, RCC_SPI2S1CKSELR, 0, 3),
0391 CFG_MUX(MUX_SPI4, RCC_SPI45CKSELR, 0, 3),
0392 CFG_MUX(MUX_SPI5, RCC_SPI45CKSELR, 3, 3),
0393 CFG_MUX(MUX_STGEN, RCC_STGENCKSELR, 0, 2),
0394 CFG_MUX(MUX_UART1, RCC_UART12CKSELR, 0, 3),
0395 CFG_MUX(MUX_UART2, RCC_UART12CKSELR, 3, 3),
0396 CFG_MUX(MUX_UART4, RCC_UART4CKSELR, 0, 3),
0397 CFG_MUX(MUX_UART6, RCC_UART6CKSELR, 0, 3),
0398 CFG_MUX(MUX_USBO, RCC_USBCKSELR, 4, 1),
0399 CFG_MUX(MUX_USBPHY, RCC_USBCKSELR, 0, 2),
0400 CFG_MUX_SAFE(MUX_FMC, RCC_FMCCKSELR, 0, 2),
0401 CFG_MUX_SAFE(MUX_QSPI, RCC_QSPICKSELR, 0, 2),
0402 CFG_MUX_SAFE(MUX_SDMMC1, RCC_SDMMC12CKSELR, 0, 3),
0403 CFG_MUX_SAFE(MUX_SDMMC2, RCC_SDMMC12CKSELR, 3, 3),
0404 };
0405
0406 struct clk_stm32_securiy {
0407 u32 offset;
0408 u8 bit_idx;
0409 unsigned long scmi_id;
0410 };
0411
0412 enum security_clk {
0413 SECF_NONE,
0414 SECF_LPTIM2,
0415 SECF_LPTIM3,
0416 SECF_VREF,
0417 SECF_DCMIPP,
0418 SECF_USBPHY,
0419 SECF_TZC,
0420 SECF_ETZPC,
0421 SECF_IWDG1,
0422 SECF_BSEC,
0423 SECF_STGENC,
0424 SECF_STGENRO,
0425 SECF_USART1,
0426 SECF_USART2,
0427 SECF_SPI4,
0428 SECF_SPI5,
0429 SECF_I2C3,
0430 SECF_I2C4,
0431 SECF_I2C5,
0432 SECF_TIM12,
0433 SECF_TIM13,
0434 SECF_TIM14,
0435 SECF_TIM15,
0436 SECF_TIM16,
0437 SECF_TIM17,
0438 SECF_DMA3,
0439 SECF_DMAMUX2,
0440 SECF_ADC1,
0441 SECF_ADC2,
0442 SECF_USBO,
0443 SECF_TSC,
0444 SECF_PKA,
0445 SECF_SAES,
0446 SECF_CRYP1,
0447 SECF_HASH1,
0448 SECF_RNG1,
0449 SECF_BKPSRAM,
0450 SECF_MCE,
0451 SECF_FMC,
0452 SECF_QSPI,
0453 SECF_SDMMC1,
0454 SECF_SDMMC2,
0455 SECF_ETH1CK,
0456 SECF_ETH1TX,
0457 SECF_ETH1RX,
0458 SECF_ETH1MAC,
0459 SECF_ETH1STP,
0460 SECF_ETH2CK,
0461 SECF_ETH2TX,
0462 SECF_ETH2RX,
0463 SECF_ETH2MAC,
0464 SECF_ETH2STP,
0465 SECF_MCO1,
0466 SECF_MCO2
0467 };
0468
0469 #define SECF(_sec_id, _offset, _bit_idx)[_sec_id] = {\
0470 .offset = _offset,\
0471 .bit_idx = _bit_idx,\
0472 .scmi_id = -1,\
0473 }
0474
0475 static const struct clk_stm32_securiy stm32mp13_security[] = {
0476 SECF(SECF_LPTIM2, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM2SECF),
0477 SECF(SECF_LPTIM3, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM3SECF),
0478 SECF(SECF_VREF, RCC_APB3SECSR, RCC_APB3SECSR_VREFSECF),
0479 SECF(SECF_DCMIPP, RCC_APB4SECSR, RCC_APB4SECSR_DCMIPPSECF),
0480 SECF(SECF_USBPHY, RCC_APB4SECSR, RCC_APB4SECSR_USBPHYSECF),
0481 SECF(SECF_TZC, RCC_APB5SECSR, RCC_APB5SECSR_TZCSECF),
0482 SECF(SECF_ETZPC, RCC_APB5SECSR, RCC_APB5SECSR_ETZPCSECF),
0483 SECF(SECF_IWDG1, RCC_APB5SECSR, RCC_APB5SECSR_IWDG1SECF),
0484 SECF(SECF_BSEC, RCC_APB5SECSR, RCC_APB5SECSR_BSECSECF),
0485 SECF(SECF_STGENC, RCC_APB5SECSR, RCC_APB5SECSR_STGENCSECF),
0486 SECF(SECF_STGENRO, RCC_APB5SECSR, RCC_APB5SECSR_STGENROSECF),
0487 SECF(SECF_USART1, RCC_APB6SECSR, RCC_APB6SECSR_USART1SECF),
0488 SECF(SECF_USART2, RCC_APB6SECSR, RCC_APB6SECSR_USART2SECF),
0489 SECF(SECF_SPI4, RCC_APB6SECSR, RCC_APB6SECSR_SPI4SECF),
0490 SECF(SECF_SPI5, RCC_APB6SECSR, RCC_APB6SECSR_SPI5SECF),
0491 SECF(SECF_I2C3, RCC_APB6SECSR, RCC_APB6SECSR_I2C3SECF),
0492 SECF(SECF_I2C4, RCC_APB6SECSR, RCC_APB6SECSR_I2C4SECF),
0493 SECF(SECF_I2C5, RCC_APB6SECSR, RCC_APB6SECSR_I2C5SECF),
0494 SECF(SECF_TIM12, RCC_APB6SECSR, RCC_APB6SECSR_TIM12SECF),
0495 SECF(SECF_TIM13, RCC_APB6SECSR, RCC_APB6SECSR_TIM13SECF),
0496 SECF(SECF_TIM14, RCC_APB6SECSR, RCC_APB6SECSR_TIM14SECF),
0497 SECF(SECF_TIM15, RCC_APB6SECSR, RCC_APB6SECSR_TIM15SECF),
0498 SECF(SECF_TIM16, RCC_APB6SECSR, RCC_APB6SECSR_TIM16SECF),
0499 SECF(SECF_TIM17, RCC_APB6SECSR, RCC_APB6SECSR_TIM17SECF),
0500 SECF(SECF_DMA3, RCC_AHB2SECSR, RCC_AHB2SECSR_DMA3SECF),
0501 SECF(SECF_DMAMUX2, RCC_AHB2SECSR, RCC_AHB2SECSR_DMAMUX2SECF),
0502 SECF(SECF_ADC1, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC1SECF),
0503 SECF(SECF_ADC2, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC2SECF),
0504 SECF(SECF_USBO, RCC_AHB2SECSR, RCC_AHB2SECSR_USBOSECF),
0505 SECF(SECF_TSC, RCC_AHB4SECSR, RCC_AHB4SECSR_TSCSECF),
0506 SECF(SECF_PKA, RCC_AHB5SECSR, RCC_AHB5SECSR_PKASECF),
0507 SECF(SECF_SAES, RCC_AHB5SECSR, RCC_AHB5SECSR_SAESSECF),
0508 SECF(SECF_CRYP1, RCC_AHB5SECSR, RCC_AHB5SECSR_CRYP1SECF),
0509 SECF(SECF_HASH1, RCC_AHB5SECSR, RCC_AHB5SECSR_HASH1SECF),
0510 SECF(SECF_RNG1, RCC_AHB5SECSR, RCC_AHB5SECSR_RNG1SECF),
0511 SECF(SECF_BKPSRAM, RCC_AHB5SECSR, RCC_AHB5SECSR_BKPSRAMSECF),
0512 SECF(SECF_MCE, RCC_AHB6SECSR, RCC_AHB6SECSR_MCESECF),
0513 SECF(SECF_FMC, RCC_AHB6SECSR, RCC_AHB6SECSR_FMCSECF),
0514 SECF(SECF_QSPI, RCC_AHB6SECSR, RCC_AHB6SECSR_QSPISECF),
0515 SECF(SECF_SDMMC1, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC1SECF),
0516 SECF(SECF_SDMMC2, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC2SECF),
0517 SECF(SECF_ETH1CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1CKSECF),
0518 SECF(SECF_ETH1TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1TXSECF),
0519 SECF(SECF_ETH1RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1RXSECF),
0520 SECF(SECF_ETH1MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1MACSECF),
0521 SECF(SECF_ETH1STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1STPSECF),
0522 SECF(SECF_ETH2CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2CKSECF),
0523 SECF(SECF_ETH2TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2TXSECF),
0524 SECF(SECF_ETH2RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2RXSECF),
0525 SECF(SECF_ETH2MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2MACSECF),
0526 SECF(SECF_ETH2STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2STPSECF),
0527 SECF(SECF_MCO1, RCC_SECCFGR, RCC_SECCFGR_MCO1SEC),
0528 SECF(SECF_MCO2, RCC_SECCFGR, RCC_SECCFGR_MCO2SEC),
0529 };
0530
0531 static const char * const adc12_src[] = {
0532 "pll4_r", "ck_per", "pll3_q"
0533 };
0534
0535 static const char * const dcmipp_src[] = {
0536 "ck_axi", "pll2_q", "pll4_p", "ck_per",
0537 };
0538
0539 static const char * const eth12_src[] = {
0540 "pll4_p", "pll3_q"
0541 };
0542
0543 static const char * const fdcan_src[] = {
0544 "ck_hse", "pll3_q", "pll4_q", "pll4_r"
0545 };
0546
0547 static const char * const fmc_src[] = {
0548 "ck_axi", "pll3_r", "pll4_p", "ck_per"
0549 };
0550
0551 static const char * const i2c12_src[] = {
0552 "pclk1", "pll4_r", "ck_hsi", "ck_csi"
0553 };
0554
0555 static const char * const i2c345_src[] = {
0556 "pclk6", "pll4_r", "ck_hsi", "ck_csi"
0557 };
0558
0559 static const char * const lptim1_src[] = {
0560 "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
0561 };
0562
0563 static const char * const lptim23_src[] = {
0564 "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
0565 };
0566
0567 static const char * const lptim45_src[] = {
0568 "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
0569 };
0570
0571 static const char * const mco1_src[] = {
0572 "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
0573 };
0574
0575 static const char * const mco2_src[] = {
0576 "ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi"
0577 };
0578
0579 static const char * const qspi_src[] = {
0580 "ck_axi", "pll3_r", "pll4_p", "ck_per"
0581 };
0582
0583 static const char * const rng1_src[] = {
0584 "ck_csi", "pll4_r", "ck_lse", "ck_lsi"
0585 };
0586
0587 static const char * const saes_src[] = {
0588 "ck_axi", "ck_per", "pll4_r", "ck_lsi"
0589 };
0590
0591 static const char * const sai1_src[] = {
0592 "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
0593 };
0594
0595 static const char * const sai2_src[] = {
0596 "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
0597 };
0598
0599 static const char * const sdmmc12_src[] = {
0600 "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
0601 };
0602
0603 static const char * const spdif_src[] = {
0604 "pll4_p", "pll3_q", "ck_hsi"
0605 };
0606
0607 static const char * const spi123_src[] = {
0608 "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
0609 };
0610
0611 static const char * const spi4_src[] = {
0612 "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "i2s_ckin"
0613 };
0614
0615 static const char * const spi5_src[] = {
0616 "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
0617 };
0618
0619 static const char * const stgen_src[] = {
0620 "ck_hsi", "ck_hse"
0621 };
0622
0623 static const char * const usart12_src[] = {
0624 "pclk6", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
0625 };
0626
0627 static const char * const usart34578_src[] = {
0628 "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
0629 };
0630
0631 static const char * const usart6_src[] = {
0632 "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
0633 };
0634
0635 static const char * const usbo_src[] = {
0636 "pll4_r", "ck_usbo_48m"
0637 };
0638
0639 static const char * const usbphy_src[] = {
0640 "ck_hse", "pll4_r", "clk-hse-div2"
0641 };
0642
0643
0644 static struct clk_stm32_gate tim2_k = {
0645 .gate_id = GATE_TIM2,
0646 .hw.init = CLK_HW_INIT("tim2_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0647 };
0648
0649 static struct clk_stm32_gate tim3_k = {
0650 .gate_id = GATE_TIM3,
0651 .hw.init = CLK_HW_INIT("tim3_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0652 };
0653
0654 static struct clk_stm32_gate tim4_k = {
0655 .gate_id = GATE_TIM4,
0656 .hw.init = CLK_HW_INIT("tim4_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0657 };
0658
0659 static struct clk_stm32_gate tim5_k = {
0660 .gate_id = GATE_TIM5,
0661 .hw.init = CLK_HW_INIT("tim5_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0662 };
0663
0664 static struct clk_stm32_gate tim6_k = {
0665 .gate_id = GATE_TIM6,
0666 .hw.init = CLK_HW_INIT("tim6_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0667 };
0668
0669 static struct clk_stm32_gate tim7_k = {
0670 .gate_id = GATE_TIM7,
0671 .hw.init = CLK_HW_INIT("tim7_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0672 };
0673
0674 static struct clk_stm32_gate tim1_k = {
0675 .gate_id = GATE_TIM1,
0676 .hw.init = CLK_HW_INIT("tim1_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0677 };
0678
0679 static struct clk_stm32_gate tim8_k = {
0680 .gate_id = GATE_TIM8,
0681 .hw.init = CLK_HW_INIT("tim8_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0682 };
0683
0684 static struct clk_stm32_gate tim12_k = {
0685 .gate_id = GATE_TIM12,
0686 .hw.init = CLK_HW_INIT("tim12_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0687 };
0688
0689 static struct clk_stm32_gate tim13_k = {
0690 .gate_id = GATE_TIM13,
0691 .hw.init = CLK_HW_INIT("tim13_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0692 };
0693
0694 static struct clk_stm32_gate tim14_k = {
0695 .gate_id = GATE_TIM14,
0696 .hw.init = CLK_HW_INIT("tim14_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0697 };
0698
0699 static struct clk_stm32_gate tim15_k = {
0700 .gate_id = GATE_TIM15,
0701 .hw.init = CLK_HW_INIT("tim15_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0702 };
0703
0704 static struct clk_stm32_gate tim16_k = {
0705 .gate_id = GATE_TIM16,
0706 .hw.init = CLK_HW_INIT("tim16_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0707 };
0708
0709 static struct clk_stm32_gate tim17_k = {
0710 .gate_id = GATE_TIM17,
0711 .hw.init = CLK_HW_INIT("tim17_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
0712 };
0713
0714
0715 static struct clk_stm32_gate sai1 = {
0716 .gate_id = GATE_SAI1,
0717 .hw.init = CLK_HW_INIT("sai1", "pclk2", &clk_stm32_gate_ops, 0),
0718 };
0719
0720 static struct clk_stm32_gate sai2 = {
0721 .gate_id = GATE_SAI2,
0722 .hw.init = CLK_HW_INIT("sai2", "pclk2", &clk_stm32_gate_ops, 0),
0723 };
0724
0725 static struct clk_stm32_gate syscfg = {
0726 .gate_id = GATE_SYSCFG,
0727 .hw.init = CLK_HW_INIT("syscfg", "pclk3", &clk_stm32_gate_ops, 0),
0728 };
0729
0730 static struct clk_stm32_gate vref = {
0731 .gate_id = GATE_VREF,
0732 .hw.init = CLK_HW_INIT("vref", "pclk3", &clk_stm32_gate_ops, 0),
0733 };
0734
0735 static struct clk_stm32_gate dts = {
0736 .gate_id = GATE_DTS,
0737 .hw.init = CLK_HW_INIT("dts", "pclk3", &clk_stm32_gate_ops, 0),
0738 };
0739
0740 static struct clk_stm32_gate pmbctrl = {
0741 .gate_id = GATE_PMBCTRL,
0742 .hw.init = CLK_HW_INIT("pmbctrl", "pclk3", &clk_stm32_gate_ops, 0),
0743 };
0744
0745 static struct clk_stm32_gate hdp = {
0746 .gate_id = GATE_HDP,
0747 .hw.init = CLK_HW_INIT("hdp", "pclk3", &clk_stm32_gate_ops, 0),
0748 };
0749
0750 static struct clk_stm32_gate iwdg2 = {
0751 .gate_id = GATE_IWDG2APB,
0752 .hw.init = CLK_HW_INIT("iwdg2", "pclk4", &clk_stm32_gate_ops, 0),
0753 };
0754
0755 static struct clk_stm32_gate stgenro = {
0756 .gate_id = GATE_STGENRO,
0757 .hw.init = CLK_HW_INIT("stgenro", "pclk4", &clk_stm32_gate_ops, 0),
0758 };
0759
0760 static struct clk_stm32_gate gpioa = {
0761 .gate_id = GATE_GPIOA,
0762 .hw.init = CLK_HW_INIT("gpioa", "pclk4", &clk_stm32_gate_ops, 0),
0763 };
0764
0765 static struct clk_stm32_gate gpiob = {
0766 .gate_id = GATE_GPIOB,
0767 .hw.init = CLK_HW_INIT("gpiob", "pclk4", &clk_stm32_gate_ops, 0),
0768 };
0769
0770 static struct clk_stm32_gate gpioc = {
0771 .gate_id = GATE_GPIOC,
0772 .hw.init = CLK_HW_INIT("gpioc", "pclk4", &clk_stm32_gate_ops, 0),
0773 };
0774
0775 static struct clk_stm32_gate gpiod = {
0776 .gate_id = GATE_GPIOD,
0777 .hw.init = CLK_HW_INIT("gpiod", "pclk4", &clk_stm32_gate_ops, 0),
0778 };
0779
0780 static struct clk_stm32_gate gpioe = {
0781 .gate_id = GATE_GPIOE,
0782 .hw.init = CLK_HW_INIT("gpioe", "pclk4", &clk_stm32_gate_ops, 0),
0783 };
0784
0785 static struct clk_stm32_gate gpiof = {
0786 .gate_id = GATE_GPIOF,
0787 .hw.init = CLK_HW_INIT("gpiof", "pclk4", &clk_stm32_gate_ops, 0),
0788 };
0789
0790 static struct clk_stm32_gate gpiog = {
0791 .gate_id = GATE_GPIOG,
0792 .hw.init = CLK_HW_INIT("gpiog", "pclk4", &clk_stm32_gate_ops, 0),
0793 };
0794
0795 static struct clk_stm32_gate gpioh = {
0796 .gate_id = GATE_GPIOH,
0797 .hw.init = CLK_HW_INIT("gpioh", "pclk4", &clk_stm32_gate_ops, 0),
0798 };
0799
0800 static struct clk_stm32_gate gpioi = {
0801 .gate_id = GATE_GPIOI,
0802 .hw.init = CLK_HW_INIT("gpioi", "pclk4", &clk_stm32_gate_ops, 0),
0803 };
0804
0805 static struct clk_stm32_gate tsc = {
0806 .gate_id = GATE_TSC,
0807 .hw.init = CLK_HW_INIT("tsc", "pclk4", &clk_stm32_gate_ops, 0),
0808 };
0809
0810 static struct clk_stm32_gate ddrperfm = {
0811 .gate_id = GATE_DDRPERFM,
0812 .hw.init = CLK_HW_INIT("ddrperfm", "pclk4", &clk_stm32_gate_ops, 0),
0813 };
0814
0815 static struct clk_stm32_gate tzpc = {
0816 .gate_id = GATE_TZC,
0817 .hw.init = CLK_HW_INIT("tzpc", "pclk5", &clk_stm32_gate_ops, 0),
0818 };
0819
0820 static struct clk_stm32_gate iwdg1 = {
0821 .gate_id = GATE_IWDG1APB,
0822 .hw.init = CLK_HW_INIT("iwdg1", "pclk5", &clk_stm32_gate_ops, 0),
0823 };
0824
0825 static struct clk_stm32_gate bsec = {
0826 .gate_id = GATE_BSEC,
0827 .hw.init = CLK_HW_INIT("bsec", "pclk5", &clk_stm32_gate_ops, 0),
0828 };
0829
0830 static struct clk_stm32_gate dma1 = {
0831 .gate_id = GATE_DMA1,
0832 .hw.init = CLK_HW_INIT("dma1", "ck_mlahb", &clk_stm32_gate_ops, 0),
0833 };
0834
0835 static struct clk_stm32_gate dma2 = {
0836 .gate_id = GATE_DMA2,
0837 .hw.init = CLK_HW_INIT("dma2", "ck_mlahb", &clk_stm32_gate_ops, 0),
0838 };
0839
0840 static struct clk_stm32_gate dmamux1 = {
0841 .gate_id = GATE_DMAMUX1,
0842 .hw.init = CLK_HW_INIT("dmamux1", "ck_mlahb", &clk_stm32_gate_ops, 0),
0843 };
0844
0845 static struct clk_stm32_gate dma3 = {
0846 .gate_id = GATE_DMA3,
0847 .hw.init = CLK_HW_INIT("dma3", "ck_mlahb", &clk_stm32_gate_ops, 0),
0848 };
0849
0850 static struct clk_stm32_gate dmamux2 = {
0851 .gate_id = GATE_DMAMUX2,
0852 .hw.init = CLK_HW_INIT("dmamux2", "ck_mlahb", &clk_stm32_gate_ops, 0),
0853 };
0854
0855 static struct clk_stm32_gate adc1 = {
0856 .gate_id = GATE_ADC1,
0857 .hw.init = CLK_HW_INIT("adc1", "ck_mlahb", &clk_stm32_gate_ops, 0),
0858 };
0859
0860 static struct clk_stm32_gate adc2 = {
0861 .gate_id = GATE_ADC2,
0862 .hw.init = CLK_HW_INIT("adc2", "ck_mlahb", &clk_stm32_gate_ops, 0),
0863 };
0864
0865 static struct clk_stm32_gate pka = {
0866 .gate_id = GATE_PKA,
0867 .hw.init = CLK_HW_INIT("pka", "ck_axi", &clk_stm32_gate_ops, 0),
0868 };
0869
0870 static struct clk_stm32_gate cryp1 = {
0871 .gate_id = GATE_CRYP1,
0872 .hw.init = CLK_HW_INIT("cryp1", "ck_axi", &clk_stm32_gate_ops, 0),
0873 };
0874
0875 static struct clk_stm32_gate hash1 = {
0876 .gate_id = GATE_HASH1,
0877 .hw.init = CLK_HW_INIT("hash1", "ck_axi", &clk_stm32_gate_ops, 0),
0878 };
0879
0880 static struct clk_stm32_gate bkpsram = {
0881 .gate_id = GATE_BKPSRAM,
0882 .hw.init = CLK_HW_INIT("bkpsram", "ck_axi", &clk_stm32_gate_ops, 0),
0883 };
0884
0885 static struct clk_stm32_gate mdma = {
0886 .gate_id = GATE_MDMA,
0887 .hw.init = CLK_HW_INIT("mdma", "ck_axi", &clk_stm32_gate_ops, 0),
0888 };
0889
0890 static struct clk_stm32_gate eth1tx = {
0891 .gate_id = GATE_ETH1TX,
0892 .hw.init = CLK_HW_INIT("eth1tx", "ck_axi", &clk_stm32_gate_ops, 0),
0893 };
0894
0895 static struct clk_stm32_gate eth1rx = {
0896 .gate_id = GATE_ETH1RX,
0897 .hw.init = CLK_HW_INIT("eth1rx", "ck_axi", &clk_stm32_gate_ops, 0),
0898 };
0899
0900 static struct clk_stm32_gate eth1mac = {
0901 .gate_id = GATE_ETH1MAC,
0902 .hw.init = CLK_HW_INIT("eth1mac", "ck_axi", &clk_stm32_gate_ops, 0),
0903 };
0904
0905 static struct clk_stm32_gate eth2tx = {
0906 .gate_id = GATE_ETH2TX,
0907 .hw.init = CLK_HW_INIT("eth2tx", "ck_axi", &clk_stm32_gate_ops, 0),
0908 };
0909
0910 static struct clk_stm32_gate eth2rx = {
0911 .gate_id = GATE_ETH2RX,
0912 .hw.init = CLK_HW_INIT("eth2rx", "ck_axi", &clk_stm32_gate_ops, 0),
0913 };
0914
0915 static struct clk_stm32_gate eth2mac = {
0916 .gate_id = GATE_ETH2MAC,
0917 .hw.init = CLK_HW_INIT("eth2mac", "ck_axi", &clk_stm32_gate_ops, 0),
0918 };
0919
0920 static struct clk_stm32_gate crc1 = {
0921 .gate_id = GATE_CRC1,
0922 .hw.init = CLK_HW_INIT("crc1", "ck_axi", &clk_stm32_gate_ops, 0),
0923 };
0924
0925 static struct clk_stm32_gate usbh = {
0926 .gate_id = GATE_USBH,
0927 .hw.init = CLK_HW_INIT("usbh", "ck_axi", &clk_stm32_gate_ops, 0),
0928 };
0929
0930 static struct clk_stm32_gate eth1stp = {
0931 .gate_id = GATE_ETH1STP,
0932 .hw.init = CLK_HW_INIT("eth1stp", "ck_axi", &clk_stm32_gate_ops, 0),
0933 };
0934
0935 static struct clk_stm32_gate eth2stp = {
0936 .gate_id = GATE_ETH2STP,
0937 .hw.init = CLK_HW_INIT("eth2stp", "ck_axi", &clk_stm32_gate_ops, 0),
0938 };
0939
0940
0941 static struct clk_stm32_composite sdmmc1_k = {
0942 .gate_id = GATE_SDMMC1,
0943 .mux_id = MUX_SDMMC1,
0944 .div_id = NO_STM32_DIV,
0945 .hw.init = CLK_HW_INIT_PARENTS("sdmmc1_k", sdmmc12_src, &clk_stm32_composite_ops,
0946 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
0947 };
0948
0949 static struct clk_stm32_composite sdmmc2_k = {
0950 .gate_id = GATE_SDMMC2,
0951 .mux_id = MUX_SDMMC2,
0952 .div_id = NO_STM32_DIV,
0953 .hw.init = CLK_HW_INIT_PARENTS("sdmmc2_k", sdmmc12_src, &clk_stm32_composite_ops,
0954 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
0955 };
0956
0957 static struct clk_stm32_composite fmc_k = {
0958 .gate_id = GATE_FMC,
0959 .mux_id = MUX_FMC,
0960 .div_id = NO_STM32_DIV,
0961 .hw.init = CLK_HW_INIT_PARENTS("fmc_k", fmc_src, &clk_stm32_composite_ops,
0962 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
0963 };
0964
0965 static struct clk_stm32_composite qspi_k = {
0966 .gate_id = GATE_QSPI,
0967 .mux_id = MUX_QSPI,
0968 .div_id = NO_STM32_DIV,
0969 .hw.init = CLK_HW_INIT_PARENTS("qspi_k", qspi_src, &clk_stm32_composite_ops,
0970 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
0971 };
0972
0973 static struct clk_stm32_composite spi2_k = {
0974 .gate_id = GATE_SPI2,
0975 .mux_id = MUX_SPI23,
0976 .div_id = NO_STM32_DIV,
0977 .hw.init = CLK_HW_INIT_PARENTS("spi2_k", spi123_src, &clk_stm32_composite_ops,
0978 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
0979 };
0980
0981 static struct clk_stm32_composite spi3_k = {
0982 .gate_id = GATE_SPI3,
0983 .mux_id = MUX_SPI23,
0984 .div_id = NO_STM32_DIV,
0985 .hw.init = CLK_HW_INIT_PARENTS("spi3_k", spi123_src, &clk_stm32_composite_ops,
0986 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
0987 };
0988
0989 static struct clk_stm32_composite i2c1_k = {
0990 .gate_id = GATE_I2C1,
0991 .mux_id = MUX_I2C12,
0992 .div_id = NO_STM32_DIV,
0993 .hw.init = CLK_HW_INIT_PARENTS("i2c1_k", i2c12_src, &clk_stm32_composite_ops,
0994 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
0995 };
0996
0997 static struct clk_stm32_composite i2c2_k = {
0998 .gate_id = GATE_I2C2,
0999 .mux_id = MUX_I2C12,
1000 .div_id = NO_STM32_DIV,
1001 .hw.init = CLK_HW_INIT_PARENTS("i2c2_k", i2c12_src, &clk_stm32_composite_ops,
1002 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1003 };
1004
1005 static struct clk_stm32_composite lptim4_k = {
1006 .gate_id = GATE_LPTIM4,
1007 .mux_id = MUX_LPTIM45,
1008 .div_id = NO_STM32_DIV,
1009 .hw.init = CLK_HW_INIT_PARENTS("lptim4_k", lptim45_src, &clk_stm32_composite_ops,
1010 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1011 };
1012
1013 static struct clk_stm32_composite lptim5_k = {
1014 .gate_id = GATE_LPTIM5,
1015 .mux_id = MUX_LPTIM45,
1016 .div_id = NO_STM32_DIV,
1017 .hw.init = CLK_HW_INIT_PARENTS("lptim5_k", lptim45_src, &clk_stm32_composite_ops,
1018 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1019 };
1020
1021 static struct clk_stm32_composite usart3_k = {
1022 .gate_id = GATE_USART3,
1023 .mux_id = MUX_UART35,
1024 .div_id = NO_STM32_DIV,
1025 .hw.init = CLK_HW_INIT_PARENTS("usart3_k", usart34578_src, &clk_stm32_composite_ops,
1026 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1027 };
1028
1029 static struct clk_stm32_composite uart5_k = {
1030 .gate_id = GATE_UART5,
1031 .mux_id = MUX_UART35,
1032 .div_id = NO_STM32_DIV,
1033 .hw.init = CLK_HW_INIT_PARENTS("uart5_k", usart34578_src, &clk_stm32_composite_ops,
1034 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1035 };
1036
1037 static struct clk_stm32_composite uart7_k = {
1038 .gate_id = GATE_UART7,
1039 .mux_id = MUX_UART78,
1040 .div_id = NO_STM32_DIV,
1041 .hw.init = CLK_HW_INIT_PARENTS("uart7_k", usart34578_src, &clk_stm32_composite_ops,
1042 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1043 };
1044
1045 static struct clk_stm32_composite uart8_k = {
1046 .gate_id = GATE_UART8,
1047 .mux_id = MUX_UART78,
1048 .div_id = NO_STM32_DIV,
1049 .hw.init = CLK_HW_INIT_PARENTS("uart8_k", usart34578_src, &clk_stm32_composite_ops,
1050 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1051 };
1052
1053 static struct clk_stm32_composite sai1_k = {
1054 .gate_id = GATE_SAI1,
1055 .mux_id = MUX_SAI1,
1056 .div_id = NO_STM32_DIV,
1057 .hw.init = CLK_HW_INIT_PARENTS("sai1_k", sai1_src, &clk_stm32_composite_ops,
1058 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1059 };
1060
1061 static struct clk_stm32_composite adfsdm_k = {
1062 .gate_id = GATE_ADFSDM,
1063 .mux_id = MUX_SAI1,
1064 .div_id = NO_STM32_DIV,
1065 .hw.init = CLK_HW_INIT_PARENTS("adfsdm_k", sai1_src, &clk_stm32_composite_ops,
1066 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1067 };
1068
1069 static struct clk_stm32_composite sai2_k = {
1070 .gate_id = GATE_SAI2,
1071 .mux_id = MUX_SAI2,
1072 .div_id = NO_STM32_DIV,
1073 .hw.init = CLK_HW_INIT_PARENTS("sai2_k", sai2_src, &clk_stm32_composite_ops,
1074 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1075 };
1076
1077 static struct clk_stm32_composite adc1_k = {
1078 .gate_id = GATE_ADC1,
1079 .mux_id = MUX_ADC1,
1080 .div_id = NO_STM32_DIV,
1081 .hw.init = CLK_HW_INIT_PARENTS("adc1_k", adc12_src, &clk_stm32_composite_ops,
1082 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1083 };
1084
1085 static struct clk_stm32_composite adc2_k = {
1086 .gate_id = GATE_ADC2,
1087 .mux_id = MUX_ADC2,
1088 .div_id = NO_STM32_DIV,
1089 .hw.init = CLK_HW_INIT_PARENTS("adc2_k", adc12_src, &clk_stm32_composite_ops,
1090 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1091 };
1092
1093 static struct clk_stm32_composite rng1_k = {
1094 .gate_id = GATE_RNG1,
1095 .mux_id = MUX_RNG1,
1096 .div_id = NO_STM32_DIV,
1097 .hw.init = CLK_HW_INIT_PARENTS("rng1_k", rng1_src, &clk_stm32_composite_ops,
1098 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1099 };
1100
1101 static struct clk_stm32_composite usbphy_k = {
1102 .gate_id = GATE_USBPHY,
1103 .mux_id = MUX_USBPHY,
1104 .div_id = NO_STM32_DIV,
1105 .hw.init = CLK_HW_INIT_PARENTS("usbphy_k", usbphy_src, &clk_stm32_composite_ops,
1106 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1107 };
1108
1109 static struct clk_stm32_composite stgen_k = {
1110 .gate_id = GATE_STGENC,
1111 .mux_id = MUX_STGEN,
1112 .div_id = NO_STM32_DIV,
1113 .hw.init = CLK_HW_INIT_PARENTS("stgen_k", stgen_src, &clk_stm32_composite_ops,
1114 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1115 };
1116
1117 static struct clk_stm32_composite spdif_k = {
1118 .gate_id = GATE_SPDIF,
1119 .mux_id = MUX_SPDIF,
1120 .div_id = NO_STM32_DIV,
1121 .hw.init = CLK_HW_INIT_PARENTS("spdif_k", spdif_src, &clk_stm32_composite_ops,
1122 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1123 };
1124
1125 static struct clk_stm32_composite spi1_k = {
1126 .gate_id = GATE_SPI1,
1127 .mux_id = MUX_SPI1,
1128 .div_id = NO_STM32_DIV,
1129 .hw.init = CLK_HW_INIT_PARENTS("spi1_k", spi123_src, &clk_stm32_composite_ops,
1130 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1131 };
1132
1133 static struct clk_stm32_composite spi4_k = {
1134 .gate_id = GATE_SPI4,
1135 .mux_id = MUX_SPI4,
1136 .div_id = NO_STM32_DIV,
1137 .hw.init = CLK_HW_INIT_PARENTS("spi4_k", spi4_src, &clk_stm32_composite_ops,
1138 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1139 };
1140
1141 static struct clk_stm32_composite spi5_k = {
1142 .gate_id = GATE_SPI5,
1143 .mux_id = MUX_SPI5,
1144 .div_id = NO_STM32_DIV,
1145 .hw.init = CLK_HW_INIT_PARENTS("spi5_k", spi5_src, &clk_stm32_composite_ops,
1146 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1147 };
1148
1149 static struct clk_stm32_composite i2c3_k = {
1150 .gate_id = GATE_I2C3,
1151 .mux_id = MUX_I2C3,
1152 .div_id = NO_STM32_DIV,
1153 .hw.init = CLK_HW_INIT_PARENTS("i2c3_k", i2c345_src, &clk_stm32_composite_ops,
1154 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1155 };
1156
1157 static struct clk_stm32_composite i2c4_k = {
1158 .gate_id = GATE_I2C4,
1159 .mux_id = MUX_I2C4,
1160 .div_id = NO_STM32_DIV,
1161 .hw.init = CLK_HW_INIT_PARENTS("i2c4_k", i2c345_src, &clk_stm32_composite_ops,
1162 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1163 };
1164
1165 static struct clk_stm32_composite i2c5_k = {
1166 .gate_id = GATE_I2C5,
1167 .mux_id = MUX_I2C5,
1168 .div_id = NO_STM32_DIV,
1169 .hw.init = CLK_HW_INIT_PARENTS("i2c5_k", i2c345_src, &clk_stm32_composite_ops,
1170 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1171 };
1172
1173 static struct clk_stm32_composite lptim1_k = {
1174 .gate_id = GATE_LPTIM1,
1175 .mux_id = MUX_LPTIM1,
1176 .div_id = NO_STM32_DIV,
1177 .hw.init = CLK_HW_INIT_PARENTS("lptim1_k", lptim1_src, &clk_stm32_composite_ops,
1178 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1179 };
1180
1181 static struct clk_stm32_composite lptim2_k = {
1182 .gate_id = GATE_LPTIM2,
1183 .mux_id = MUX_LPTIM2,
1184 .div_id = NO_STM32_DIV,
1185 .hw.init = CLK_HW_INIT_PARENTS("lptim2_k", lptim23_src, &clk_stm32_composite_ops,
1186 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1187 };
1188
1189 static struct clk_stm32_composite lptim3_k = {
1190 .gate_id = GATE_LPTIM3,
1191 .mux_id = MUX_LPTIM3,
1192 .div_id = NO_STM32_DIV,
1193 .hw.init = CLK_HW_INIT_PARENTS("lptim3_k", lptim23_src, &clk_stm32_composite_ops,
1194 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1195 };
1196
1197 static struct clk_stm32_composite usart1_k = {
1198 .gate_id = GATE_USART1,
1199 .mux_id = MUX_UART1,
1200 .div_id = NO_STM32_DIV,
1201 .hw.init = CLK_HW_INIT_PARENTS("usart1_k", usart12_src, &clk_stm32_composite_ops,
1202 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1203 };
1204
1205 static struct clk_stm32_composite usart2_k = {
1206 .gate_id = GATE_USART2,
1207 .mux_id = MUX_UART2,
1208 .div_id = NO_STM32_DIV,
1209 .hw.init = CLK_HW_INIT_PARENTS("usart2_k", usart12_src, &clk_stm32_composite_ops,
1210 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1211 };
1212
1213 static struct clk_stm32_composite uart4_k = {
1214 .gate_id = GATE_UART4,
1215 .mux_id = MUX_UART4,
1216 .div_id = NO_STM32_DIV,
1217 .hw.init = CLK_HW_INIT_PARENTS("uart4_k", usart34578_src, &clk_stm32_composite_ops,
1218 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1219 };
1220
1221 static struct clk_stm32_composite uart6_k = {
1222 .gate_id = GATE_USART6,
1223 .mux_id = MUX_UART6,
1224 .div_id = NO_STM32_DIV,
1225 .hw.init = CLK_HW_INIT_PARENTS("uart6_k", usart6_src, &clk_stm32_composite_ops,
1226 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1227 };
1228
1229 static struct clk_stm32_composite fdcan_k = {
1230 .gate_id = GATE_FDCAN,
1231 .mux_id = MUX_FDCAN,
1232 .div_id = NO_STM32_DIV,
1233 .hw.init = CLK_HW_INIT_PARENTS("fdcan_k", fdcan_src, &clk_stm32_composite_ops,
1234 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1235 };
1236
1237 static struct clk_stm32_composite dcmipp_k = {
1238 .gate_id = GATE_DCMIPP,
1239 .mux_id = MUX_DCMIPP,
1240 .div_id = NO_STM32_DIV,
1241 .hw.init = CLK_HW_INIT_PARENTS("dcmipp_k", dcmipp_src, &clk_stm32_composite_ops,
1242 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1243 };
1244
1245 static struct clk_stm32_composite usbo_k = {
1246 .gate_id = GATE_USBO,
1247 .mux_id = MUX_USBO,
1248 .div_id = NO_STM32_DIV,
1249 .hw.init = CLK_HW_INIT_PARENTS("usbo_k", usbo_src, &clk_stm32_composite_ops,
1250 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1251 };
1252
1253 static struct clk_stm32_composite saes_k = {
1254 .gate_id = GATE_SAES,
1255 .mux_id = MUX_SAES,
1256 .div_id = NO_STM32_DIV,
1257 .hw.init = CLK_HW_INIT_PARENTS("saes_k", saes_src, &clk_stm32_composite_ops,
1258 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1259 };
1260
1261 static struct clk_stm32_gate dfsdm_k = {
1262 .gate_id = GATE_DFSDM,
1263 .hw.init = CLK_HW_INIT("dfsdm_k", "ck_mlahb", &clk_stm32_gate_ops, 0),
1264 };
1265
1266 static struct clk_stm32_gate ltdc_px = {
1267 .gate_id = GATE_LTDC,
1268 .hw.init = CLK_HW_INIT("ltdc_px", "pll4_q", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
1269 };
1270
1271 static struct clk_stm32_mux ck_ker_eth1 = {
1272 .mux_id = MUX_ETH1,
1273 .hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops,
1274 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1275 };
1276
1277 static struct clk_stm32_gate eth1ck_k = {
1278 .gate_id = GATE_ETH1CK,
1279 .hw.init = CLK_HW_INIT_HW("eth1ck_k", &ck_ker_eth1.hw, &clk_stm32_gate_ops, 0),
1280 };
1281
1282 static struct clk_stm32_div eth1ptp_k = {
1283 .div_id = DIV_ETH1PTP,
1284 .hw.init = CLK_HW_INIT_HW("eth1ptp_k", &ck_ker_eth1.hw, &clk_stm32_divider_ops,
1285 CLK_SET_RATE_NO_REPARENT),
1286 };
1287
1288 static struct clk_stm32_mux ck_ker_eth2 = {
1289 .mux_id = MUX_ETH2,
1290 .hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth2", eth12_src, &clk_stm32_mux_ops,
1291 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1292 };
1293
1294 static struct clk_stm32_gate eth2ck_k = {
1295 .gate_id = GATE_ETH2CK,
1296 .hw.init = CLK_HW_INIT_HW("eth2ck_k", &ck_ker_eth2.hw, &clk_stm32_gate_ops, 0),
1297 };
1298
1299 static struct clk_stm32_div eth2ptp_k = {
1300 .div_id = DIV_ETH2PTP,
1301 .hw.init = CLK_HW_INIT_HW("eth2ptp_k", &ck_ker_eth2.hw, &clk_stm32_divider_ops,
1302 CLK_SET_RATE_NO_REPARENT),
1303 };
1304
1305 static struct clk_stm32_composite ck_mco1 = {
1306 .gate_id = GATE_MCO1,
1307 .mux_id = MUX_MCO1,
1308 .div_id = DIV_MCO1,
1309 .hw.init = CLK_HW_INIT_PARENTS("ck_mco1", mco1_src, &clk_stm32_composite_ops,
1310 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
1311 CLK_IGNORE_UNUSED),
1312 };
1313
1314 static struct clk_stm32_composite ck_mco2 = {
1315 .gate_id = GATE_MCO2,
1316 .mux_id = MUX_MCO2,
1317 .div_id = DIV_MCO2,
1318 .hw.init = CLK_HW_INIT_PARENTS("ck_mco2", mco2_src, &clk_stm32_composite_ops,
1319 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
1320 CLK_IGNORE_UNUSED),
1321 };
1322
1323
1324 static struct clk_stm32_gate ck_sys_dbg = {
1325 .gate_id = GATE_DBGCK,
1326 .hw.init = CLK_HW_INIT("ck_sys_dbg", "ck_axi", &clk_stm32_gate_ops, CLK_IS_CRITICAL),
1327 };
1328
1329 static struct clk_stm32_composite ck_trace = {
1330 .gate_id = GATE_TRACECK,
1331 .mux_id = NO_STM32_MUX,
1332 .div_id = DIV_TRACE,
1333 .hw.init = CLK_HW_INIT("ck_trace", "ck_axi", &clk_stm32_composite_ops, CLK_IGNORE_UNUSED),
1334 };
1335
1336 static const struct clock_config stm32mp13_clock_cfg[] = {
1337
1338 STM32_GATE_CFG(TIM2_K, tim2_k, SECF_NONE),
1339 STM32_GATE_CFG(TIM3_K, tim3_k, SECF_NONE),
1340 STM32_GATE_CFG(TIM4_K, tim4_k, SECF_NONE),
1341 STM32_GATE_CFG(TIM5_K, tim5_k, SECF_NONE),
1342 STM32_GATE_CFG(TIM6_K, tim6_k, SECF_NONE),
1343 STM32_GATE_CFG(TIM7_K, tim7_k, SECF_NONE),
1344 STM32_GATE_CFG(TIM1_K, tim1_k, SECF_NONE),
1345 STM32_GATE_CFG(TIM8_K, tim8_k, SECF_NONE),
1346 STM32_GATE_CFG(TIM12_K, tim12_k, SECF_TIM12),
1347 STM32_GATE_CFG(TIM13_K, tim13_k, SECF_TIM13),
1348 STM32_GATE_CFG(TIM14_K, tim14_k, SECF_TIM14),
1349 STM32_GATE_CFG(TIM15_K, tim15_k, SECF_TIM15),
1350 STM32_GATE_CFG(TIM16_K, tim16_k, SECF_TIM16),
1351 STM32_GATE_CFG(TIM17_K, tim17_k, SECF_TIM17),
1352
1353
1354 STM32_GATE_CFG(SAI1, sai1, SECF_NONE),
1355 STM32_GATE_CFG(SAI2, sai2, SECF_NONE),
1356 STM32_GATE_CFG(SYSCFG, syscfg, SECF_NONE),
1357 STM32_GATE_CFG(VREF, vref, SECF_VREF),
1358 STM32_GATE_CFG(DTS, dts, SECF_NONE),
1359 STM32_GATE_CFG(PMBCTRL, pmbctrl, SECF_NONE),
1360 STM32_GATE_CFG(HDP, hdp, SECF_NONE),
1361 STM32_GATE_CFG(IWDG2, iwdg2, SECF_NONE),
1362 STM32_GATE_CFG(STGENRO, stgenro, SECF_STGENRO),
1363 STM32_GATE_CFG(TZPC, tzpc, SECF_TZC),
1364 STM32_GATE_CFG(IWDG1, iwdg1, SECF_IWDG1),
1365 STM32_GATE_CFG(BSEC, bsec, SECF_BSEC),
1366 STM32_GATE_CFG(DMA1, dma1, SECF_NONE),
1367 STM32_GATE_CFG(DMA2, dma2, SECF_NONE),
1368 STM32_GATE_CFG(DMAMUX1, dmamux1, SECF_NONE),
1369 STM32_GATE_CFG(DMA3, dma3, SECF_DMA3),
1370 STM32_GATE_CFG(DMAMUX2, dmamux2, SECF_DMAMUX2),
1371 STM32_GATE_CFG(ADC1, adc1, SECF_ADC1),
1372 STM32_GATE_CFG(ADC2, adc2, SECF_ADC2),
1373 STM32_GATE_CFG(GPIOA, gpioa, SECF_NONE),
1374 STM32_GATE_CFG(GPIOB, gpiob, SECF_NONE),
1375 STM32_GATE_CFG(GPIOC, gpioc, SECF_NONE),
1376 STM32_GATE_CFG(GPIOD, gpiod, SECF_NONE),
1377 STM32_GATE_CFG(GPIOE, gpioe, SECF_NONE),
1378 STM32_GATE_CFG(GPIOF, gpiof, SECF_NONE),
1379 STM32_GATE_CFG(GPIOG, gpiog, SECF_NONE),
1380 STM32_GATE_CFG(GPIOH, gpioh, SECF_NONE),
1381 STM32_GATE_CFG(GPIOI, gpioi, SECF_NONE),
1382 STM32_GATE_CFG(TSC, tsc, SECF_TZC),
1383 STM32_GATE_CFG(PKA, pka, SECF_PKA),
1384 STM32_GATE_CFG(CRYP1, cryp1, SECF_CRYP1),
1385 STM32_GATE_CFG(HASH1, hash1, SECF_HASH1),
1386 STM32_GATE_CFG(BKPSRAM, bkpsram, SECF_BKPSRAM),
1387 STM32_GATE_CFG(MDMA, mdma, SECF_NONE),
1388 STM32_GATE_CFG(ETH1TX, eth1tx, SECF_ETH1TX),
1389 STM32_GATE_CFG(ETH1RX, eth1rx, SECF_ETH1RX),
1390 STM32_GATE_CFG(ETH1MAC, eth1mac, SECF_ETH1MAC),
1391 STM32_GATE_CFG(ETH2TX, eth2tx, SECF_ETH2TX),
1392 STM32_GATE_CFG(ETH2RX, eth2rx, SECF_ETH2RX),
1393 STM32_GATE_CFG(ETH2MAC, eth2mac, SECF_ETH2MAC),
1394 STM32_GATE_CFG(CRC1, crc1, SECF_NONE),
1395 STM32_GATE_CFG(USBH, usbh, SECF_NONE),
1396 STM32_GATE_CFG(DDRPERFM, ddrperfm, SECF_NONE),
1397 STM32_GATE_CFG(ETH1STP, eth1stp, SECF_ETH1STP),
1398 STM32_GATE_CFG(ETH2STP, eth2stp, SECF_ETH2STP),
1399
1400
1401 STM32_COMPOSITE_CFG(SDMMC1_K, sdmmc1_k, SECF_SDMMC1),
1402 STM32_COMPOSITE_CFG(SDMMC2_K, sdmmc2_k, SECF_SDMMC2),
1403 STM32_COMPOSITE_CFG(FMC_K, fmc_k, SECF_FMC),
1404 STM32_COMPOSITE_CFG(QSPI_K, qspi_k, SECF_QSPI),
1405 STM32_COMPOSITE_CFG(SPI2_K, spi2_k, SECF_NONE),
1406 STM32_COMPOSITE_CFG(SPI3_K, spi3_k, SECF_NONE),
1407 STM32_COMPOSITE_CFG(I2C1_K, i2c1_k, SECF_NONE),
1408 STM32_COMPOSITE_CFG(I2C2_K, i2c2_k, SECF_NONE),
1409 STM32_COMPOSITE_CFG(LPTIM4_K, lptim4_k, SECF_NONE),
1410 STM32_COMPOSITE_CFG(LPTIM5_K, lptim5_k, SECF_NONE),
1411 STM32_COMPOSITE_CFG(USART3_K, usart3_k, SECF_NONE),
1412 STM32_COMPOSITE_CFG(UART5_K, uart5_k, SECF_NONE),
1413 STM32_COMPOSITE_CFG(UART7_K, uart7_k, SECF_NONE),
1414 STM32_COMPOSITE_CFG(UART8_K, uart8_k, SECF_NONE),
1415 STM32_COMPOSITE_CFG(SAI1_K, sai1_k, SECF_NONE),
1416 STM32_COMPOSITE_CFG(SAI2_K, sai2_k, SECF_NONE),
1417 STM32_COMPOSITE_CFG(ADFSDM_K, adfsdm_k, SECF_NONE),
1418 STM32_COMPOSITE_CFG(ADC1_K, adc1_k, SECF_ADC1),
1419 STM32_COMPOSITE_CFG(ADC2_K, adc2_k, SECF_ADC2),
1420 STM32_COMPOSITE_CFG(RNG1_K, rng1_k, SECF_RNG1),
1421 STM32_COMPOSITE_CFG(USBPHY_K, usbphy_k, SECF_USBPHY),
1422 STM32_COMPOSITE_CFG(STGEN_K, stgen_k, SECF_STGENC),
1423 STM32_COMPOSITE_CFG(SPDIF_K, spdif_k, SECF_NONE),
1424 STM32_COMPOSITE_CFG(SPI1_K, spi1_k, SECF_NONE),
1425 STM32_COMPOSITE_CFG(SPI4_K, spi4_k, SECF_SPI4),
1426 STM32_COMPOSITE_CFG(SPI5_K, spi5_k, SECF_SPI5),
1427 STM32_COMPOSITE_CFG(I2C3_K, i2c3_k, SECF_I2C3),
1428 STM32_COMPOSITE_CFG(I2C4_K, i2c4_k, SECF_I2C4),
1429 STM32_COMPOSITE_CFG(I2C5_K, i2c5_k, SECF_I2C5),
1430 STM32_COMPOSITE_CFG(LPTIM1_K, lptim1_k, SECF_NONE),
1431 STM32_COMPOSITE_CFG(LPTIM2_K, lptim2_k, SECF_LPTIM2),
1432 STM32_COMPOSITE_CFG(LPTIM3_K, lptim3_k, SECF_LPTIM3),
1433 STM32_COMPOSITE_CFG(USART1_K, usart1_k, SECF_USART1),
1434 STM32_COMPOSITE_CFG(USART2_K, usart2_k, SECF_USART2),
1435 STM32_COMPOSITE_CFG(UART4_K, uart4_k, SECF_NONE),
1436 STM32_COMPOSITE_CFG(USART6_K, uart6_k, SECF_NONE),
1437 STM32_COMPOSITE_CFG(FDCAN_K, fdcan_k, SECF_NONE),
1438 STM32_COMPOSITE_CFG(DCMIPP_K, dcmipp_k, SECF_DCMIPP),
1439 STM32_COMPOSITE_CFG(USBO_K, usbo_k, SECF_USBO),
1440 STM32_COMPOSITE_CFG(SAES_K, saes_k, SECF_SAES),
1441 STM32_GATE_CFG(DFSDM_K, dfsdm_k, SECF_NONE),
1442 STM32_GATE_CFG(LTDC_PX, ltdc_px, SECF_NONE),
1443
1444 STM32_MUX_CFG(NO_ID, ck_ker_eth1, SECF_ETH1CK),
1445 STM32_GATE_CFG(ETH1CK_K, eth1ck_k, SECF_ETH1CK),
1446 STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k, SECF_ETH1CK),
1447
1448 STM32_MUX_CFG(NO_ID, ck_ker_eth2, SECF_ETH2CK),
1449 STM32_GATE_CFG(ETH2CK_K, eth2ck_k, SECF_ETH2CK),
1450 STM32_DIV_CFG(ETH2PTP_K, eth2ptp_k, SECF_ETH2CK),
1451
1452 STM32_GATE_CFG(CK_DBG, ck_sys_dbg, SECF_NONE),
1453 STM32_COMPOSITE_CFG(CK_TRACE, ck_trace, SECF_NONE),
1454
1455 STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1, SECF_MCO1),
1456 STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2, SECF_MCO2),
1457 };
1458
1459 static int stm32mp13_clock_is_provided_by_secure(void __iomem *base,
1460 const struct clock_config *cfg)
1461 {
1462 int sec_id = cfg->sec_id;
1463
1464 if (sec_id != SECF_NONE) {
1465 const struct clk_stm32_securiy *secf;
1466
1467 secf = &stm32mp13_security[sec_id];
1468
1469 return !!(readl(base + secf->offset) & BIT(secf->bit_idx));
1470 }
1471
1472 return 0;
1473 }
1474
1475 struct multi_mux {
1476 struct clk_hw *hw1;
1477 struct clk_hw *hw2;
1478 };
1479
1480 static struct multi_mux *stm32_mp13_multi_mux[MUX_NB] = {
1481 [MUX_SPI23] = &(struct multi_mux){ &spi2_k.hw, &spi3_k.hw },
1482 [MUX_I2C12] = &(struct multi_mux){ &i2c1_k.hw, &i2c2_k.hw },
1483 [MUX_LPTIM45] = &(struct multi_mux){ &lptim4_k.hw, &lptim5_k.hw },
1484 [MUX_UART35] = &(struct multi_mux){ &usart3_k.hw, &uart5_k.hw },
1485 [MUX_UART78] = &(struct multi_mux){ &uart7_k.hw, &uart8_k.hw },
1486 [MUX_SAI1] = &(struct multi_mux){ &sai1_k.hw, &adfsdm_k.hw },
1487 };
1488
1489 static struct clk_hw *stm32mp13_is_multi_mux(struct clk_hw *hw)
1490 {
1491 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
1492 struct multi_mux *mmux = stm32_mp13_multi_mux[composite->mux_id];
1493
1494 if (mmux) {
1495 if (!(mmux->hw1 == hw))
1496 return mmux->hw1;
1497 else
1498 return mmux->hw2;
1499 }
1500
1501 return NULL;
1502 }
1503
1504 static u16 stm32mp13_cpt_gate[GATE_NB];
1505
1506 static struct clk_stm32_clock_data stm32mp13_clock_data = {
1507 .gate_cpt = stm32mp13_cpt_gate,
1508 .gates = stm32mp13_gates,
1509 .muxes = stm32mp13_muxes,
1510 .dividers = stm32mp13_dividers,
1511 .is_multi_mux = stm32mp13_is_multi_mux,
1512 };
1513
1514 static const struct stm32_rcc_match_data stm32mp13_data = {
1515 .tab_clocks = stm32mp13_clock_cfg,
1516 .num_clocks = ARRAY_SIZE(stm32mp13_clock_cfg),
1517 .clock_data = &stm32mp13_clock_data,
1518 .check_security = &stm32mp13_clock_is_provided_by_secure,
1519 .maxbinding = STM32MP1_LAST_CLK,
1520 .clear_offset = RCC_CLR_OFFSET,
1521 };
1522
1523 static const struct of_device_id stm32mp13_match_data[] = {
1524 {
1525 .compatible = "st,stm32mp13-rcc",
1526 .data = &stm32mp13_data,
1527 },
1528 { }
1529 };
1530 MODULE_DEVICE_TABLE(of, stm32mp13_match_data);
1531
1532 static int stm32mp1_rcc_init(struct device *dev)
1533 {
1534 void __iomem *rcc_base;
1535 int ret = -ENOMEM;
1536
1537 rcc_base = of_iomap(dev_of_node(dev), 0);
1538 if (!rcc_base) {
1539 dev_err(dev, "%pOFn: unable to map resource", dev_of_node(dev));
1540 goto out;
1541 }
1542
1543 ret = stm32_rcc_init(dev, stm32mp13_match_data, rcc_base);
1544 out:
1545 if (ret) {
1546 if (rcc_base)
1547 iounmap(rcc_base);
1548
1549 of_node_put(dev_of_node(dev));
1550 }
1551
1552 return ret;
1553 }
1554
1555 static int get_clock_deps(struct device *dev)
1556 {
1557 static const char * const clock_deps_name[] = {
1558 "hsi", "hse", "csi", "lsi", "lse",
1559 };
1560 size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
1561 struct clk **clk_deps;
1562 int i;
1563
1564 clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
1565 if (!clk_deps)
1566 return -ENOMEM;
1567
1568 for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
1569 struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
1570 clock_deps_name[i]);
1571
1572 if (IS_ERR(clk)) {
1573 if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
1574 return PTR_ERR(clk);
1575 } else {
1576
1577 clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
1578 clk_put(clk);
1579 }
1580 }
1581
1582 return 0;
1583 }
1584
1585 static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
1586 {
1587 struct device *dev = &pdev->dev;
1588 int ret = get_clock_deps(dev);
1589
1590 if (!ret)
1591 ret = stm32mp1_rcc_init(dev);
1592
1593 return ret;
1594 }
1595
1596 static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
1597 {
1598 struct device *dev = &pdev->dev;
1599 struct device_node *child, *np = dev_of_node(dev);
1600
1601 for_each_available_child_of_node(np, child)
1602 of_clk_del_provider(child);
1603
1604 return 0;
1605 }
1606
1607 static struct platform_driver stm32mp13_rcc_clocks_driver = {
1608 .driver = {
1609 .name = "stm32mp13_rcc",
1610 .of_match_table = stm32mp13_match_data,
1611 },
1612 .probe = stm32mp1_rcc_clocks_probe,
1613 .remove = stm32mp1_rcc_clocks_remove,
1614 };
1615
1616 static int __init stm32mp13_clocks_init(void)
1617 {
1618 return platform_driver_register(&stm32mp13_rcc_clocks_driver);
1619 }
1620 core_initcall(stm32mp13_clocks_init);
