clk/stm32/clk-stm32-core.h

0001 /* SPDX-License-Identifier: GPL-2.0  */
0002 /*
0003  * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
0004  * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
0005  */
0006
0007 #include <linux/clk-provider.h>
0008
0009 struct stm32_rcc_match_data;
0010
0011 struct stm32_mux_cfg {
0012     u16 offset;
0013     u8  shift;
0014     u8  width;
0015     u8  flags;
0016     u32 *table;
0017     u8  ready;
0018 };
0019
0020 struct stm32_gate_cfg {
0021     u16 offset;
0022     u8  bit_idx;
0023     u8  set_clr;
0024 };
0025
0026 struct stm32_div_cfg {
0027     u16 offset;
0028     u8  shift;
0029     u8  width;
0030     u8  flags;
0031     u8  ready;
0032     const struct clk_div_table *table;
0033 };
0034
0035 struct stm32_composite_cfg {
0036     int mux;
0037     int gate;
0038     int div;
0039 };
0040
0041 #define NO_ID 0xFFFFFFFF
0042
0043 #define NO_STM32_MUX        0xFFFF
0044 #define NO_STM32_DIV        0xFFFF
0045 #define NO_STM32_GATE       0xFFFF
0046
0047 struct clock_config {
0048     unsigned long   id;
0049     int     sec_id;
0050     void        *clock_cfg;
0051
0052     struct clk_hw *(*func)(struct device *dev,
0053                    const struct stm32_rcc_match_data *data,
0054                    void __iomem *base,
0055                    spinlock_t *lock,
0056                    const struct clock_config *cfg);
0057 };
0058
0059 struct clk_stm32_clock_data {
0060     u16 *gate_cpt;
0061     const struct stm32_gate_cfg *gates;
0062     const struct stm32_mux_cfg  *muxes;
0063     const struct stm32_div_cfg  *dividers;
0064     struct clk_hw *(*is_multi_mux)(struct clk_hw *hw);
0065 };
0066
0067 struct stm32_rcc_match_data {
0068     struct clk_hw_onecell_data  *hw_clks;
0069     unsigned int            num_clocks;
0070     const struct clock_config   *tab_clocks;
0071     unsigned int            maxbinding;
0072     struct clk_stm32_clock_data *clock_data;
0073     u32             clear_offset;
0074     int (*check_security)(void __iomem *base,
0075                   const struct clock_config *cfg);
0076     int (*multi_mux)(void __iomem *base, const struct clock_config *cfg);
0077 };
0078
0079 int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
0080              void __iomem *base);
0081
0082 int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
0083            void __iomem *base);
0084
0085 /* MUX define */
0086 #define MUX_NO_RDY      0xFF
0087 #define MUX_SAFE        BIT(7)
0088
0089 /* DIV define */
0090 #define DIV_NO_RDY      0xFF
0091
0092 /* Definition of clock structure */
0093 struct clk_stm32_mux {
0094     u16 mux_id;
0095     struct clk_hw hw;
0096     void __iomem *base;
0097     struct clk_stm32_clock_data *clock_data;
0098     spinlock_t *lock; /* spin lock */
0099 };
0100
0101 #define to_clk_stm32_mux(_hw) container_of(_hw, struct clk_stm32_mux, hw)
0102
0103 struct clk_stm32_gate {
0104     u16 gate_id;
0105     struct clk_hw hw;
0106     void __iomem *base;
0107     struct clk_stm32_clock_data *clock_data;
0108     spinlock_t *lock; /* spin lock */
0109 };
0110
0111 #define to_clk_stm32_gate(_hw) container_of(_hw, struct clk_stm32_gate, hw)
0112
0113 struct clk_stm32_div {
0114     u16 div_id;
0115     struct clk_hw hw;
0116     void __iomem *base;
0117     struct clk_stm32_clock_data *clock_data;
0118     spinlock_t *lock; /* spin lock */
0119 };
0120
0121 #define to_clk_stm32_divider(_hw) container_of(_hw, struct clk_stm32_div, hw)
0122
0123 struct clk_stm32_composite {
0124     u16 gate_id;
0125     u16 mux_id;
0126     u16 div_id;
0127     struct clk_hw hw;
0128     void __iomem *base;
0129     struct clk_stm32_clock_data *clock_data;
0130     spinlock_t *lock; /* spin lock */
0131 };
0132
0133 #define to_clk_stm32_composite(_hw) container_of(_hw, struct clk_stm32_composite, hw)
0134
0135 /* Clock operators */
0136 extern const struct clk_ops clk_stm32_mux_ops;
0137 extern const struct clk_ops clk_stm32_gate_ops;
0138 extern const struct clk_ops clk_stm32_divider_ops;
0139 extern const struct clk_ops clk_stm32_composite_ops;
0140
0141 /* Clock registering */
0142 struct clk_hw *clk_stm32_mux_register(struct device *dev,
0143                       const struct stm32_rcc_match_data *data,
0144                       void __iomem *base,
0145                       spinlock_t *lock,
0146                       const struct clock_config *cfg);
0147
0148 struct clk_hw *clk_stm32_gate_register(struct device *dev,
0149                        const struct stm32_rcc_match_data *data,
0150                        void __iomem *base,
0151                        spinlock_t *lock,
0152                        const struct clock_config *cfg);
0153
0154 struct clk_hw *clk_stm32_div_register(struct device *dev,
0155                       const struct stm32_rcc_match_data *data,
0156                       void __iomem *base,
0157                       spinlock_t *lock,
0158                       const struct clock_config *cfg);
0159
0160 struct clk_hw *clk_stm32_composite_register(struct device *dev,
0161                         const struct stm32_rcc_match_data *data,
0162                         void __iomem *base,
0163                         spinlock_t *lock,
0164                         const struct clock_config *cfg);
0165
0166 #define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\
0167 {\
0168     .id     = (_binding),\
0169     .sec_id     = (_sec_id),\
0170     .clock_cfg  = (_struct) {_clk},\
0171     .func       = (_register),\
0172 }
0173
0174 #define STM32_MUX_CFG(_binding, _clk, _sec_id)\
0175     STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_mux *,\
0176             &clk_stm32_mux_register)
0177
0178 #define STM32_GATE_CFG(_binding, _clk, _sec_id)\
0179     STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_gate *,\
0180             &clk_stm32_gate_register)
0181
0182 #define STM32_DIV_CFG(_binding, _clk, _sec_id)\
0183     STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_div *,\
0184             &clk_stm32_div_register)
0185
0186 #define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\
0187     STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_composite *,\
0188             &clk_stm32_composite_register)