clk/starfive/clk-starfive-jh7100.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __CLK_STARFIVE_JH7100_H
0003 #define __CLK_STARFIVE_JH7100_H
0004
0005 #include <linux/bits.h>
0006 #include <linux/clk-provider.h>
0007
0008 /* register fields */
0009 #define JH7100_CLK_ENABLE   BIT(31)
0010 #define JH7100_CLK_INVERT   BIT(30)
0011 #define JH7100_CLK_MUX_MASK GENMASK(27, 24)
0012 #define JH7100_CLK_MUX_SHIFT    24
0013 #define JH7100_CLK_DIV_MASK GENMASK(23, 0)
0014 #define JH7100_CLK_FRAC_MASK    GENMASK(15, 8)
0015 #define JH7100_CLK_FRAC_SHIFT   8
0016 #define JH7100_CLK_INT_MASK GENMASK(7, 0)
0017
0018 /* fractional divider min/max */
0019 #define JH7100_CLK_FRAC_MIN 100UL
0020 #define JH7100_CLK_FRAC_MAX 25599UL
0021
0022 /* clock data */
0023 struct jh7100_clk_data {
0024     const char *name;
0025     unsigned long flags;
0026     u32 max;
0027     u8 parents[4];
0028 };
0029
0030 #define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = {            \
0031     .name = _name,                              \
0032     .flags = CLK_SET_RATE_PARENT | (_flags),                \
0033     .max = JH7100_CLK_ENABLE,                       \
0034     .parents = { [0] = _parent },                       \
0035 }
0036
0037 #define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = {          \
0038     .name = _name,                              \
0039     .flags = 0,                             \
0040     .max = _max,                                \
0041     .parents = { [0] = _parent },                       \
0042 }
0043
0044 #define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = {      \
0045     .name = _name,                              \
0046     .flags = _flags,                            \
0047     .max = JH7100_CLK_ENABLE | (_max),                  \
0048     .parents = { [0] = _parent },                       \
0049 }
0050
0051 #define JH7100_FDIV(_idx, _name, _parent) [_idx] = {                \
0052     .name = _name,                              \
0053     .flags = 0,                             \
0054     .max = JH7100_CLK_FRAC_MAX,                     \
0055     .parents = { [0] = _parent },                       \
0056 }
0057
0058 #define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = {         \
0059     .name = _name,                              \
0060     .flags = 0,                             \
0061     .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT,           \
0062     .parents = { __VA_ARGS__ },                     \
0063 }
0064
0065 #define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = {     \
0066     .name = _name,                              \
0067     .flags = _flags,                            \
0068     .max = JH7100_CLK_ENABLE |                      \
0069         (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT),            \
0070     .parents = { __VA_ARGS__ },                     \
0071 }
0072
0073 #define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = {       \
0074     .name = _name,                              \
0075     .flags = 0,                             \
0076     .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max),        \
0077     .parents = { __VA_ARGS__ },                     \
0078 }
0079
0080 #define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = {   \
0081     .name = _name,                              \
0082     .flags = _flags,                            \
0083     .max = JH7100_CLK_ENABLE |                      \
0084         (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max),       \
0085     .parents = { __VA_ARGS__ },                     \
0086 }
0087
0088 #define JH7100__INV(_idx, _name, _parent) [_idx] = {                \
0089     .name = _name,                              \
0090     .flags = CLK_SET_RATE_PARENT,                       \
0091     .max = JH7100_CLK_INVERT,                       \
0092     .parents = { [0] = _parent },                       \
0093 }
0094
0095 struct jh7100_clk {
0096     struct clk_hw hw;
0097     unsigned int idx;
0098     unsigned int max_div;
0099 };
0100
0101 struct jh7100_clk_priv {
0102     /* protect clk enable and set rate/parent from happening at the same time */
0103     spinlock_t rmw_lock;
0104     struct device *dev;
0105     void __iomem *base;
0106     struct clk_hw *pll[3];
0107     struct jh7100_clk reg[];
0108 };
0109
0110 const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
0111
0112 #endif