clk/starfive/clk-starfive-jh7100.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * StarFive JH7100 Clock Generator Driver
0004  *
0005  * Copyright 2021 Ahmad Fatoum, Pengutronix
0006  * Copyright (C) 2021 Glider bv
0007  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
0008  */
0009
0010 #include <linux/bits.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/debugfs.h>
0013 #include <linux/device.h>
0014 #include <linux/init.h>
0015 #include <linux/io.h>
0016 #include <linux/kernel.h>
0017 #include <linux/mod_devicetable.h>
0018 #include <linux/module.h>
0019 #include <linux/platform_device.h>
0020
0021 #include <dt-bindings/clock/starfive-jh7100.h>
0022
0023 #include "clk-starfive-jh7100.h"
0024
0025 /* external clocks */
0026 #define JH7100_CLK_OSC_SYS      (JH7100_CLK_END + 0)
0027 #define JH7100_CLK_OSC_AUD      (JH7100_CLK_END + 1)
0028 #define JH7100_CLK_GMAC_RMII_REF    (JH7100_CLK_END + 2)
0029 #define JH7100_CLK_GMAC_GR_MII_RX   (JH7100_CLK_END + 3)
0030
0031 static const struct jh7100_clk_data jh7100_clk_data[] __initconst = {
0032     JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
0033             JH7100_CLK_OSC_SYS,
0034             JH7100_CLK_PLL0_OUT,
0035             JH7100_CLK_PLL1_OUT,
0036             JH7100_CLK_PLL2_OUT),
0037     JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
0038             JH7100_CLK_OSC_SYS,
0039             JH7100_CLK_PLL1_OUT,
0040             JH7100_CLK_PLL2_OUT),
0041     JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
0042             JH7100_CLK_OSC_SYS,
0043             JH7100_CLK_PLL0_OUT,
0044             JH7100_CLK_PLL1_OUT,
0045             JH7100_CLK_PLL2_OUT),
0046     JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
0047             JH7100_CLK_OSC_SYS,
0048             JH7100_CLK_PLL0_OUT,
0049             JH7100_CLK_PLL2_OUT),
0050     JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
0051             JH7100_CLK_OSC_SYS,
0052             JH7100_CLK_PLL0_OUT),
0053     JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
0054             JH7100_CLK_OSC_SYS,
0055             JH7100_CLK_PLL2_OUT),
0056     JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
0057             JH7100_CLK_OSC_SYS,
0058             JH7100_CLK_PLL1_OUT,
0059             JH7100_CLK_PLL2_OUT),
0060     JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
0061             JH7100_CLK_OSC_AUD,
0062             JH7100_CLK_PLL0_OUT,
0063             JH7100_CLK_PLL2_OUT),
0064     JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
0065     JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
0066             JH7100_CLK_OSC_SYS,
0067             JH7100_CLK_PLL1_OUT,
0068             JH7100_CLK_PLL2_OUT),
0069     JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
0070             JH7100_CLK_OSC_SYS,
0071             JH7100_CLK_PLL0_OUT,
0072             JH7100_CLK_PLL1_OUT),
0073     JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
0074             JH7100_CLK_OSC_AUD,
0075             JH7100_CLK_PLL0_OUT,
0076             JH7100_CLK_PLL2_OUT),
0077     JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
0078     JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
0079     JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
0080     JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
0081     JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
0082     JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
0083     JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
0084     JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
0085             JH7100_CLK_OSC_SYS,
0086             JH7100_CLK_OSC_AUD),
0087     JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
0088     JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
0089     JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
0090     JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
0091     JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
0092     JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
0093     JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
0094     JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
0095     JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
0096     JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
0097     JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
0098     JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
0099     JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
0100     JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
0101     JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
0102     JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
0103     JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
0104     JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
0105     JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
0106     JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
0107     JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
0108     JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
0109     JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
0110     JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
0111     JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
0112     JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
0113     JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
0114     JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
0115     JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
0116     JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
0117     JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
0118     JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
0119     JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
0120     JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
0121     JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
0122     JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
0123     JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
0124     JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
0125     JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
0126     JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
0127     JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
0128     JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
0129     JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
0130     JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
0131     JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
0132     JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
0133     JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
0134             JH7100_CLK_DDROSC_DIV2,
0135             JH7100_CLK_DDRPLL_DIV2,
0136             JH7100_CLK_DDRPLL_DIV4,
0137             JH7100_CLK_DDRPLL_DIV8),
0138     JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
0139             JH7100_CLK_DDROSC_DIV2,
0140             JH7100_CLK_DDRPLL_DIV2,
0141             JH7100_CLK_DDRPLL_DIV4,
0142             JH7100_CLK_DDRPLL_DIV8),
0143     JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
0144     JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
0145     JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
0146     JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
0147     JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
0148     JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
0149             JH7100_CLK_CPU_AXI,
0150             JH7100_CLK_NNEBUS_SRC1),
0151     JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
0152     JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
0153     JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
0154     JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
0155     JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
0156     JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
0157     JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
0158     JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
0159     JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
0160     JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
0161     JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
0162     JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
0163     JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
0164     JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
0165     JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
0166     JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
0167     JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
0168     JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
0169     JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
0170     JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
0171     JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
0172             JH7100_CLK_OSC_SYS,
0173             JH7100_CLK_USBPHY_PLLDIV25M),
0174     JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
0175     JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
0176     JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
0177     JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
0178     JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
0179     JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
0180     JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
0181     JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
0182     JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
0183     JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
0184     JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
0185     JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
0186     JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
0187     JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
0188     JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
0189     JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
0190     JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
0191     JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
0192     JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
0193     JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
0194     JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
0195     JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
0196     JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
0197     JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
0198     JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
0199     JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
0200     JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
0201     JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
0202     JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
0203     JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
0204     JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
0205     JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
0206             JH7100_CLK_GMAC_GTX,
0207             JH7100_CLK_GMAC_TX_INV,
0208             JH7100_CLK_GMAC_RMII_TX),
0209     JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
0210     JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
0211             JH7100_CLK_GMAC_GR_MII_RX,
0212             JH7100_CLK_GMAC_RMII_RX),
0213     JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
0214     JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
0215     JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
0216     JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
0217     JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
0218     JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
0219     JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
0220     JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
0221     JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
0222     JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
0223     JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
0224     JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
0225     JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
0226     JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
0227     JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
0228     JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
0229     JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
0230     JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
0231     JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
0232     JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
0233     JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
0234     JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
0235     JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
0236     JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
0237     JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
0238     JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
0239     JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
0240     JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
0241     JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
0242     JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
0243     JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
0244     JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
0245     JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
0246     JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
0247     JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
0248     JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
0249     JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
0250     JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
0251     JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
0252     JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
0253     JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
0254     JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
0255     JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
0256     JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
0257     JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
0258     JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
0259     JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
0260     JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
0261     JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
0262     JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
0263     JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
0264     JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
0265     JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
0266     JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
0267     JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
0268     JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
0269     JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
0270 };
0271
0272 static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
0273 {
0274     return container_of(hw, struct jh7100_clk, hw);
0275 }
0276
0277 static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
0278 {
0279     return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
0280 }
0281
0282 static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
0283 {
0284     struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
0285     void __iomem *reg = priv->base + 4 * clk->idx;
0286
0287     return readl_relaxed(reg);
0288 }
0289
0290 static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
0291 {
0292     struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
0293     void __iomem *reg = priv->base + 4 * clk->idx;
0294     unsigned long flags;
0295
0296     spin_lock_irqsave(&priv->rmw_lock, flags);
0297     value |= readl_relaxed(reg) & ~mask;
0298     writel_relaxed(value, reg);
0299     spin_unlock_irqrestore(&priv->rmw_lock, flags);
0300 }
0301
0302 static int jh7100_clk_enable(struct clk_hw *hw)
0303 {
0304     struct jh7100_clk *clk = jh7100_clk_from(hw);
0305
0306     jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
0307     return 0;
0308 }
0309
0310 static void jh7100_clk_disable(struct clk_hw *hw)
0311 {
0312     struct jh7100_clk *clk = jh7100_clk_from(hw);
0313
0314     jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
0315 }
0316
0317 static int jh7100_clk_is_enabled(struct clk_hw *hw)
0318 {
0319     struct jh7100_clk *clk = jh7100_clk_from(hw);
0320
0321     return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
0322 }
0323
0324 static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
0325                         unsigned long parent_rate)
0326 {
0327     struct jh7100_clk *clk = jh7100_clk_from(hw);
0328     u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
0329
0330     return div ? parent_rate / div : 0;
0331 }
0332
0333 static int jh7100_clk_determine_rate(struct clk_hw *hw,
0334                      struct clk_rate_request *req)
0335 {
0336     struct jh7100_clk *clk = jh7100_clk_from(hw);
0337     unsigned long parent = req->best_parent_rate;
0338     unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
0339     unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
0340     unsigned long result = parent / div;
0341
0342     /*
0343      * we want the result clamped by min_rate and max_rate if possible:
0344      * case 1: div hits the max divider value, which means it's less than
0345      * parent / rate, so the result is greater than rate and min_rate in
0346      * particular. we can't do anything about result > max_rate because the
0347      * divider doesn't go any further.
0348      * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
0349      * always lower or equal to rate and max_rate. however the result may
0350      * turn out lower than min_rate, but then the next higher rate is fine:
0351      *   div - 1 = ceil(parent / rate) - 1 < parent / rate
0352      * and thus
0353      *   min_rate <= rate < parent / (div - 1)
0354      */
0355     if (result < req->min_rate && div > 1)
0356         result = parent / (div - 1);
0357
0358     req->rate = result;
0359     return 0;
0360 }
0361
0362 static int jh7100_clk_set_rate(struct clk_hw *hw,
0363                    unsigned long rate,
0364                    unsigned long parent_rate)
0365 {
0366     struct jh7100_clk *clk = jh7100_clk_from(hw);
0367     unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
0368                   1UL, (unsigned long)clk->max_div);
0369
0370     jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
0371     return 0;
0372 }
0373
0374 static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,
0375                          unsigned long parent_rate)
0376 {
0377     struct jh7100_clk *clk = jh7100_clk_from(hw);
0378     u32 reg = jh7100_clk_reg_get(clk);
0379     unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +
0380                    ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);
0381
0382     return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
0383 }
0384
0385 static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,
0386                       struct clk_rate_request *req)
0387 {
0388     unsigned long parent100 = 100 * req->best_parent_rate;
0389     unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
0390     unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
0391                      JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
0392     unsigned long result = parent100 / div100;
0393
0394     /* clamp the result as in jh7100_clk_determine_rate() above */
0395     if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)
0396         result = parent100 / (div100 + 1);
0397     if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)
0398         result = parent100 / (div100 - 1);
0399
0400     req->rate = result;
0401     return 0;
0402 }
0403
0404 static int jh7100_clk_frac_set_rate(struct clk_hw *hw,
0405                     unsigned long rate,
0406                     unsigned long parent_rate)
0407 {
0408     struct jh7100_clk *clk = jh7100_clk_from(hw);
0409     unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
0410                      JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
0411     u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);
0412
0413     jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);
0414     return 0;
0415 }
0416
0417 static u8 jh7100_clk_get_parent(struct clk_hw *hw)
0418 {
0419     struct jh7100_clk *clk = jh7100_clk_from(hw);
0420     u32 value = jh7100_clk_reg_get(clk);
0421
0422     return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
0423 }
0424
0425 static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
0426 {
0427     struct jh7100_clk *clk = jh7100_clk_from(hw);
0428     u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
0429
0430     jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
0431     return 0;
0432 }
0433
0434 static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
0435                      struct clk_rate_request *req)
0436 {
0437     return clk_mux_determine_rate_flags(hw, req, 0);
0438 }
0439
0440 static int jh7100_clk_get_phase(struct clk_hw *hw)
0441 {
0442     struct jh7100_clk *clk = jh7100_clk_from(hw);
0443     u32 value = jh7100_clk_reg_get(clk);
0444
0445     return (value & JH7100_CLK_INVERT) ? 180 : 0;
0446 }
0447
0448 static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
0449 {
0450     struct jh7100_clk *clk = jh7100_clk_from(hw);
0451     u32 value;
0452
0453     if (degrees == 0)
0454         value = 0;
0455     else if (degrees == 180)
0456         value = JH7100_CLK_INVERT;
0457     else
0458         return -EINVAL;
0459
0460     jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
0461     return 0;
0462 }
0463
0464 #ifdef CONFIG_DEBUG_FS
0465 static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
0466 {
0467     static const struct debugfs_reg32 jh7100_clk_reg = {
0468         .name = "CTRL",
0469         .offset = 0,
0470     };
0471     struct jh7100_clk *clk = jh7100_clk_from(hw);
0472     struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
0473     struct debugfs_regset32 *regset;
0474
0475     regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
0476     if (!regset)
0477         return;
0478
0479     regset->regs = &jh7100_clk_reg;
0480     regset->nregs = 1;
0481     regset->base = priv->base + 4 * clk->idx;
0482
0483     debugfs_create_regset32("registers", 0400, dentry, regset);
0484 }
0485 #else
0486 #define jh7100_clk_debug_init NULL
0487 #endif
0488
0489 static const struct clk_ops jh7100_clk_gate_ops = {
0490     .enable = jh7100_clk_enable,
0491     .disable = jh7100_clk_disable,
0492     .is_enabled = jh7100_clk_is_enabled,
0493     .debug_init = jh7100_clk_debug_init,
0494 };
0495
0496 static const struct clk_ops jh7100_clk_div_ops = {
0497     .recalc_rate = jh7100_clk_recalc_rate,
0498     .determine_rate = jh7100_clk_determine_rate,
0499     .set_rate = jh7100_clk_set_rate,
0500     .debug_init = jh7100_clk_debug_init,
0501 };
0502
0503 static const struct clk_ops jh7100_clk_fdiv_ops = {
0504     .recalc_rate = jh7100_clk_frac_recalc_rate,
0505     .determine_rate = jh7100_clk_frac_determine_rate,
0506     .set_rate = jh7100_clk_frac_set_rate,
0507     .debug_init = jh7100_clk_debug_init,
0508 };
0509
0510 static const struct clk_ops jh7100_clk_gdiv_ops = {
0511     .enable = jh7100_clk_enable,
0512     .disable = jh7100_clk_disable,
0513     .is_enabled = jh7100_clk_is_enabled,
0514     .recalc_rate = jh7100_clk_recalc_rate,
0515     .determine_rate = jh7100_clk_determine_rate,
0516     .set_rate = jh7100_clk_set_rate,
0517     .debug_init = jh7100_clk_debug_init,
0518 };
0519
0520 static const struct clk_ops jh7100_clk_mux_ops = {
0521     .determine_rate = jh7100_clk_mux_determine_rate,
0522     .set_parent = jh7100_clk_set_parent,
0523     .get_parent = jh7100_clk_get_parent,
0524     .debug_init = jh7100_clk_debug_init,
0525 };
0526
0527 static const struct clk_ops jh7100_clk_gmux_ops = {
0528     .enable = jh7100_clk_enable,
0529     .disable = jh7100_clk_disable,
0530     .is_enabled = jh7100_clk_is_enabled,
0531     .determine_rate = jh7100_clk_mux_determine_rate,
0532     .set_parent = jh7100_clk_set_parent,
0533     .get_parent = jh7100_clk_get_parent,
0534     .debug_init = jh7100_clk_debug_init,
0535 };
0536
0537 static const struct clk_ops jh7100_clk_mdiv_ops = {
0538     .recalc_rate = jh7100_clk_recalc_rate,
0539     .determine_rate = jh7100_clk_determine_rate,
0540     .get_parent = jh7100_clk_get_parent,
0541     .set_parent = jh7100_clk_set_parent,
0542     .set_rate = jh7100_clk_set_rate,
0543     .debug_init = jh7100_clk_debug_init,
0544 };
0545
0546 static const struct clk_ops jh7100_clk_gmd_ops = {
0547     .enable = jh7100_clk_enable,
0548     .disable = jh7100_clk_disable,
0549     .is_enabled = jh7100_clk_is_enabled,
0550     .recalc_rate = jh7100_clk_recalc_rate,
0551     .determine_rate = jh7100_clk_determine_rate,
0552     .get_parent = jh7100_clk_get_parent,
0553     .set_parent = jh7100_clk_set_parent,
0554     .set_rate = jh7100_clk_set_rate,
0555     .debug_init = jh7100_clk_debug_init,
0556 };
0557
0558 static const struct clk_ops jh7100_clk_inv_ops = {
0559     .get_phase = jh7100_clk_get_phase,
0560     .set_phase = jh7100_clk_set_phase,
0561     .debug_init = jh7100_clk_debug_init,
0562 };
0563
0564 const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
0565 {
0566     if (max & JH7100_CLK_DIV_MASK) {
0567         if (max & JH7100_CLK_MUX_MASK) {
0568             if (max & JH7100_CLK_ENABLE)
0569                 return &jh7100_clk_gmd_ops;
0570             return &jh7100_clk_mdiv_ops;
0571         }
0572         if (max & JH7100_CLK_ENABLE)
0573             return &jh7100_clk_gdiv_ops;
0574         if (max == JH7100_CLK_FRAC_MAX)
0575             return &jh7100_clk_fdiv_ops;
0576         return &jh7100_clk_div_ops;
0577     }
0578
0579     if (max & JH7100_CLK_MUX_MASK) {
0580         if (max & JH7100_CLK_ENABLE)
0581             return &jh7100_clk_gmux_ops;
0582         return &jh7100_clk_mux_ops;
0583     }
0584
0585     if (max & JH7100_CLK_ENABLE)
0586         return &jh7100_clk_gate_ops;
0587
0588     return &jh7100_clk_inv_ops;
0589 }
0590 EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
0591
0592 static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
0593 {
0594     struct jh7100_clk_priv *priv = data;
0595     unsigned int idx = clkspec->args[0];
0596
0597     if (idx < JH7100_CLK_PLL0_OUT)
0598         return &priv->reg[idx].hw;
0599
0600     if (idx < JH7100_CLK_END)
0601         return priv->pll[idx - JH7100_CLK_PLL0_OUT];
0602
0603     return ERR_PTR(-EINVAL);
0604 }
0605
0606 static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
0607 {
0608     struct jh7100_clk_priv *priv;
0609     unsigned int idx;
0610     int ret;
0611
0612     priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_CLK_PLL0_OUT), GFP_KERNEL);
0613     if (!priv)
0614         return -ENOMEM;
0615
0616     spin_lock_init(&priv->rmw_lock);
0617     priv->dev = &pdev->dev;
0618     priv->base = devm_platform_ioremap_resource(pdev, 0);
0619     if (IS_ERR(priv->base))
0620         return PTR_ERR(priv->base);
0621
0622     priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
0623                              "osc_sys", 0, 40, 1);
0624     if (IS_ERR(priv->pll[0]))
0625         return PTR_ERR(priv->pll[0]);
0626
0627     priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
0628                              "osc_sys", 0, 64, 1);
0629     if (IS_ERR(priv->pll[1]))
0630         return PTR_ERR(priv->pll[1]);
0631
0632     priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
0633                              "pll2_refclk", 0, 55, 1);
0634     if (IS_ERR(priv->pll[2]))
0635         return PTR_ERR(priv->pll[2]);
0636
0637     for (idx = 0; idx < JH7100_CLK_PLL0_OUT; idx++) {
0638         u32 max = jh7100_clk_data[idx].max;
0639         struct clk_parent_data parents[4] = {};
0640         struct clk_init_data init = {
0641             .name = jh7100_clk_data[idx].name,
0642             .ops = starfive_jh7100_clk_ops(max),
0643             .parent_data = parents,
0644             .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
0645             .flags = jh7100_clk_data[idx].flags,
0646         };
0647         struct jh7100_clk *clk = &priv->reg[idx];
0648         unsigned int i;
0649
0650         for (i = 0; i < init.num_parents; i++) {
0651             unsigned int pidx = jh7100_clk_data[idx].parents[i];
0652
0653             if (pidx < JH7100_CLK_PLL0_OUT)
0654                 parents[i].hw = &priv->reg[pidx].hw;
0655             else if (pidx < JH7100_CLK_END)
0656                 parents[i].hw = priv->pll[pidx - JH7100_CLK_PLL0_OUT];
0657             else if (pidx == JH7100_CLK_OSC_SYS)
0658                 parents[i].fw_name = "osc_sys";
0659             else if (pidx == JH7100_CLK_OSC_AUD)
0660                 parents[i].fw_name = "osc_aud";
0661             else if (pidx == JH7100_CLK_GMAC_RMII_REF)
0662                 parents[i].fw_name = "gmac_rmii_ref";
0663             else if (pidx == JH7100_CLK_GMAC_GR_MII_RX)
0664                 parents[i].fw_name = "gmac_gr_mii_rxclk";
0665         }
0666
0667         clk->hw.init = &init;
0668         clk->idx = idx;
0669         clk->max_div = max & JH7100_CLK_DIV_MASK;
0670
0671         ret = devm_clk_hw_register(priv->dev, &clk->hw);
0672         if (ret)
0673             return ret;
0674     }
0675
0676     return devm_of_clk_add_hw_provider(priv->dev, jh7100_clk_get, priv);
0677 }
0678
0679 static const struct of_device_id clk_starfive_jh7100_match[] = {
0680     { .compatible = "starfive,jh7100-clkgen" },
0681     { /* sentinel */ }
0682 };
0683
0684 static struct platform_driver clk_starfive_jh7100_driver = {
0685     .driver = {
0686         .name = "clk-starfive-jh7100",
0687         .of_match_table = clk_starfive_jh7100_match,
0688         .suppress_bind_attrs = true,
0689     },
0690 };
0691 builtin_platform_driver_probe(clk_starfive_jh7100_driver, clk_starfive_jh7100_probe);