clk/starfive/clk-starfive-jh7100-audio.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * StarFive JH7100 Audio Clock Driver
0004  *
0005  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
0006  */
0007
0008 #include <linux/bits.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/device.h>
0011 #include <linux/kernel.h>
0012 #include <linux/mod_devicetable.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/platform_device.h>
0016
0017 #include <dt-bindings/clock/starfive-jh7100-audio.h>
0018
0019 #include "clk-starfive-jh7100.h"
0020
0021 /* external clocks */
0022 #define JH7100_AUDCLK_AUDIO_SRC         (JH7100_AUDCLK_END + 0)
0023 #define JH7100_AUDCLK_AUDIO_12288       (JH7100_AUDCLK_END + 1)
0024 #define JH7100_AUDCLK_DOM7AHB_BUS       (JH7100_AUDCLK_END + 2)
0025 #define JH7100_AUDCLK_I2SADC_BCLK_IOPAD     (JH7100_AUDCLK_END + 3)
0026 #define JH7100_AUDCLK_I2SADC_LRCLK_IOPAD    (JH7100_AUDCLK_END + 4)
0027 #define JH7100_AUDCLK_I2SDAC_BCLK_IOPAD     (JH7100_AUDCLK_END + 5)
0028 #define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD    (JH7100_AUDCLK_END + 6)
0029 #define JH7100_AUDCLK_VAD_INTMEM                (JH7100_AUDCLK_END + 7)
0030
0031 static const struct jh7100_clk_data jh7100_audclk_data[] = {
0032     JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
0033             JH7100_AUDCLK_AUDIO_SRC,
0034             JH7100_AUDCLK_AUDIO_12288),
0035     JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
0036             JH7100_AUDCLK_AUDIO_SRC,
0037             JH7100_AUDCLK_AUDIO_12288),
0038     JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
0039     JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
0040             JH7100_AUDCLK_ADC_MCLK,
0041             JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
0042     JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
0043     JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
0044             JH7100_AUDCLK_I2SADC_BCLK_N,
0045             JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
0046             JH7100_AUDCLK_I2SADC_BCLK),
0047     JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
0048     JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
0049             JH7100_AUDCLK_AUDIO_SRC,
0050             JH7100_AUDCLK_AUDIO_12288),
0051     JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
0052     JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
0053             JH7100_AUDCLK_AUDIO_SRC,
0054             JH7100_AUDCLK_AUDIO_12288),
0055     JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
0056     JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
0057     JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
0058             JH7100_AUDCLK_AUDIO_SRC,
0059             JH7100_AUDCLK_AUDIO_12288),
0060     JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
0061     JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
0062             JH7100_AUDCLK_DAC_MCLK,
0063             JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
0064     JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
0065     JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
0066             JH7100_AUDCLK_I2S1_MCLK,
0067             JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
0068     JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
0069     JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
0070             JH7100_AUDCLK_I2S1_MCLK,
0071             JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
0072     JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
0073     JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
0074             JH7100_AUDCLK_I2S1_BCLK_N,
0075             JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
0076     JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
0077     JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
0078     JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
0079     JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
0080     JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
0081     JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
0082     JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
0083     JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
0084             JH7100_AUDCLK_VAD_INTMEM,
0085             JH7100_AUDCLK_AUDIO_12288),
0086 };
0087
0088 static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
0089 {
0090     struct jh7100_clk_priv *priv = data;
0091     unsigned int idx = clkspec->args[0];
0092
0093     if (idx < JH7100_AUDCLK_END)
0094         return &priv->reg[idx].hw;
0095
0096     return ERR_PTR(-EINVAL);
0097 }
0098
0099 static int jh7100_audclk_probe(struct platform_device *pdev)
0100 {
0101     struct jh7100_clk_priv *priv;
0102     unsigned int idx;
0103     int ret;
0104
0105     priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_AUDCLK_END), GFP_KERNEL);
0106     if (!priv)
0107         return -ENOMEM;
0108
0109     spin_lock_init(&priv->rmw_lock);
0110     priv->dev = &pdev->dev;
0111     priv->base = devm_platform_ioremap_resource(pdev, 0);
0112     if (IS_ERR(priv->base))
0113         return PTR_ERR(priv->base);
0114
0115     for (idx = 0; idx < JH7100_AUDCLK_END; idx++) {
0116         u32 max = jh7100_audclk_data[idx].max;
0117         struct clk_parent_data parents[4] = {};
0118         struct clk_init_data init = {
0119             .name = jh7100_audclk_data[idx].name,
0120             .ops = starfive_jh7100_clk_ops(max),
0121             .parent_data = parents,
0122             .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
0123             .flags = jh7100_audclk_data[idx].flags,
0124         };
0125         struct jh7100_clk *clk = &priv->reg[idx];
0126         unsigned int i;
0127
0128         for (i = 0; i < init.num_parents; i++) {
0129             unsigned int pidx = jh7100_audclk_data[idx].parents[i];
0130
0131             if (pidx < JH7100_AUDCLK_END)
0132                 parents[i].hw = &priv->reg[pidx].hw;
0133             else if (pidx == JH7100_AUDCLK_AUDIO_SRC)
0134                 parents[i].fw_name = "audio_src";
0135             else if (pidx == JH7100_AUDCLK_AUDIO_12288)
0136                 parents[i].fw_name = "audio_12288";
0137             else if (pidx == JH7100_AUDCLK_DOM7AHB_BUS)
0138                 parents[i].fw_name = "dom7ahb_bus";
0139         }
0140
0141         clk->hw.init = &init;
0142         clk->idx = idx;
0143         clk->max_div = max & JH7100_CLK_DIV_MASK;
0144
0145         ret = devm_clk_hw_register(priv->dev, &clk->hw);
0146         if (ret)
0147             return ret;
0148     }
0149
0150     return devm_of_clk_add_hw_provider(priv->dev, jh7100_audclk_get, priv);
0151 }
0152
0153 static const struct of_device_id jh7100_audclk_match[] = {
0154     { .compatible = "starfive,jh7100-audclk" },
0155     { /* sentinel */ }
0156 };
0157 MODULE_DEVICE_TABLE(of, jh7100_audclk_match);
0158
0159 static struct platform_driver jh7100_audclk_driver = {
0160     .probe = jh7100_audclk_probe,
0161     .driver = {
0162         .name = "clk-starfive-jh7100-audio",
0163         .of_match_table = jh7100_audclk_match,
0164     },
0165 };
0166 module_platform_driver(jh7100_audclk_driver);
0167
0168 MODULE_AUTHOR("Emil Renner Berthing");
0169 MODULE_DESCRIPTION("StarFive JH7100 audio clock driver");
0170 MODULE_LICENSE("GPL v2");