clk/sprd/sc9860-clk.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Spreatrum SC9860 clock driver
0004 //
0005 // Copyright (C) 2017 Spreadtrum, Inc.
0006 // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/slab.h>
0015
0016 #include <dt-bindings/clock/sprd,sc9860-clk.h>
0017
0018 #include "common.h"
0019 #include "composite.h"
0020 #include "div.h"
0021 #include "gate.h"
0022 #include "mux.h"
0023 #include "pll.h"
0024
0025 static CLK_FIXED_FACTOR(fac_4m,     "fac-4m",   "ext-26m",
0026             6, 1, 0);
0027 static CLK_FIXED_FACTOR(fac_2m,     "fac-2m",   "ext-26m",
0028             13, 1, 0);
0029 static CLK_FIXED_FACTOR(fac_1m,     "fac-1m",   "ext-26m",
0030             26, 1, 0);
0031 static CLK_FIXED_FACTOR(fac_250k,   "fac-250k", "ext-26m",
0032             104, 1, 0);
0033 static CLK_FIXED_FACTOR(fac_rpll0_26m,  "rpll0-26m",    "ext-26m",
0034             1, 1, 0);
0035 static CLK_FIXED_FACTOR(fac_rpll1_26m,  "rpll1-26m",    "ext-26m",
0036             1, 1, 0);
0037 static CLK_FIXED_FACTOR(fac_rco_25m,    "rco-25m",  "ext-rc0-100m",
0038             4, 1, 0);
0039 static CLK_FIXED_FACTOR(fac_rco_4m, "rco-4m",   "ext-rc0-100m",
0040             25, 1, 0);
0041 static CLK_FIXED_FACTOR(fac_rco_2m, "rco-2m",   "ext-rc0-100m",
0042             50, 1, 0);
0043 static CLK_FIXED_FACTOR(fac_3k2,    "fac-3k2",  "ext-32k",
0044             10, 1, 0);
0045 static CLK_FIXED_FACTOR(fac_1k,     "fac-1k",   "ext-32k",
0046             32, 1, 0);
0047
0048 static SPRD_SC_GATE_CLK(mpll0_gate, "mpll0-gate",   "ext-26m", 0xb0,
0049              0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
0050 static SPRD_SC_GATE_CLK(mpll1_gate, "mpll1-gate",   "ext-26m", 0xb0,
0051              0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
0052 static SPRD_SC_GATE_CLK(dpll0_gate, "dpll0-gate",   "ext-26m", 0xb4,
0053              0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
0054 static SPRD_SC_GATE_CLK(dpll1_gate, "dpll1-gate",   "ext-26m", 0xb4,
0055              0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
0056 static SPRD_SC_GATE_CLK(ltepll0_gate,   "ltepll0-gate", "ext-26m", 0xb8,
0057              0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
0058 static SPRD_SC_GATE_CLK(twpll_gate, "twpll-gate",   "ext-26m", 0xbc,
0059              0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
0060 static SPRD_SC_GATE_CLK(ltepll1_gate,   "ltepll1-gate", "ext-26m", 0x10c,
0061              0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
0062 static SPRD_SC_GATE_CLK(rpll0_gate, "rpll0-gate",   "ext-26m", 0x16c,
0063              0x1000, BIT(2), 0, 0);
0064 static SPRD_SC_GATE_CLK(rpll1_gate, "rpll1-gate",   "ext-26m", 0x16c,
0065              0x1000, BIT(18), 0, 0);
0066 static SPRD_SC_GATE_CLK(cppll_gate, "cppll-gate",   "ext-26m", 0x2b4,
0067              0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
0068 static SPRD_SC_GATE_CLK(gpll_gate,  "gpll-gate",    "ext-26m", 0x32c,
0069         0x1000, BIT(0), CLK_IGNORE_UNUSED, CLK_GATE_SET_TO_DISABLE);
0070
0071 static struct sprd_clk_common *sc9860_pmu_gate_clks[] = {
0072     /* address base is 0x402b0000 */
0073     &mpll0_gate.common,
0074     &mpll1_gate.common,
0075     &dpll0_gate.common,
0076     &dpll1_gate.common,
0077     &ltepll0_gate.common,
0078     &twpll_gate.common,
0079     &ltepll1_gate.common,
0080     &rpll0_gate.common,
0081     &rpll1_gate.common,
0082     &cppll_gate.common,
0083     &gpll_gate.common,
0084 };
0085
0086 static struct clk_hw_onecell_data sc9860_pmu_gate_hws = {
0087     .hws    = {
0088         [CLK_FAC_4M]        = &fac_4m.hw,
0089         [CLK_FAC_2M]        = &fac_2m.hw,
0090         [CLK_FAC_1M]        = &fac_1m.hw,
0091         [CLK_FAC_250K]      = &fac_250k.hw,
0092         [CLK_FAC_RPLL0_26M] = &fac_rpll0_26m.hw,
0093         [CLK_FAC_RPLL1_26M] = &fac_rpll1_26m.hw,
0094         [CLK_FAC_RCO25M]    = &fac_rco_25m.hw,
0095         [CLK_FAC_RCO4M]     = &fac_rco_4m.hw,
0096         [CLK_FAC_RCO2M]     = &fac_rco_2m.hw,
0097         [CLK_FAC_3K2]       = &fac_3k2.hw,
0098         [CLK_FAC_1K]        = &fac_1k.hw,
0099         [CLK_MPLL0_GATE]    = &mpll0_gate.common.hw,
0100         [CLK_MPLL1_GATE]    = &mpll1_gate.common.hw,
0101         [CLK_DPLL0_GATE]    = &dpll0_gate.common.hw,
0102         [CLK_DPLL1_GATE]    = &dpll1_gate.common.hw,
0103         [CLK_LTEPLL0_GATE]  = &ltepll0_gate.common.hw,
0104         [CLK_TWPLL_GATE]    = &twpll_gate.common.hw,
0105         [CLK_LTEPLL1_GATE]  = &ltepll1_gate.common.hw,
0106         [CLK_RPLL0_GATE]    = &rpll0_gate.common.hw,
0107         [CLK_RPLL1_GATE]    = &rpll1_gate.common.hw,
0108         [CLK_CPPLL_GATE]    = &cppll_gate.common.hw,
0109         [CLK_GPLL_GATE]     = &gpll_gate.common.hw,
0110     },
0111     .num    = CLK_PMU_GATE_NUM,
0112 };
0113
0114 static const struct sprd_clk_desc sc9860_pmu_gate_desc = {
0115     .clk_clks   = sc9860_pmu_gate_clks,
0116     .num_clk_clks   = ARRAY_SIZE(sc9860_pmu_gate_clks),
0117     .hw_clks        = &sc9860_pmu_gate_hws,
0118 };
0119
0120 /* GPLL/LPLL/DPLL/RPLL/CPLL */
0121 static const u64 itable1[4] = {3, 780000000, 988000000, 1196000000};
0122
0123 /* TWPLL/MPLL0/MPLL1 */
0124 static const u64 itable2[4] = {3, 1638000000, 2080000000, 2600000000UL};
0125
0126 static const struct clk_bit_field f_mpll0[PLL_FACT_MAX] = {
0127     { .shift = 20,  .width = 1 },   /* lock_done    */
0128     { .shift = 19,  .width = 1 },   /* div_s    */
0129     { .shift = 18,  .width = 1 },   /* mod_en   */
0130     { .shift = 17,  .width = 1 },   /* sdm_en   */
0131     { .shift = 0,   .width = 0 },   /* refin    */
0132     { .shift = 11,  .width = 2 },   /* ibias    */
0133     { .shift = 0,   .width = 7 },   /* n        */
0134     { .shift = 57,  .width = 7 },   /* nint     */
0135     { .shift = 32,  .width = 23},   /* kint     */
0136     { .shift = 0,   .width = 0 },   /* prediv   */
0137     { .shift = 56,  .width = 1 },   /* postdiv  */
0138 };
0139 static SPRD_PLL_WITH_ITABLE_K_FVCO(mpll0_clk, "mpll0", "mpll0-gate", 0x24,
0140                    2, itable2, f_mpll0, 200,
0141                    1000, 1000, 1, 1300000000);
0142
0143 static const struct clk_bit_field f_mpll1[PLL_FACT_MAX] = {
0144     { .shift = 20,  .width = 1 },   /* lock_done    */
0145     { .shift = 19,  .width = 1 },   /* div_s    */
0146     { .shift = 18,  .width = 1 },   /* mod_en   */
0147     { .shift = 17,  .width = 1 },   /* sdm_en   */
0148     { .shift = 0,   .width = 0 },   /* refin    */
0149     { .shift = 11,  .width = 2 },   /* ibias    */
0150     { .shift = 0,   .width = 7 },   /* n        */
0151     { .shift = 57,  .width = 7 },   /* nint     */
0152     { .shift = 32,  .width = 23},   /* kint     */
0153     { .shift = 56,  .width = 1 },   /* prediv   */
0154     { .shift = 0,   .width = 0 },   /* postdiv  */
0155 };
0156 static SPRD_PLL_WITH_ITABLE_1K(mpll1_clk, "mpll1", "mpll1-gate", 0x2c,
0157                    2, itable2, f_mpll1, 200);
0158
0159 static const struct clk_bit_field f_dpll[PLL_FACT_MAX] = {
0160     { .shift = 16,  .width = 1 },   /* lock_done    */
0161     { .shift = 15,  .width = 1 },   /* div_s    */
0162     { .shift = 14,  .width = 1 },   /* mod_en   */
0163     { .shift = 13,  .width = 1 },   /* sdm_en   */
0164     { .shift = 0,   .width = 0 },   /* refin    */
0165     { .shift = 8,   .width = 2 },   /* ibias    */
0166     { .shift = 0,   .width = 7 },   /* n        */
0167     { .shift = 57,  .width = 7 },   /* nint     */
0168     { .shift = 32,  .width = 23},   /* kint     */
0169     { .shift = 0,   .width = 0 },   /* prediv   */
0170     { .shift = 0,   .width = 0 },   /* postdiv  */
0171 };
0172 static SPRD_PLL_WITH_ITABLE_1K(dpll0_clk, "dpll0", "dpll0-gate", 0x34,
0173                    2, itable1, f_dpll, 200);
0174
0175 static SPRD_PLL_WITH_ITABLE_1K(dpll1_clk, "dpll1", "dpll1-gate", 0x3c,
0176                    2, itable1, f_dpll, 200);
0177
0178 static const struct clk_bit_field f_rpll[PLL_FACT_MAX] = {
0179     { .shift = 0,   .width = 1 },   /* lock_done    */
0180     { .shift = 3,   .width = 1 },   /* div_s    */
0181     { .shift = 80,  .width = 1 },   /* mod_en   */
0182     { .shift = 81,  .width = 1 },   /* sdm_en   */
0183     { .shift = 0,   .width = 0 },   /* refin    */
0184     { .shift = 14,  .width = 2 },   /* ibias    */
0185     { .shift = 16,  .width = 7 },   /* n        */
0186     { .shift = 4,   .width = 7 },   /* nint     */
0187     { .shift = 32,  .width = 23},   /* kint     */
0188     { .shift = 0,   .width = 0 },   /* prediv   */
0189     { .shift = 0,   .width = 0 },   /* postdiv  */
0190 };
0191 static SPRD_PLL_WITH_ITABLE_1K(rpll0_clk, "rpll0", "rpll0-gate", 0x44,
0192                    3, itable1, f_rpll, 200);
0193
0194 static SPRD_PLL_WITH_ITABLE_1K(rpll1_clk, "rpll1", "rpll1-gate", 0x50,
0195                    3, itable1, f_rpll, 200);
0196
0197 static const struct clk_bit_field f_twpll[PLL_FACT_MAX] = {
0198     { .shift = 21,  .width = 1 },   /* lock_done    */
0199     { .shift = 20,  .width = 1 },   /* div_s    */
0200     { .shift = 19,  .width = 1 },   /* mod_en   */
0201     { .shift = 18,  .width = 1 },   /* sdm_en   */
0202     { .shift = 0,   .width = 0 },   /* refin    */
0203     { .shift = 13,  .width = 2 },   /* ibias    */
0204     { .shift = 0,   .width = 7 },   /* n        */
0205     { .shift = 57,  .width = 7 },   /* nint     */
0206     { .shift = 32,  .width = 23},   /* kint     */
0207     { .shift = 0,   .width = 0 },   /* prediv   */
0208     { .shift = 0,   .width = 0 },   /* postdiv  */
0209 };
0210 static SPRD_PLL_WITH_ITABLE_1K(twpll_clk, "twpll", "twpll-gate", 0x5c,
0211                    2, itable2, f_twpll, 200);
0212
0213 static const struct clk_bit_field f_ltepll[PLL_FACT_MAX] = {
0214     { .shift = 31,  .width = 1 },   /* lock_done    */
0215     { .shift = 27,  .width = 1 },   /* div_s    */
0216     { .shift = 26,  .width = 1 },   /* mod_en   */
0217     { .shift = 25,  .width = 1 },   /* sdm_en   */
0218     { .shift = 0,   .width = 0 },   /* refin    */
0219     { .shift = 20,  .width = 2 },   /* ibias    */
0220     { .shift = 0,   .width = 7 },   /* n        */
0221     { .shift = 57,  .width = 7 },   /* nint     */
0222     { .shift = 32,  .width = 23},   /* kint     */
0223     { .shift = 0,   .width = 0 },   /* prediv   */
0224     { .shift = 0,   .width = 0 },   /* postdiv  */
0225 };
0226 static SPRD_PLL_WITH_ITABLE_1K(ltepll0_clk, "ltepll0", "ltepll0-gate",
0227                    0x64, 2, itable1,
0228                    f_ltepll, 200);
0229 static SPRD_PLL_WITH_ITABLE_1K(ltepll1_clk, "ltepll1", "ltepll1-gate",
0230                    0x6c, 2, itable1,
0231                    f_ltepll, 200);
0232
0233 static const struct clk_bit_field f_gpll[PLL_FACT_MAX] = {
0234     { .shift = 18,  .width = 1 },   /* lock_done    */
0235     { .shift = 15,  .width = 1 },   /* div_s    */
0236     { .shift = 14,  .width = 1 },   /* mod_en   */
0237     { .shift = 13,  .width = 1 },   /* sdm_en   */
0238     { .shift = 0,   .width = 0 },   /* refin    */
0239     { .shift = 8,   .width = 2 },   /* ibias    */
0240     { .shift = 0,   .width = 7 },   /* n        */
0241     { .shift = 57,  .width = 7 },   /* nint     */
0242     { .shift = 32,  .width = 23},   /* kint     */
0243     { .shift = 0,   .width = 0 },   /* prediv   */
0244     { .shift = 17,  .width = 1 },   /* postdiv  */
0245 };
0246 static SPRD_PLL_WITH_ITABLE_K_FVCO(gpll_clk, "gpll", "gpll-gate", 0x9c,
0247                    2, itable1, f_gpll, 200,
0248                    1000, 1000, 1, 600000000);
0249
0250 static const struct clk_bit_field f_cppll[PLL_FACT_MAX] = {
0251     { .shift = 17,  .width = 1 },   /* lock_done    */
0252     { .shift = 15,  .width = 1 },   /* div_s    */
0253     { .shift = 14,  .width = 1 },   /* mod_en   */
0254     { .shift = 13,  .width = 1 },   /* sdm_en   */
0255     { .shift = 0,   .width = 0 },   /* refin    */
0256     { .shift = 8,   .width = 2 },   /* ibias    */
0257     { .shift = 0,   .width = 7 },   /* n        */
0258     { .shift = 57,  .width = 7 },   /* nint     */
0259     { .shift = 32,  .width = 23},   /* kint     */
0260     { .shift = 0,   .width = 0 },   /* prediv   */
0261     { .shift = 0,   .width = 0 },   /* postdiv  */
0262 };
0263 static SPRD_PLL_WITH_ITABLE_1K(cppll_clk, "cppll", "cppll-gate", 0xc4,
0264                    2, itable1, f_cppll, 200);
0265
0266 static CLK_FIXED_FACTOR(gpll_42m5, "gpll-42m5", "gpll", 20, 1, 0);
0267 static CLK_FIXED_FACTOR(twpll_768m, "twpll-768m", "twpll", 2, 1, 0);
0268 static CLK_FIXED_FACTOR(twpll_384m, "twpll-384m", "twpll", 4, 1, 0);
0269 static CLK_FIXED_FACTOR(twpll_192m, "twpll-192m", "twpll", 8, 1, 0);
0270 static CLK_FIXED_FACTOR(twpll_96m, "twpll-96m", "twpll", 16, 1, 0);
0271 static CLK_FIXED_FACTOR(twpll_48m, "twpll-48m", "twpll", 32, 1, 0);
0272 static CLK_FIXED_FACTOR(twpll_24m, "twpll-24m", "twpll", 64, 1, 0);
0273 static CLK_FIXED_FACTOR(twpll_12m, "twpll-12m", "twpll", 128, 1, 0);
0274 static CLK_FIXED_FACTOR(twpll_512m, "twpll-512m", "twpll", 3, 1, 0);
0275 static CLK_FIXED_FACTOR(twpll_256m, "twpll-256m", "twpll", 6, 1, 0);
0276 static CLK_FIXED_FACTOR(twpll_128m, "twpll-128m", "twpll", 12, 1, 0);
0277 static CLK_FIXED_FACTOR(twpll_64m, "twpll-64m", "twpll", 24, 1, 0);
0278 static CLK_FIXED_FACTOR(twpll_307m2, "twpll-307m2", "twpll", 5, 1, 0);
0279 static CLK_FIXED_FACTOR(twpll_153m6, "twpll-153m6", "twpll", 10, 1, 0);
0280 static CLK_FIXED_FACTOR(twpll_76m8, "twpll-76m8", "twpll", 20, 1, 0);
0281 static CLK_FIXED_FACTOR(twpll_51m2, "twpll-51m2", "twpll", 30, 1, 0);
0282 static CLK_FIXED_FACTOR(twpll_38m4, "twpll-38m4", "twpll", 40, 1, 0);
0283 static CLK_FIXED_FACTOR(twpll_19m2, "twpll-19m2", "twpll", 80, 1, 0);
0284 static CLK_FIXED_FACTOR(l0_614m4, "l0-614m4", "ltepll0", 2, 1, 0);
0285 static CLK_FIXED_FACTOR(l0_409m6, "l0-409m6", "ltepll0", 3, 1, 0);
0286 static CLK_FIXED_FACTOR(l0_38m, "l0-38m", "ltepll0", 32, 1, 0);
0287 static CLK_FIXED_FACTOR(l1_38m, "l1-38m", "ltepll1", 32, 1, 0);
0288 static CLK_FIXED_FACTOR(rpll0_192m, "rpll0-192m", "rpll0", 6, 1, 0);
0289 static CLK_FIXED_FACTOR(rpll0_96m, "rpll0-96m", "rpll0", 12, 1, 0);
0290 static CLK_FIXED_FACTOR(rpll0_48m, "rpll0-48m", "rpll0", 24, 1, 0);
0291 static CLK_FIXED_FACTOR(rpll1_468m, "rpll1-468m", "rpll1", 2, 1, 0);
0292 static CLK_FIXED_FACTOR(rpll1_192m, "rpll1-192m", "rpll1", 6, 1, 0);
0293 static CLK_FIXED_FACTOR(rpll1_96m, "rpll1-96m", "rpll1", 12, 1, 0);
0294 static CLK_FIXED_FACTOR(rpll1_64m, "rpll1-64m", "rpll1", 18, 1, 0);
0295 static CLK_FIXED_FACTOR(rpll1_48m, "rpll1-48m", "rpll1", 24, 1, 0);
0296 static CLK_FIXED_FACTOR(dpll0_50m, "dpll0-50m", "dpll0", 16, 1, 0);
0297 static CLK_FIXED_FACTOR(dpll1_50m, "dpll1-50m", "dpll1", 16, 1, 0);
0298 static CLK_FIXED_FACTOR(cppll_50m, "cppll-50m", "cppll", 18, 1, 0);
0299 static CLK_FIXED_FACTOR(m0_39m, "m0-39m", "mpll0", 32, 1, 0);
0300 static CLK_FIXED_FACTOR(m1_63m, "m1-63m", "mpll1", 32, 1, 0);
0301
0302 static struct sprd_clk_common *sc9860_pll_clks[] = {
0303     /* address base is 0x40400000 */
0304     &mpll0_clk.common,
0305     &mpll1_clk.common,
0306     &dpll0_clk.common,
0307     &dpll1_clk.common,
0308     &rpll0_clk.common,
0309     &rpll1_clk.common,
0310     &twpll_clk.common,
0311     &ltepll0_clk.common,
0312     &ltepll1_clk.common,
0313     &gpll_clk.common,
0314     &cppll_clk.common,
0315 };
0316
0317 static struct clk_hw_onecell_data sc9860_pll_hws = {
0318     .hws    = {
0319         [CLK_MPLL0]     = &mpll0_clk.common.hw,
0320         [CLK_MPLL1]     = &mpll1_clk.common.hw,
0321         [CLK_DPLL0]     = &dpll0_clk.common.hw,
0322         [CLK_DPLL1]     = &dpll1_clk.common.hw,
0323         [CLK_RPLL0]     = &rpll0_clk.common.hw,
0324         [CLK_RPLL1]     = &rpll1_clk.common.hw,
0325         [CLK_TWPLL]     = &twpll_clk.common.hw,
0326         [CLK_LTEPLL0]       = &ltepll0_clk.common.hw,
0327         [CLK_LTEPLL1]       = &ltepll1_clk.common.hw,
0328         [CLK_GPLL]      = &gpll_clk.common.hw,
0329         [CLK_CPPLL]     = &cppll_clk.common.hw,
0330         [CLK_GPLL_42M5]     = &gpll_42m5.hw,
0331         [CLK_TWPLL_768M]    = &twpll_768m.hw,
0332         [CLK_TWPLL_384M]    = &twpll_384m.hw,
0333         [CLK_TWPLL_192M]    = &twpll_192m.hw,
0334         [CLK_TWPLL_96M]     = &twpll_96m.hw,
0335         [CLK_TWPLL_48M]     = &twpll_48m.hw,
0336         [CLK_TWPLL_24M]     = &twpll_24m.hw,
0337         [CLK_TWPLL_12M]     = &twpll_12m.hw,
0338         [CLK_TWPLL_512M]    = &twpll_512m.hw,
0339         [CLK_TWPLL_256M]    = &twpll_256m.hw,
0340         [CLK_TWPLL_128M]    = &twpll_128m.hw,
0341         [CLK_TWPLL_64M]     = &twpll_64m.hw,
0342         [CLK_TWPLL_307M2]   = &twpll_307m2.hw,
0343         [CLK_TWPLL_153M6]   = &twpll_153m6.hw,
0344         [CLK_TWPLL_76M8]    = &twpll_76m8.hw,
0345         [CLK_TWPLL_51M2]    = &twpll_51m2.hw,
0346         [CLK_TWPLL_38M4]    = &twpll_38m4.hw,
0347         [CLK_TWPLL_19M2]    = &twpll_19m2.hw,
0348         [CLK_L0_614M4]      = &l0_614m4.hw,
0349         [CLK_L0_409M6]      = &l0_409m6.hw,
0350         [CLK_L0_38M]        = &l0_38m.hw,
0351         [CLK_L1_38M]        = &l1_38m.hw,
0352         [CLK_RPLL0_192M]    = &rpll0_192m.hw,
0353         [CLK_RPLL0_96M]     = &rpll0_96m.hw,
0354         [CLK_RPLL0_48M]     = &rpll0_48m.hw,
0355         [CLK_RPLL1_468M]    = &rpll1_468m.hw,
0356         [CLK_RPLL1_192M]    = &rpll1_192m.hw,
0357         [CLK_RPLL1_96M]     = &rpll1_96m.hw,
0358         [CLK_RPLL1_64M]     = &rpll1_64m.hw,
0359         [CLK_RPLL1_48M]     = &rpll1_48m.hw,
0360         [CLK_DPLL0_50M]     = &dpll0_50m.hw,
0361         [CLK_DPLL1_50M]     = &dpll1_50m.hw,
0362         [CLK_CPPLL_50M]     = &cppll_50m.hw,
0363         [CLK_M0_39M]        = &m0_39m.hw,
0364         [CLK_M1_63M]        = &m1_63m.hw,
0365     },
0366     .num    = CLK_PLL_NUM,
0367 };
0368
0369 static const struct sprd_clk_desc sc9860_pll_desc = {
0370     .clk_clks   = sc9860_pll_clks,
0371     .num_clk_clks   = ARRAY_SIZE(sc9860_pll_clks),
0372     .hw_clks    = &sc9860_pll_hws,
0373 };
0374
0375 #define SC9860_MUX_FLAG \
0376     (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)
0377
0378 static const char * const ap_apb_parents[] = { "ext-26m", "twpll-64m",
0379                            "twpll-96m", "twpll-128m" };
0380 static SPRD_MUX_CLK(ap_apb, "ap-apb", ap_apb_parents,
0381             0x20, 0, 1, SC9860_MUX_FLAG);
0382
0383 static const char * const ap_apb_usb3[] = { "ext-32k", "twpll-24m" };
0384 static SPRD_MUX_CLK(ap_usb3, "ap-usb3", ap_apb_usb3,
0385             0x2c, 0, 1, SC9860_MUX_FLAG);
0386
0387 static const char * const uart_parents[] = {    "ext-26m",  "twpll-48m",
0388                         "twpll-51m2",   "twpll-96m" };
0389 static SPRD_COMP_CLK(uart0_clk, "uart0",    uart_parents, 0x30,
0390              0, 2, 8, 3, 0);
0391 static SPRD_COMP_CLK(uart1_clk, "uart1",    uart_parents, 0x34,
0392              0, 2, 8, 3, 0);
0393 static SPRD_COMP_CLK(uart2_clk, "uart2",    uart_parents, 0x38,
0394              0, 2, 8, 3, 0);
0395 static SPRD_COMP_CLK(uart3_clk, "uart3",    uart_parents, 0x3c,
0396              0, 2, 8, 3, 0);
0397 static SPRD_COMP_CLK(uart4_clk, "uart4",    uart_parents, 0x40,
0398              0, 2, 8, 3, 0);
0399
0400 static const char * const i2c_parents[] = { "ext-26m", "twpll-48m",
0401                         "twpll-51m2", "twpll-153m6" };
0402 static SPRD_COMP_CLK(i2c0_clk,  "i2c0", i2c_parents, 0x44,
0403              0, 2, 8, 3, 0);
0404 static SPRD_COMP_CLK(i2c1_clk,  "i2c1", i2c_parents, 0x48,
0405              0, 2, 8, 3, 0);
0406 static SPRD_COMP_CLK(i2c2_clk,  "i2c2", i2c_parents, 0x4c,
0407              0, 2, 8, 3, 0);
0408 static SPRD_COMP_CLK(i2c3_clk,  "i2c3", i2c_parents, 0x50,
0409              0, 2, 8, 3, 0);
0410 static SPRD_COMP_CLK(i2c4_clk,  "i2c4", i2c_parents, 0x54,
0411              0, 2, 8, 3, 0);
0412 static SPRD_COMP_CLK(i2c5_clk,  "i2c5", i2c_parents, 0x58,
0413              0, 2, 8, 3, 0);
0414
0415 static const char * const spi_parents[] = { "ext-26m",  "twpll-128m",
0416                         "twpll-153m6",  "twpll-192m" };
0417 static SPRD_COMP_CLK(spi0_clk,  "spi0", spi_parents, 0x5c,
0418              0, 2, 8, 3, 0);
0419 static SPRD_COMP_CLK(spi1_clk,  "spi1", spi_parents, 0x60,
0420              0, 2, 8, 3, 0);
0421 static SPRD_COMP_CLK(spi2_clk,  "spi2", spi_parents, 0x64,
0422              0, 2, 8, 3, 0);
0423 static SPRD_COMP_CLK(spi3_clk,  "spi3", spi_parents, 0x68,
0424              0, 2, 8, 3, 0);
0425
0426 static const char * const iis_parents[] = { "ext-26m",
0427                         "twpll-128m",
0428                         "twpll-153m6" };
0429 static SPRD_COMP_CLK(iis0_clk,  "iis0", iis_parents, 0x6c,
0430              0, 2, 8, 6, 0);
0431 static SPRD_COMP_CLK(iis1_clk,  "iis1", iis_parents, 0x70,
0432              0, 2, 8, 6, 0);
0433 static SPRD_COMP_CLK(iis2_clk,  "iis2", iis_parents, 0x74,
0434              0, 2, 8, 6, 0);
0435 static SPRD_COMP_CLK(iis3_clk,  "iis3", iis_parents, 0x78,
0436              0, 2, 8, 6, 0);
0437
0438 static struct sprd_clk_common *sc9860_ap_clks[] = {
0439     /* address base is 0x20000000 */
0440     &ap_apb.common,
0441     &ap_usb3.common,
0442     &uart0_clk.common,
0443     &uart1_clk.common,
0444     &uart2_clk.common,
0445     &uart3_clk.common,
0446     &uart4_clk.common,
0447     &i2c0_clk.common,
0448     &i2c1_clk.common,
0449     &i2c2_clk.common,
0450     &i2c3_clk.common,
0451     &i2c4_clk.common,
0452     &i2c5_clk.common,
0453     &spi0_clk.common,
0454     &spi1_clk.common,
0455     &spi2_clk.common,
0456     &spi3_clk.common,
0457     &iis0_clk.common,
0458     &iis1_clk.common,
0459     &iis2_clk.common,
0460     &iis3_clk.common,
0461 };
0462
0463 static struct clk_hw_onecell_data sc9860_ap_clk_hws = {
0464     .hws    = {
0465         [CLK_AP_APB]    = &ap_apb.common.hw,
0466         [CLK_AP_USB3]   = &ap_usb3.common.hw,
0467         [CLK_UART0] = &uart0_clk.common.hw,
0468         [CLK_UART1] = &uart1_clk.common.hw,
0469         [CLK_UART2] = &uart2_clk.common.hw,
0470         [CLK_UART3] = &uart3_clk.common.hw,
0471         [CLK_UART4] = &uart4_clk.common.hw,
0472         [CLK_I2C0]  = &i2c0_clk.common.hw,
0473         [CLK_I2C1]  = &i2c1_clk.common.hw,
0474         [CLK_I2C2]  = &i2c2_clk.common.hw,
0475         [CLK_I2C3]  = &i2c3_clk.common.hw,
0476         [CLK_I2C4]  = &i2c4_clk.common.hw,
0477         [CLK_I2C5]  = &i2c5_clk.common.hw,
0478         [CLK_SPI0]  = &spi0_clk.common.hw,
0479         [CLK_SPI1]  = &spi1_clk.common.hw,
0480         [CLK_SPI2]  = &spi2_clk.common.hw,
0481         [CLK_SPI3]  = &spi3_clk.common.hw,
0482         [CLK_IIS0]  = &iis0_clk.common.hw,
0483         [CLK_IIS1]  = &iis1_clk.common.hw,
0484         [CLK_IIS2]  = &iis2_clk.common.hw,
0485         [CLK_IIS3]  = &iis3_clk.common.hw,
0486     },
0487     .num    = CLK_AP_CLK_NUM,
0488 };
0489
0490 static const struct sprd_clk_desc sc9860_ap_clk_desc = {
0491     .clk_clks   = sc9860_ap_clks,
0492     .num_clk_clks   = ARRAY_SIZE(sc9860_ap_clks),
0493     .hw_clks    = &sc9860_ap_clk_hws,
0494 };
0495
0496 static const char * const aon_apb_parents[] = { "rco-25m",  "ext-26m",
0497                         "ext-rco-100m", "twpll-96m",
0498                         "twpll-128m",
0499                         "twpll-153m6" };
0500 static SPRD_COMP_CLK(aon_apb, "aon-apb", aon_apb_parents, 0x230,
0501              0, 3, 8, 2, 0);
0502
0503 static const char * const aux_parents[] = { "ext-32k",      "rpll0-26m",
0504                         "rpll1-26m",    "ext-26m",
0505                         "cppll-50m",    "rco-25m",
0506                         "dpll0-50m",    "dpll1-50m",
0507                         "gpll-42m5",    "twpll-48m",
0508                         "m0-39m",       "m1-63m",
0509                         "l0-38m",       "l1-38m" };
0510
0511 static SPRD_COMP_CLK(aux0_clk,  "aux0",     aux_parents, 0x238,
0512              0, 5, 8, 4, 0);
0513 static SPRD_COMP_CLK(aux1_clk,  "aux1",     aux_parents, 0x23c,
0514              0, 5, 8, 4, 0);
0515 static SPRD_COMP_CLK(aux2_clk,  "aux2",     aux_parents, 0x240,
0516              0, 5, 8, 4, 0);
0517 static SPRD_COMP_CLK(probe_clk, "probe",    aux_parents, 0x244,
0518              0, 5, 8, 4, 0);
0519
0520 static const char * const sp_ahb_parents[] = {  "rco-4m",   "ext-26m",
0521                         "ext-rco-100m", "twpll-96m",
0522                         "twpll-128m",
0523                         "twpll-153m6" };
0524 static SPRD_COMP_CLK(sp_ahb,    "sp-ahb",   sp_ahb_parents, 0x2d0,
0525              0, 3, 8, 2, 0);
0526
0527 static const char * const cci_parents[] = { "ext-26m",  "twpll-384m",
0528                         "l0-614m4", "twpll-768m" };
0529 static SPRD_COMP_CLK(cci_clk,   "cci",      cci_parents, 0x300,
0530              0, 2, 8, 2, 0);
0531 static SPRD_COMP_CLK(gic_clk,   "gic",      cci_parents, 0x304,
0532              0, 2, 8, 2, 0);
0533 static SPRD_COMP_CLK(cssys_clk, "cssys",    cci_parents, 0x310,
0534              0, 2, 8, 2, 0);
0535
0536 static const char * const sdio_2x_parents[] = { "fac-1m",   "ext-26m",
0537                         "twpll-307m2",  "twpll-384m",
0538                         "l0-409m6" };
0539 static SPRD_COMP_CLK(sdio0_2x,  "sdio0-2x", sdio_2x_parents, 0x328,
0540              0, 3, 8, 4, 0);
0541 static SPRD_COMP_CLK(sdio1_2x,  "sdio1-2x", sdio_2x_parents, 0x330,
0542              0, 3, 8, 4, 0);
0543 static SPRD_COMP_CLK(sdio2_2x,  "sdio2-2x", sdio_2x_parents, 0x338,
0544              0, 3, 8, 4, 0);
0545 static SPRD_COMP_CLK(emmc_2x,   "emmc-2x",  sdio_2x_parents, 0x340,
0546              0, 3, 8, 4, 0);
0547
0548 static SPRD_DIV_CLK(sdio0_1x,   "sdio0-1x", "sdio0-2x", 0x32c,
0549             8, 1, 0);
0550 static SPRD_DIV_CLK(sdio1_1x,   "sdio1-1x", "sdio1-2x", 0x334,
0551             8, 1, 0);
0552 static SPRD_DIV_CLK(sdio2_1x,   "sdio2-1x", "sdio2-2x", 0x33c,
0553             8, 1, 0);
0554 static SPRD_DIV_CLK(emmc_1x,    "emmc-1x",  "emmc-2x",  0x344,
0555             8, 1, 0);
0556
0557 static const char * const adi_parents[] = { "rco-4m",   "ext-26m",
0558                         "rco-25m",  "twpll-38m4",
0559                         "twpll-51m2" };
0560 static SPRD_MUX_CLK(adi_clk,    "adi",  adi_parents, 0x234,
0561             0, 3, SC9860_MUX_FLAG);
0562
0563 static const char * const pwm_parents[] = { "ext-32k",  "ext-26m",
0564                         "rco-4m",   "rco-25m",
0565                         "twpll-48m" };
0566 static SPRD_MUX_CLK(pwm0_clk,   "pwm0", pwm_parents, 0x248,
0567             0, 3, SC9860_MUX_FLAG);
0568 static SPRD_MUX_CLK(pwm1_clk,   "pwm1", pwm_parents, 0x24c,
0569             0, 3, SC9860_MUX_FLAG);
0570 static SPRD_MUX_CLK(pwm2_clk,   "pwm2", pwm_parents, 0x250,
0571             0, 3, SC9860_MUX_FLAG);
0572 static SPRD_MUX_CLK(pwm3_clk,   "pwm3", pwm_parents, 0x254,
0573             0, 3, SC9860_MUX_FLAG);
0574
0575 static const char * const efuse_parents[] = { "rco-25m", "ext-26m" };
0576 static SPRD_MUX_CLK(efuse_clk, "efuse", efuse_parents, 0x258,
0577             0, 1, SC9860_MUX_FLAG);
0578
0579 static const char * const cm3_uart_parents[] = { "rco-4m",  "ext-26m",
0580                          "rco-100m",    "twpll-48m",
0581                          "twpll-51m2",  "twpll-96m",
0582                          "twpll-128m" };
0583 static SPRD_MUX_CLK(cm3_uart0, "cm3-uart0", cm3_uart_parents, 0x25c,
0584             0, 3, SC9860_MUX_FLAG);
0585 static SPRD_MUX_CLK(cm3_uart1, "cm3-uart1", cm3_uart_parents, 0x260,
0586             0, 3, SC9860_MUX_FLAG);
0587
0588 static const char * const thm_parents[] = { "ext-32k", "fac-250k" };
0589 static SPRD_MUX_CLK(thm_clk,    "thm",  thm_parents, 0x270,
0590             0, 1, SC9860_MUX_FLAG);
0591
0592 static const char * const cm3_i2c_parents[] = { "rco-4m",
0593                         "ext-26m",
0594                         "rco-100m",
0595                         "twpll-48m",
0596                         "twpll-51m2",
0597                         "twpll-153m6" };
0598 static SPRD_MUX_CLK(cm3_i2c0, "cm3-i2c0", cm3_i2c_parents, 0x274,
0599             0, 3, SC9860_MUX_FLAG);
0600 static SPRD_MUX_CLK(cm3_i2c1, "cm3-i2c1", cm3_i2c_parents, 0x278,
0601             0, 3, SC9860_MUX_FLAG);
0602 static SPRD_MUX_CLK(aon_i2c, "aon-i2c", cm3_i2c_parents, 0x280,
0603             0, 3, SC9860_MUX_FLAG);
0604
0605 static const char * const cm4_spi_parents[] = { "ext-26m",  "twpll-96m",
0606                         "rco-100m", "twpll-128m",
0607                         "twpll-153m6",  "twpll-192m" };
0608 static SPRD_MUX_CLK(cm4_spi, "cm4-spi", cm4_spi_parents, 0x27c,
0609             0, 3, SC9860_MUX_FLAG);
0610
0611 static SPRD_MUX_CLK(avs_clk, "avs", uart_parents, 0x284,
0612             0, 2, SC9860_MUX_FLAG);
0613
0614 static const char * const ca53_dap_parents[] = { "ext-26m", "rco-4m",
0615                          "rco-100m",    "twpll-76m8",
0616                          "twpll-128m",  "twpll-153m6" };
0617 static SPRD_MUX_CLK(ca53_dap, "ca53-dap", ca53_dap_parents, 0x288,
0618             0, 3, SC9860_MUX_FLAG);
0619
0620 static const char * const ca53_ts_parents[] = { "ext-32k", "ext-26m",
0621                         "clk-twpll-128m",
0622                         "clk-twpll-153m6" };
0623 static SPRD_MUX_CLK(ca53_ts, "ca53-ts", ca53_ts_parents, 0x290,
0624             0, 2, SC9860_MUX_FLAG);
0625
0626 static const char * const djtag_tck_parents[] = { "rco-4m", "ext-26m" };
0627 static SPRD_MUX_CLK(djtag_tck, "djtag-tck", djtag_tck_parents, 0x2c8,
0628             0, 1, SC9860_MUX_FLAG);
0629
0630 static const char * const pmu_parents[] = { "ext-32k", "rco-4m", "clk-4m" };
0631 static SPRD_MUX_CLK(pmu_clk, "pmu", pmu_parents, 0x2e0,
0632             0, 2, SC9860_MUX_FLAG);
0633
0634 static const char * const pmu_26m_parents[] = { "rco-25m", "ext-26m" };
0635 static SPRD_MUX_CLK(pmu_26m, "pmu-26m", pmu_26m_parents, 0x2e4,
0636             0, 1, SC9860_MUX_FLAG);
0637
0638 static const char * const debounce_parents[] = { "ext-32k", "rco-4m",
0639                          "rco-25m", "ext-26m" };
0640 static SPRD_MUX_CLK(debounce_clk, "debounce", debounce_parents, 0x2e8,
0641             0, 2, SC9860_MUX_FLAG);
0642
0643 static const char * const otg2_ref_parents[] = { "twpll-12m", "twpll-24m" };
0644 static SPRD_MUX_CLK(otg2_ref, "otg2-ref", otg2_ref_parents, 0x2f4,
0645             0, 1, SC9860_MUX_FLAG);
0646
0647 static const char * const usb3_ref_parents[] = { "twpll-24m", "twpll-19m2",
0648                          "twpll-48m" };
0649 static SPRD_MUX_CLK(usb3_ref, "usb3-ref", usb3_ref_parents, 0x2f8,
0650             0, 2, SC9860_MUX_FLAG);
0651
0652 static const char * const ap_axi_parents[] = { "ext-26m", "twpll-76m8",
0653                            "twpll-128m", "twpll-256m" };
0654 static SPRD_MUX_CLK(ap_axi, "ap-axi", ap_axi_parents, 0x324,
0655             0, 2, SC9860_MUX_FLAG);
0656
0657 static struct sprd_clk_common *sc9860_aon_prediv[] = {
0658     /* address base is 0x402d0000 */
0659     &aon_apb.common,
0660     &aux0_clk.common,
0661     &aux1_clk.common,
0662     &aux2_clk.common,
0663     &probe_clk.common,
0664     &sp_ahb.common,
0665     &cci_clk.common,
0666     &gic_clk.common,
0667     &cssys_clk.common,
0668     &sdio0_2x.common,
0669     &sdio1_2x.common,
0670     &sdio2_2x.common,
0671     &emmc_2x.common,
0672     &sdio0_1x.common,
0673     &sdio1_1x.common,
0674     &sdio2_1x.common,
0675     &emmc_1x.common,
0676     &adi_clk.common,
0677     &pwm0_clk.common,
0678     &pwm1_clk.common,
0679     &pwm2_clk.common,
0680     &pwm3_clk.common,
0681     &efuse_clk.common,
0682     &cm3_uart0.common,
0683     &cm3_uart1.common,
0684     &thm_clk.common,
0685     &cm3_i2c0.common,
0686     &cm3_i2c1.common,
0687     &cm4_spi.common,
0688     &aon_i2c.common,
0689     &avs_clk.common,
0690     &ca53_dap.common,
0691     &ca53_ts.common,
0692     &djtag_tck.common,
0693     &pmu_clk.common,
0694     &pmu_26m.common,
0695     &debounce_clk.common,
0696     &otg2_ref.common,
0697     &usb3_ref.common,
0698     &ap_axi.common,
0699 };
0700
0701 static struct clk_hw_onecell_data sc9860_aon_prediv_hws = {
0702     .hws    = {
0703         [CLK_AON_APB]       = &aon_apb.common.hw,
0704         [CLK_AUX0]      = &aux0_clk.common.hw,
0705         [CLK_AUX1]      = &aux1_clk.common.hw,
0706         [CLK_AUX2]      = &aux2_clk.common.hw,
0707         [CLK_PROBE]     = &probe_clk.common.hw,
0708         [CLK_SP_AHB]        = &sp_ahb.common.hw,
0709         [CLK_CCI]       = &cci_clk.common.hw,
0710         [CLK_GIC]       = &gic_clk.common.hw,
0711         [CLK_CSSYS]     = &cssys_clk.common.hw,
0712         [CLK_SDIO0_2X]      = &sdio0_2x.common.hw,
0713         [CLK_SDIO1_2X]      = &sdio1_2x.common.hw,
0714         [CLK_SDIO2_2X]      = &sdio2_2x.common.hw,
0715         [CLK_EMMC_2X]       = &emmc_2x.common.hw,
0716         [CLK_SDIO0_1X]      = &sdio0_1x.common.hw,
0717         [CLK_SDIO1_1X]      = &sdio1_1x.common.hw,
0718         [CLK_SDIO2_1X]      = &sdio2_1x.common.hw,
0719         [CLK_EMMC_1X]       = &emmc_1x.common.hw,
0720         [CLK_ADI]       = &adi_clk.common.hw,
0721         [CLK_PWM0]      = &pwm0_clk.common.hw,
0722         [CLK_PWM1]      = &pwm1_clk.common.hw,
0723         [CLK_PWM2]      = &pwm2_clk.common.hw,
0724         [CLK_PWM3]      = &pwm3_clk.common.hw,
0725         [CLK_EFUSE]     = &efuse_clk.common.hw,
0726         [CLK_CM3_UART0]     = &cm3_uart0.common.hw,
0727         [CLK_CM3_UART1]     = &cm3_uart1.common.hw,
0728         [CLK_THM]       = &thm_clk.common.hw,
0729         [CLK_CM3_I2C0]      = &cm3_i2c0.common.hw,
0730         [CLK_CM3_I2C1]      = &cm3_i2c1.common.hw,
0731         [CLK_CM4_SPI]       = &cm4_spi.common.hw,
0732         [CLK_AON_I2C]       = &aon_i2c.common.hw,
0733         [CLK_AVS]       = &avs_clk.common.hw,
0734         [CLK_CA53_DAP]      = &ca53_dap.common.hw,
0735         [CLK_CA53_TS]       = &ca53_ts.common.hw,
0736         [CLK_DJTAG_TCK]     = &djtag_tck.common.hw,
0737         [CLK_PMU]       = &pmu_clk.common.hw,
0738         [CLK_PMU_26M]       = &pmu_26m.common.hw,
0739         [CLK_DEBOUNCE]      = &debounce_clk.common.hw,
0740         [CLK_OTG2_REF]      = &otg2_ref.common.hw,
0741         [CLK_USB3_REF]      = &usb3_ref.common.hw,
0742         [CLK_AP_AXI]        = &ap_axi.common.hw,
0743     },
0744     .num    = CLK_AON_PREDIV_NUM,
0745 };
0746
0747 static const struct sprd_clk_desc sc9860_aon_prediv_desc = {
0748     .clk_clks   = sc9860_aon_prediv,
0749     .num_clk_clks   = ARRAY_SIZE(sc9860_aon_prediv),
0750     .hw_clks    = &sc9860_aon_prediv_hws,
0751 };
0752
0753 static SPRD_SC_GATE_CLK(usb3_eb,        "usb3-eb",  "ap-axi", 0x0,
0754              0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
0755 static SPRD_SC_GATE_CLK(usb3_suspend,   "usb3-suspend", "ap-axi", 0x0,
0756              0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
0757 static SPRD_SC_GATE_CLK(usb3_ref_eb,    "usb3-ref-eb",  "ap-axi", 0x0,
0758              0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
0759 static SPRD_SC_GATE_CLK(dma_eb,     "dma-eb",   "ap-axi", 0x0,
0760              0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
0761 static SPRD_SC_GATE_CLK(sdio0_eb,       "sdio0-eb", "ap-axi", 0x0,
0762              0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
0763 static SPRD_SC_GATE_CLK(sdio1_eb,       "sdio1-eb", "ap-axi", 0x0,
0764              0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
0765 static SPRD_SC_GATE_CLK(sdio2_eb,       "sdio2-eb", "ap-axi", 0x0,
0766              0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
0767 static SPRD_SC_GATE_CLK(emmc_eb,        "emmc-eb",  "ap-axi", 0x0,
0768              0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
0769 static SPRD_SC_GATE_CLK(rom_eb,     "rom-eb",   "ap-axi", 0x0,
0770              0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
0771 static SPRD_SC_GATE_CLK(busmon_eb,      "busmon-eb",    "ap-axi", 0x0,
0772              0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
0773 static SPRD_SC_GATE_CLK(cc63s_eb,       "cc63s-eb", "ap-axi", 0x0,
0774              0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
0775 static SPRD_SC_GATE_CLK(cc63p_eb,       "cc63p-eb", "ap-axi", 0x0,
0776              0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
0777 static SPRD_SC_GATE_CLK(ce0_eb,     "ce0-eb",   "ap-axi", 0x0,
0778              0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
0779 static SPRD_SC_GATE_CLK(ce1_eb,     "ce1-eb",   "ap-axi", 0x0,
0780              0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
0781
0782 static struct sprd_clk_common *sc9860_apahb_gate[] = {
0783     /* address base is 0x20210000 */
0784     &usb3_eb.common,
0785     &usb3_suspend.common,
0786     &usb3_ref_eb.common,
0787     &dma_eb.common,
0788     &sdio0_eb.common,
0789     &sdio1_eb.common,
0790     &sdio2_eb.common,
0791     &emmc_eb.common,
0792     &rom_eb.common,
0793     &busmon_eb.common,
0794     &cc63s_eb.common,
0795     &cc63p_eb.common,
0796     &ce0_eb.common,
0797     &ce1_eb.common,
0798 };
0799
0800 static struct clk_hw_onecell_data sc9860_apahb_gate_hws = {
0801     .hws    = {
0802         [CLK_USB3_EB]       = &usb3_eb.common.hw,
0803         [CLK_USB3_SUSPEND_EB]   = &usb3_suspend.common.hw,
0804         [CLK_USB3_REF_EB]   = &usb3_ref_eb.common.hw,
0805         [CLK_DMA_EB]        = &dma_eb.common.hw,
0806         [CLK_SDIO0_EB]      = &sdio0_eb.common.hw,
0807         [CLK_SDIO1_EB]      = &sdio1_eb.common.hw,
0808         [CLK_SDIO2_EB]      = &sdio2_eb.common.hw,
0809         [CLK_EMMC_EB]       = &emmc_eb.common.hw,
0810         [CLK_ROM_EB]        = &rom_eb.common.hw,
0811         [CLK_BUSMON_EB]     = &busmon_eb.common.hw,
0812         [CLK_CC63S_EB]      = &cc63s_eb.common.hw,
0813         [CLK_CC63P_EB]      = &cc63p_eb.common.hw,
0814         [CLK_CE0_EB]        = &ce0_eb.common.hw,
0815         [CLK_CE1_EB]        = &ce1_eb.common.hw,
0816     },
0817     .num    = CLK_APAHB_GATE_NUM,
0818 };
0819
0820 static const struct sprd_clk_desc sc9860_apahb_gate_desc = {
0821     .clk_clks   = sc9860_apahb_gate,
0822     .num_clk_clks   = ARRAY_SIZE(sc9860_apahb_gate),
0823     .hw_clks    = &sc9860_apahb_gate_hws,
0824 };
0825
0826 static SPRD_SC_GATE_CLK(avs_lit_eb, "avs-lit-eb",   "aon-apb", 0x0,
0827              0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
0828 static SPRD_SC_GATE_CLK(avs_big_eb, "avs-big-eb",   "aon-apb", 0x0,
0829              0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
0830 static SPRD_SC_GATE_CLK(ap_intc5_eb,    "ap-intc5-eb",  "aon-apb", 0x0,
0831              0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
0832 static SPRD_SC_GATE_CLK(gpio_eb,        "gpio-eb",  "aon-apb", 0x0,
0833              0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
0834 static SPRD_SC_GATE_CLK(pwm0_eb,        "pwm0-eb",  "aon-apb", 0x0,
0835              0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
0836 static SPRD_SC_GATE_CLK(pwm1_eb,        "pwm1-eb",  "aon-apb", 0x0,
0837              0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
0838 static SPRD_SC_GATE_CLK(pwm2_eb,        "pwm2-eb",  "aon-apb", 0x0,
0839              0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
0840 static SPRD_SC_GATE_CLK(pwm3_eb,        "pwm3-eb",  "aon-apb", 0x0,
0841              0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
0842 static SPRD_SC_GATE_CLK(kpd_eb,     "kpd-eb",   "aon-apb", 0x0,
0843              0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
0844 static SPRD_SC_GATE_CLK(aon_sys_eb, "aon-sys-eb",   "aon-apb", 0x0,
0845              0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
0846 static SPRD_SC_GATE_CLK(ap_sys_eb,  "ap-sys-eb",    "aon-apb", 0x0,
0847              0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
0848 static SPRD_SC_GATE_CLK(aon_tmr_eb, "aon-tmr-eb",   "aon-apb", 0x0,
0849              0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
0850 static SPRD_SC_GATE_CLK(ap_tmr0_eb, "ap-tmr0-eb",   "aon-apb", 0x0,
0851              0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
0852 static SPRD_SC_GATE_CLK(efuse_eb,   "efuse-eb", "aon-apb", 0x0,
0853              0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
0854 static SPRD_SC_GATE_CLK(eic_eb,     "eic-eb",   "aon-apb", 0x0,
0855              0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
0856 static SPRD_SC_GATE_CLK(pub1_reg_eb,    "pub1-reg-eb",  "aon-apb", 0x0,
0857              0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
0858 static SPRD_SC_GATE_CLK(adi_eb,     "adi-eb",   "aon-apb", 0x0,
0859              0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
0860 static SPRD_SC_GATE_CLK(ap_intc0_eb,    "ap-intc0-eb",  "aon-apb", 0x0,
0861              0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
0862 static SPRD_SC_GATE_CLK(ap_intc1_eb,    "ap-intc1-eb",  "aon-apb", 0x0,
0863              0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
0864 static SPRD_SC_GATE_CLK(ap_intc2_eb,    "ap-intc2-eb",  "aon-apb", 0x0,
0865              0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
0866 static SPRD_SC_GATE_CLK(ap_intc3_eb,    "ap-intc3-eb",  "aon-apb", 0x0,
0867              0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
0868 static SPRD_SC_GATE_CLK(ap_intc4_eb,    "ap-intc4-eb",  "aon-apb", 0x0,
0869              0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
0870 static SPRD_SC_GATE_CLK(splk_eb,        "splk-eb",  "aon-apb", 0x0,
0871              0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
0872 static SPRD_SC_GATE_CLK(mspi_eb,        "mspi-eb",  "aon-apb", 0x0,
0873              0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
0874 static SPRD_SC_GATE_CLK(pub0_reg_eb,    "pub0-reg-eb",  "aon-apb", 0x0,
0875              0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
0876 static SPRD_SC_GATE_CLK(pin_eb,     "pin-eb",   "aon-apb", 0x0,
0877              0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
0878 static SPRD_SC_GATE_CLK(aon_ckg_eb, "aon-ckg-eb",   "aon-apb", 0x0,
0879              0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);
0880 static SPRD_SC_GATE_CLK(gpu_eb,     "gpu-eb",   "aon-apb", 0x0,
0881              0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
0882 static SPRD_SC_GATE_CLK(apcpu_ts0_eb,   "apcpu-ts0-eb", "aon-apb", 0x0,
0883              0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);
0884 static SPRD_SC_GATE_CLK(apcpu_ts1_eb,   "apcpu-ts1-eb", "aon-apb", 0x0,
0885              0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);
0886 static SPRD_SC_GATE_CLK(dap_eb,     "dap-eb",   "aon-apb", 0x0,
0887              0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);
0888 static SPRD_SC_GATE_CLK(i2c_eb,     "i2c-eb",   "aon-apb", 0x0,
0889              0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);
0890 static SPRD_SC_GATE_CLK(pmu_eb,     "pmu-eb",   "aon-apb", 0x4,
0891              0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
0892 static SPRD_SC_GATE_CLK(thm_eb,     "thm-eb",   "aon-apb", 0x4,
0893              0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
0894 static SPRD_SC_GATE_CLK(aux0_eb,        "aux0-eb",  "aon-apb", 0x4,
0895              0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
0896 static SPRD_SC_GATE_CLK(aux1_eb,        "aux1-eb",  "aon-apb", 0x4,
0897              0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
0898 static SPRD_SC_GATE_CLK(aux2_eb,        "aux2-eb",  "aon-apb", 0x4,
0899              0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
0900 static SPRD_SC_GATE_CLK(probe_eb,       "probe-eb", "aon-apb", 0x4,
0901              0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
0902 static SPRD_SC_GATE_CLK(gpu0_avs_eb,    "gpu0-avs-eb",  "aon-apb", 0x4,
0903              0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
0904 static SPRD_SC_GATE_CLK(gpu1_avs_eb,    "gpu1-avs-eb",  "aon-apb", 0x4,
0905              0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
0906 static SPRD_SC_GATE_CLK(apcpu_wdg_eb,   "apcpu-wdg-eb", "aon-apb", 0x4,
0907              0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
0908 static SPRD_SC_GATE_CLK(ap_tmr1_eb, "ap-tmr1-eb",   "aon-apb", 0x4,
0909              0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
0910 static SPRD_SC_GATE_CLK(ap_tmr2_eb, "ap-tmr2-eb",   "aon-apb", 0x4,
0911              0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
0912 static SPRD_SC_GATE_CLK(disp_emc_eb,    "disp-emc-eb",  "aon-apb", 0x4,
0913              0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
0914 static SPRD_SC_GATE_CLK(zip_emc_eb, "zip-emc-eb",   "aon-apb", 0x4,
0915              0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
0916 static SPRD_SC_GATE_CLK(gsp_emc_eb, "gsp-emc-eb",   "aon-apb", 0x4,
0917              0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
0918 static SPRD_SC_GATE_CLK(osc_aon_eb, "osc-aon-eb",   "aon-apb", 0x4,
0919              0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
0920 static SPRD_SC_GATE_CLK(lvds_trx_eb,    "lvds-trx-eb",  "aon-apb", 0x4,
0921              0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
0922 static SPRD_SC_GATE_CLK(lvds_tcxo_eb,   "lvds-tcxo-eb", "aon-apb", 0x4,
0923              0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
0924 static SPRD_SC_GATE_CLK(mdar_eb,        "mdar-eb",  "aon-apb", 0x4,
0925              0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
0926 static SPRD_SC_GATE_CLK(rtc4m0_cal_eb, "rtc4m0-cal-eb", "aon-apb", 0x4,
0927              0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
0928 static SPRD_SC_GATE_CLK(rct100m_cal_eb, "rct100m-cal-eb",   "aon-apb", 0x4,
0929              0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
0930 static SPRD_SC_GATE_CLK(djtag_eb,       "djtag-eb", "aon-apb", 0x4,
0931              0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
0932 static SPRD_SC_GATE_CLK(mbox_eb,        "mbox-eb",  "aon-apb", 0x4,
0933              0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
0934 static SPRD_SC_GATE_CLK(aon_dma_eb, "aon-dma-eb",   "aon-apb", 0x4,
0935              0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
0936 static SPRD_SC_GATE_CLK(dbg_emc_eb, "dbg-emc-eb",   "aon-apb", 0x4,
0937              0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
0938 static SPRD_SC_GATE_CLK(lvds_pll_div_en, "lvds-pll-div-en", "aon-apb", 0x4,
0939              0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
0940 static SPRD_SC_GATE_CLK(def_eb,     "def-eb",   "aon-apb", 0x4,
0941              0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
0942 static SPRD_SC_GATE_CLK(aon_apb_rsv0,   "aon-apb-rsv0", "aon-apb", 0x4,
0943              0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);
0944 static SPRD_SC_GATE_CLK(orp_jtag_eb,    "orp-jtag-eb",  "aon-apb", 0x4,
0945              0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
0946 static SPRD_SC_GATE_CLK(vsp_eb,     "vsp-eb",   "aon-apb", 0x4,
0947              0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);
0948 static SPRD_SC_GATE_CLK(cam_eb,     "cam-eb",   "aon-apb", 0x4,
0949              0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);
0950 static SPRD_SC_GATE_CLK(disp_eb,        "disp-eb",  "aon-apb", 0x4,
0951              0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);
0952 static SPRD_SC_GATE_CLK(dbg_axi_if_eb, "dbg-axi-if-eb", "aon-apb", 0x4,
0953              0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);
0954 static SPRD_SC_GATE_CLK(sdio0_2x_en,    "sdio0-2x-en",  "aon-apb", 0x13c,
0955                    0x1000, BIT(2), 0, 0);
0956 static SPRD_SC_GATE_CLK(sdio1_2x_en,    "sdio1-2x-en",  "aon-apb", 0x13c,
0957                    0x1000, BIT(4), 0, 0);
0958 static SPRD_SC_GATE_CLK(sdio2_2x_en,    "sdio2-2x-en",  "aon-apb", 0x13c,
0959                    0x1000, BIT(6), 0, 0);
0960 static SPRD_SC_GATE_CLK(emmc_2x_en, "emmc-2x-en",   "aon-apb", 0x13c,
0961                    0x1000, BIT(9), 0, 0);
0962 static SPRD_SC_GATE_CLK(arch_rtc_eb, "arch-rtc-eb", "aon-apb", 0x10,
0963              0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
0964 static SPRD_SC_GATE_CLK(kpb_rtc_eb, "kpb-rtc-eb",   "aon-apb", 0x10,
0965              0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
0966 static SPRD_SC_GATE_CLK(aon_syst_rtc_eb, "aon-syst-rtc-eb", "aon-apb", 0x10,
0967              0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
0968 static SPRD_SC_GATE_CLK(ap_syst_rtc_eb, "ap-syst-rtc-eb",   "aon-apb", 0x10,
0969              0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
0970 static SPRD_SC_GATE_CLK(aon_tmr_rtc_eb, "aon-tmr-rtc-eb",   "aon-apb", 0x10,
0971              0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
0972 static SPRD_SC_GATE_CLK(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb",   "aon-apb", 0x10,
0973              0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
0974 static SPRD_SC_GATE_CLK(eic_rtc_eb, "eic-rtc-eb",   "aon-apb", 0x10,
0975              0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
0976 static SPRD_SC_GATE_CLK(eic_rtcdv5_eb, "eic-rtcdv5-eb", "aon-apb", 0x10,
0977              0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
0978 static SPRD_SC_GATE_CLK(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", "aon-apb", 0x10,
0979              0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
0980 static SPRD_SC_GATE_CLK(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb",   "aon-apb", 0x10,
0981              0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
0982 static SPRD_SC_GATE_CLK(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb",   "aon-apb", 0x10,
0983              0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
0984 static SPRD_SC_GATE_CLK(dcxo_tmr_rtc_eb, "dcxo-tmr-rtc-eb", "aon-apb", 0x10,
0985              0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
0986 static SPRD_SC_GATE_CLK(bb_cal_rtc_eb, "bb-cal-rtc-eb", "aon-apb", 0x10,
0987              0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
0988 static SPRD_SC_GATE_CLK(avs_big_rtc_eb, "avs-big-rtc-eb",   "aon-apb", 0x10,
0989              0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
0990 static SPRD_SC_GATE_CLK(avs_lit_rtc_eb, "avs-lit-rtc-eb",   "aon-apb", 0x10,
0991              0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
0992 static SPRD_SC_GATE_CLK(avs_gpu0_rtc_eb, "avs-gpu0-rtc-eb", "aon-apb", 0x10,
0993              0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
0994 static SPRD_SC_GATE_CLK(avs_gpu1_rtc_eb, "avs-gpu1-rtc-eb", "aon-apb", 0x10,
0995              0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
0996 static SPRD_SC_GATE_CLK(gpu_ts_eb, "gpu-ts-eb", "aon-apb", 0x10,
0997              0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
0998 static SPRD_SC_GATE_CLK(rtcdv10_eb, "rtcdv10-eb",   "aon-apb", 0x10,
0999              0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
1000
1001 static struct sprd_clk_common *sc9860_aon_gate[] = {
1002     /* address base is 0x402e0000 */
1003     &avs_lit_eb.common,
1004     &avs_big_eb.common,
1005     &ap_intc5_eb.common,
1006     &gpio_eb.common,
1007     &pwm0_eb.common,
1008     &pwm1_eb.common,
1009     &pwm2_eb.common,
1010     &pwm3_eb.common,
1011     &kpd_eb.common,
1012     &aon_sys_eb.common,
1013     &ap_sys_eb.common,
1014     &aon_tmr_eb.common,
1015     &ap_tmr0_eb.common,
1016     &efuse_eb.common,
1017     &eic_eb.common,
1018     &pub1_reg_eb.common,
1019     &adi_eb.common,
1020     &ap_intc0_eb.common,
1021     &ap_intc1_eb.common,
1022     &ap_intc2_eb.common,
1023     &ap_intc3_eb.common,
1024     &ap_intc4_eb.common,
1025     &splk_eb.common,
1026     &mspi_eb.common,
1027     &pub0_reg_eb.common,
1028     &pin_eb.common,
1029     &aon_ckg_eb.common,
1030     &gpu_eb.common,
1031     &apcpu_ts0_eb.common,
1032     &apcpu_ts1_eb.common,
1033     &dap_eb.common,
1034     &i2c_eb.common,
1035     &pmu_eb.common,
1036     &thm_eb.common,
1037     &aux0_eb.common,
1038     &aux1_eb.common,
1039     &aux2_eb.common,
1040     &probe_eb.common,
1041     &gpu0_avs_eb.common,
1042     &gpu1_avs_eb.common,
1043     &apcpu_wdg_eb.common,
1044     &ap_tmr1_eb.common,
1045     &ap_tmr2_eb.common,
1046     &disp_emc_eb.common,
1047     &zip_emc_eb.common,
1048     &gsp_emc_eb.common,
1049     &osc_aon_eb.common,
1050     &lvds_trx_eb.common,
1051     &lvds_tcxo_eb.common,
1052     &mdar_eb.common,
1053     &rtc4m0_cal_eb.common,
1054     &rct100m_cal_eb.common,
1055     &djtag_eb.common,
1056     &mbox_eb.common,
1057     &aon_dma_eb.common,
1058     &dbg_emc_eb.common,
1059     &lvds_pll_div_en.common,
1060     &def_eb.common,
1061     &aon_apb_rsv0.common,
1062     &orp_jtag_eb.common,
1063     &vsp_eb.common,
1064     &cam_eb.common,
1065     &disp_eb.common,
1066     &dbg_axi_if_eb.common,
1067     &sdio0_2x_en.common,
1068     &sdio1_2x_en.common,
1069     &sdio2_2x_en.common,
1070     &emmc_2x_en.common,
1071     &arch_rtc_eb.common,
1072     &kpb_rtc_eb.common,
1073     &aon_syst_rtc_eb.common,
1074     &ap_syst_rtc_eb.common,
1075     &aon_tmr_rtc_eb.common,
1076     &ap_tmr0_rtc_eb.common,
1077     &eic_rtc_eb.common,
1078     &eic_rtcdv5_eb.common,
1079     &ap_wdg_rtc_eb.common,
1080     &ap_tmr1_rtc_eb.common,
1081     &ap_tmr2_rtc_eb.common,
1082     &dcxo_tmr_rtc_eb.common,
1083     &bb_cal_rtc_eb.common,
1084     &avs_big_rtc_eb.common,
1085     &avs_lit_rtc_eb.common,
1086     &avs_gpu0_rtc_eb.common,
1087     &avs_gpu1_rtc_eb.common,
1088     &gpu_ts_eb.common,
1089     &rtcdv10_eb.common,
1090 };
1091
1092 static struct clk_hw_onecell_data sc9860_aon_gate_hws = {
1093     .hws    = {
1094         [CLK_AVS_LIT_EB]    = &avs_lit_eb.common.hw,
1095         [CLK_AVS_BIG_EB]    = &avs_big_eb.common.hw,
1096         [CLK_AP_INTC5_EB]   = &ap_intc5_eb.common.hw,
1097         [CLK_GPIO_EB]       = &gpio_eb.common.hw,
1098         [CLK_PWM0_EB]       = &pwm0_eb.common.hw,
1099         [CLK_PWM1_EB]       = &pwm1_eb.common.hw,
1100         [CLK_PWM2_EB]       = &pwm2_eb.common.hw,
1101         [CLK_PWM3_EB]       = &pwm3_eb.common.hw,
1102         [CLK_KPD_EB]        = &kpd_eb.common.hw,
1103         [CLK_AON_SYS_EB]    = &aon_sys_eb.common.hw,
1104         [CLK_AP_SYS_EB]     = &ap_sys_eb.common.hw,
1105         [CLK_AON_TMR_EB]    = &aon_tmr_eb.common.hw,
1106         [CLK_AP_TMR0_EB]    = &ap_tmr0_eb.common.hw,
1107         [CLK_EFUSE_EB]      = &efuse_eb.common.hw,
1108         [CLK_EIC_EB]        = &eic_eb.common.hw,
1109         [CLK_PUB1_REG_EB]   = &pub1_reg_eb.common.hw,
1110         [CLK_ADI_EB]        = &adi_eb.common.hw,
1111         [CLK_AP_INTC0_EB]   = &ap_intc0_eb.common.hw,
1112         [CLK_AP_INTC1_EB]   = &ap_intc1_eb.common.hw,
1113         [CLK_AP_INTC2_EB]   = &ap_intc2_eb.common.hw,
1114         [CLK_AP_INTC3_EB]   = &ap_intc3_eb.common.hw,
1115         [CLK_AP_INTC4_EB]   = &ap_intc4_eb.common.hw,
1116         [CLK_SPLK_EB]       = &splk_eb.common.hw,
1117         [CLK_MSPI_EB]       = &mspi_eb.common.hw,
1118         [CLK_PUB0_REG_EB]   = &pub0_reg_eb.common.hw,
1119         [CLK_PIN_EB]        = &pin_eb.common.hw,
1120         [CLK_AON_CKG_EB]    = &aon_ckg_eb.common.hw,
1121         [CLK_GPU_EB]        = &gpu_eb.common.hw,
1122         [CLK_APCPU_TS0_EB]  = &apcpu_ts0_eb.common.hw,
1123         [CLK_APCPU_TS1_EB]  = &apcpu_ts1_eb.common.hw,
1124         [CLK_DAP_EB]        = &dap_eb.common.hw,
1125         [CLK_I2C_EB]        = &i2c_eb.common.hw,
1126         [CLK_PMU_EB]        = &pmu_eb.common.hw,
1127         [CLK_THM_EB]        = &thm_eb.common.hw,
1128         [CLK_AUX0_EB]       = &aux0_eb.common.hw,
1129         [CLK_AUX1_EB]       = &aux1_eb.common.hw,
1130         [CLK_AUX2_EB]       = &aux2_eb.common.hw,
1131         [CLK_PROBE_EB]      = &probe_eb.common.hw,
1132         [CLK_GPU0_AVS_EB]   = &gpu0_avs_eb.common.hw,
1133         [CLK_GPU1_AVS_EB]   = &gpu1_avs_eb.common.hw,
1134         [CLK_APCPU_WDG_EB]  = &apcpu_wdg_eb.common.hw,
1135         [CLK_AP_TMR1_EB]    = &ap_tmr1_eb.common.hw,
1136         [CLK_AP_TMR2_EB]    = &ap_tmr2_eb.common.hw,
1137         [CLK_DISP_EMC_EB]   = &disp_emc_eb.common.hw,
1138         [CLK_ZIP_EMC_EB]    = &zip_emc_eb.common.hw,
1139         [CLK_GSP_EMC_EB]    = &gsp_emc_eb.common.hw,
1140         [CLK_OSC_AON_EB]    = &osc_aon_eb.common.hw,
1141         [CLK_LVDS_TRX_EB]   = &lvds_trx_eb.common.hw,
1142         [CLK_LVDS_TCXO_EB]  = &lvds_tcxo_eb.common.hw,
1143         [CLK_MDAR_EB]       = &mdar_eb.common.hw,
1144         [CLK_RTC4M0_CAL_EB] = &rtc4m0_cal_eb.common.hw,
1145         [CLK_RCT100M_CAL_EB]    = &rct100m_cal_eb.common.hw,
1146         [CLK_DJTAG_EB]      = &djtag_eb.common.hw,
1147         [CLK_MBOX_EB]       = &mbox_eb.common.hw,
1148         [CLK_AON_DMA_EB]    = &aon_dma_eb.common.hw,
1149         [CLK_DBG_EMC_EB]    = &dbg_emc_eb.common.hw,
1150         [CLK_LVDS_PLL_DIV_EN]   = &lvds_pll_div_en.common.hw,
1151         [CLK_DEF_EB]        = &def_eb.common.hw,
1152         [CLK_AON_APB_RSV0]  = &aon_apb_rsv0.common.hw,
1153         [CLK_ORP_JTAG_EB]   = &orp_jtag_eb.common.hw,
1154         [CLK_VSP_EB]        = &vsp_eb.common.hw,
1155         [CLK_CAM_EB]        = &cam_eb.common.hw,
1156         [CLK_DISP_EB]       = &disp_eb.common.hw,
1157         [CLK_DBG_AXI_IF_EB] = &dbg_axi_if_eb.common.hw,
1158         [CLK_SDIO0_2X_EN]   = &sdio0_2x_en.common.hw,
1159         [CLK_SDIO1_2X_EN]   = &sdio1_2x_en.common.hw,
1160         [CLK_SDIO2_2X_EN]   = &sdio2_2x_en.common.hw,
1161         [CLK_EMMC_2X_EN]    = &emmc_2x_en.common.hw,
1162         [CLK_ARCH_RTC_EB]   = &arch_rtc_eb.common.hw,
1163         [CLK_KPB_RTC_EB]    = &kpb_rtc_eb.common.hw,
1164         [CLK_AON_SYST_RTC_EB]   = &aon_syst_rtc_eb.common.hw,
1165         [CLK_AP_SYST_RTC_EB]    = &ap_syst_rtc_eb.common.hw,
1166         [CLK_AON_TMR_RTC_EB]    = &aon_tmr_rtc_eb.common.hw,
1167         [CLK_AP_TMR0_RTC_EB]    = &ap_tmr0_rtc_eb.common.hw,
1168         [CLK_EIC_RTC_EB]    = &eic_rtc_eb.common.hw,
1169         [CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw,
1170         [CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw,
1171         [CLK_AP_TMR1_RTC_EB]    = &ap_tmr1_rtc_eb.common.hw,
1172         [CLK_AP_TMR2_RTC_EB]    = &ap_tmr2_rtc_eb.common.hw,
1173         [CLK_DCXO_TMR_RTC_EB]   = &dcxo_tmr_rtc_eb.common.hw,
1174         [CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw,
1175         [CLK_AVS_BIG_RTC_EB]    = &avs_big_rtc_eb.common.hw,
1176         [CLK_AVS_LIT_RTC_EB]    = &avs_lit_rtc_eb.common.hw,
1177         [CLK_AVS_GPU0_RTC_EB]   = &avs_gpu0_rtc_eb.common.hw,
1178         [CLK_AVS_GPU1_RTC_EB]   = &avs_gpu1_rtc_eb.common.hw,
1179         [CLK_GPU_TS_EB]     = &gpu_ts_eb.common.hw,
1180         [CLK_RTCDV10_EB]    = &rtcdv10_eb.common.hw,
1181     },
1182     .num    = CLK_AON_GATE_NUM,
1183 };
1184
1185 static const struct sprd_clk_desc sc9860_aon_gate_desc = {
1186     .clk_clks   = sc9860_aon_gate,
1187     .num_clk_clks   = ARRAY_SIZE(sc9860_aon_gate),
1188     .hw_clks    = &sc9860_aon_gate_hws,
1189 };
1190
1191 static const u8 mcu_table[] = { 0, 1, 2, 3, 4, 8 };
1192 static const char * const lit_mcu_parents[] = { "ext-26m",  "twpll-512m",
1193                         "twpll-768m",   "ltepll0",
1194                         "twpll",    "mpll0" };
1195 static SPRD_COMP_CLK_TABLE(lit_mcu, "lit-mcu", lit_mcu_parents, 0x20,
1196                mcu_table, 0, 4, 4, 3, 0);
1197
1198 static const char * const big_mcu_parents[] = { "ext-26m",  "twpll-512m",
1199                         "twpll-768m",   "ltepll0",
1200                         "twpll",    "mpll1" };
1201 static SPRD_COMP_CLK_TABLE(big_mcu, "big-mcu", big_mcu_parents, 0x24,
1202                mcu_table, 0, 4, 4, 3, 0);
1203
1204 static struct sprd_clk_common *sc9860_aonsecure_clk[] = {
1205     /* address base is 0x40880000 */
1206     &lit_mcu.common,
1207     &big_mcu.common,
1208 };
1209
1210 static struct clk_hw_onecell_data sc9860_aonsecure_clk_hws = {
1211     .hws    = {
1212         [CLK_LIT_MCU]       = &lit_mcu.common.hw,
1213         [CLK_BIG_MCU]       = &big_mcu.common.hw,
1214     },
1215     .num    = CLK_AONSECURE_NUM,
1216 };
1217
1218 static const struct sprd_clk_desc sc9860_aonsecure_clk_desc = {
1219     .clk_clks   = sc9860_aonsecure_clk,
1220     .num_clk_clks   = ARRAY_SIZE(sc9860_aonsecure_clk),
1221     .hw_clks    = &sc9860_aonsecure_clk_hws,
1222 };
1223
1224 static SPRD_SC_GATE_CLK(agcp_iis0_eb,   "agcp-iis0-eb",     "aon-apb",
1225              0x0, 0x100, BIT(0), 0, 0);
1226 static SPRD_SC_GATE_CLK(agcp_iis1_eb,   "agcp-iis1-eb",     "aon-apb",
1227              0x0, 0x100, BIT(1), 0, 0);
1228 static SPRD_SC_GATE_CLK(agcp_iis2_eb,   "agcp-iis2-eb",     "aon-apb",
1229              0x0, 0x100, BIT(2), 0, 0);
1230 static SPRD_SC_GATE_CLK(agcp_iis3_eb,   "agcp-iis3-eb",     "aon-apb",
1231              0x0, 0x100, BIT(3), 0, 0);
1232 static SPRD_SC_GATE_CLK(agcp_uart_eb,   "agcp-uart-eb",     "aon-apb",
1233              0x0, 0x100, BIT(4), 0, 0);
1234 static SPRD_SC_GATE_CLK(agcp_dmacp_eb,  "agcp-dmacp-eb",    "aon-apb",
1235              0x0, 0x100, BIT(5), 0, 0);
1236 static SPRD_SC_GATE_CLK(agcp_dmaap_eb,  "agcp-dmaap-eb",    "aon-apb",
1237              0x0, 0x100, BIT(6), 0, 0);
1238 static SPRD_SC_GATE_CLK(agcp_arc48k_eb, "agcp-arc48k-eb",   "aon-apb",
1239              0x0, 0x100, BIT(10), 0, 0);
1240 static SPRD_SC_GATE_CLK(agcp_src44p1k_eb, "agcp-src44p1k-eb",   "aon-apb",
1241              0x0, 0x100, BIT(11), 0, 0);
1242 static SPRD_SC_GATE_CLK(agcp_mcdt_eb,   "agcp-mcdt-eb",     "aon-apb",
1243              0x0, 0x100, BIT(12), 0, 0);
1244 static SPRD_SC_GATE_CLK(agcp_vbcifd_eb, "agcp-vbcifd-eb",   "aon-apb",
1245              0x0, 0x100, BIT(13), 0, 0);
1246 static SPRD_SC_GATE_CLK(agcp_vbc_eb,    "agcp-vbc-eb",      "aon-apb",
1247              0x0, 0x100, BIT(14), 0, 0);
1248 static SPRD_SC_GATE_CLK(agcp_spinlock_eb, "agcp-spinlock-eb",   "aon-apb",
1249              0x0, 0x100, BIT(15), 0, 0);
1250 static SPRD_SC_GATE_CLK(agcp_icu_eb,    "agcp-icu-eb",      "aon-apb",
1251              0x0, 0x100, BIT(16), CLK_IGNORE_UNUSED, 0);
1252 static SPRD_SC_GATE_CLK(agcp_ap_ashb_eb, "agcp-ap-ashb-eb", "aon-apb",
1253              0x0, 0x100, BIT(17), 0, 0);
1254 static SPRD_SC_GATE_CLK(agcp_cp_ashb_eb, "agcp-cp-ashb-eb", "aon-apb",
1255              0x0, 0x100, BIT(18), 0, 0);
1256 static SPRD_SC_GATE_CLK(agcp_aud_eb,    "agcp-aud-eb",      "aon-apb",
1257              0x0, 0x100, BIT(19), 0, 0);
1258 static SPRD_SC_GATE_CLK(agcp_audif_eb,  "agcp-audif-eb",    "aon-apb",
1259              0x0, 0x100, BIT(20), 0, 0);
1260
1261 static struct sprd_clk_common *sc9860_agcp_gate[] = {
1262     /* address base is 0x415e0000 */
1263     &agcp_iis0_eb.common,
1264     &agcp_iis1_eb.common,
1265     &agcp_iis2_eb.common,
1266     &agcp_iis3_eb.common,
1267     &agcp_uart_eb.common,
1268     &agcp_dmacp_eb.common,
1269     &agcp_dmaap_eb.common,
1270     &agcp_arc48k_eb.common,
1271     &agcp_src44p1k_eb.common,
1272     &agcp_mcdt_eb.common,
1273     &agcp_vbcifd_eb.common,
1274     &agcp_vbc_eb.common,
1275     &agcp_spinlock_eb.common,
1276     &agcp_icu_eb.common,
1277     &agcp_ap_ashb_eb.common,
1278     &agcp_cp_ashb_eb.common,
1279     &agcp_aud_eb.common,
1280     &agcp_audif_eb.common,
1281 };
1282
1283 static struct clk_hw_onecell_data sc9860_agcp_gate_hws = {
1284     .hws    = {
1285         [CLK_AGCP_IIS0_EB]  = &agcp_iis0_eb.common.hw,
1286         [CLK_AGCP_IIS1_EB]  = &agcp_iis1_eb.common.hw,
1287         [CLK_AGCP_IIS2_EB]  = &agcp_iis2_eb.common.hw,
1288         [CLK_AGCP_IIS3_EB]  = &agcp_iis3_eb.common.hw,
1289         [CLK_AGCP_UART_EB]  = &agcp_uart_eb.common.hw,
1290         [CLK_AGCP_DMACP_EB] = &agcp_dmacp_eb.common.hw,
1291         [CLK_AGCP_DMAAP_EB] = &agcp_dmaap_eb.common.hw,
1292         [CLK_AGCP_ARC48K_EB]    = &agcp_arc48k_eb.common.hw,
1293         [CLK_AGCP_SRC44P1K_EB]  = &agcp_src44p1k_eb.common.hw,
1294         [CLK_AGCP_MCDT_EB]  = &agcp_mcdt_eb.common.hw,
1295         [CLK_AGCP_VBCIFD_EB]    = &agcp_vbcifd_eb.common.hw,
1296         [CLK_AGCP_VBC_EB]   = &agcp_vbc_eb.common.hw,
1297         [CLK_AGCP_SPINLOCK_EB]  = &agcp_spinlock_eb.common.hw,
1298         [CLK_AGCP_ICU_EB]   = &agcp_icu_eb.common.hw,
1299         [CLK_AGCP_AP_ASHB_EB]   = &agcp_ap_ashb_eb.common.hw,
1300         [CLK_AGCP_CP_ASHB_EB]   = &agcp_cp_ashb_eb.common.hw,
1301         [CLK_AGCP_AUD_EB]   = &agcp_aud_eb.common.hw,
1302         [CLK_AGCP_AUDIF_EB] = &agcp_audif_eb.common.hw,
1303     },
1304     .num    = CLK_AGCP_GATE_NUM,
1305 };
1306
1307 static const struct sprd_clk_desc sc9860_agcp_gate_desc = {
1308     .clk_clks   = sc9860_agcp_gate,
1309     .num_clk_clks   = ARRAY_SIZE(sc9860_agcp_gate),
1310     .hw_clks    = &sc9860_agcp_gate_hws,
1311 };
1312
1313 static const char * const gpu_parents[] = { "twpll-512m",
1314                         "twpll-768m",
1315                         "gpll" };
1316 static SPRD_COMP_CLK(gpu_clk,   "gpu",  gpu_parents, 0x20,
1317              0, 2, 8, 4, 0);
1318
1319 static struct sprd_clk_common *sc9860_gpu_clk[] = {
1320     /* address base is 0x60200000 */
1321     &gpu_clk.common,
1322 };
1323
1324 static struct clk_hw_onecell_data sc9860_gpu_clk_hws = {
1325     .hws    = {
1326         [CLK_GPU]   = &gpu_clk.common.hw,
1327     },
1328     .num    = CLK_GPU_NUM,
1329 };
1330
1331 static const struct sprd_clk_desc sc9860_gpu_clk_desc = {
1332     .clk_clks   = sc9860_gpu_clk,
1333     .num_clk_clks   = ARRAY_SIZE(sc9860_gpu_clk),
1334     .hw_clks    = &sc9860_gpu_clk_hws,
1335 };
1336
1337 static const char * const ahb_parents[] = { "ext-26m", "twpll-96m",
1338                         "twpll-128m", "twpll-153m6" };
1339 static SPRD_MUX_CLK(ahb_vsp, "ahb-vsp", ahb_parents, 0x20,
1340             0, 2, SC9860_MUX_FLAG);
1341
1342 static const char * const vsp_parents[] = { "twpll-76m8",   "twpll-128m",
1343                         "twpll-256m",   "twpll-307m2",
1344                         "twpll-384m" };
1345 static SPRD_COMP_CLK(vsp_clk, "vsp", vsp_parents, 0x24, 0, 3, 8, 2, 0);
1346
1347 static const char * const dispc_parents[] = {   "twpll-76m8",   "twpll-128m",
1348                         "twpll-256m",   "twpll-307m2" };
1349 static SPRD_COMP_CLK(vsp_enc, "vsp-enc", dispc_parents, 0x28, 0, 2, 8, 2, 0);
1350
1351 static const char * const vpp_parents[] = { "twpll-96m", "twpll-153m6",
1352                         "twpll-192m", "twpll-256m" };
1353 static SPRD_MUX_CLK(vpp_clk, "vpp", vpp_parents, 0x2c,
1354             0, 2, SC9860_MUX_FLAG);
1355 static const char * const vsp_26m_parents[] = { "ext-26m" };
1356 static SPRD_MUX_CLK(vsp_26m, "vsp-26m", vsp_26m_parents, 0x30,
1357             0, 1, SC9860_MUX_FLAG);
1358
1359 static struct sprd_clk_common *sc9860_vsp_clk[] = {
1360     /* address base is 0x61000000 */
1361     &ahb_vsp.common,
1362     &vsp_clk.common,
1363     &vsp_enc.common,
1364     &vpp_clk.common,
1365     &vsp_26m.common,
1366 };
1367
1368 static struct clk_hw_onecell_data sc9860_vsp_clk_hws = {
1369     .hws    = {
1370         [CLK_AHB_VSP]   = &ahb_vsp.common.hw,
1371         [CLK_VSP]   = &vsp_clk.common.hw,
1372         [CLK_VSP_ENC]   = &vsp_enc.common.hw,
1373         [CLK_VPP]   = &vpp_clk.common.hw,
1374         [CLK_VSP_26M]   = &vsp_26m.common.hw,
1375     },
1376     .num    = CLK_VSP_NUM,
1377 };
1378
1379 static const struct sprd_clk_desc sc9860_vsp_clk_desc = {
1380     .clk_clks   = sc9860_vsp_clk,
1381     .num_clk_clks   = ARRAY_SIZE(sc9860_vsp_clk),
1382     .hw_clks    = &sc9860_vsp_clk_hws,
1383 };
1384
1385 static SPRD_SC_GATE_CLK(vsp_dec_eb, "vsp-dec-eb",   "ahb-vsp", 0x0,
1386              0x1000, BIT(0), 0, 0);
1387 static SPRD_SC_GATE_CLK(vsp_ckg_eb, "vsp-ckg-eb",   "ahb-vsp", 0x0,
1388              0x1000, BIT(1), 0, 0);
1389 static SPRD_SC_GATE_CLK(vsp_mmu_eb, "vsp-mmu-eb",   "ahb-vsp", 0x0,
1390              0x1000, BIT(2), 0, 0);
1391 static SPRD_SC_GATE_CLK(vsp_enc_eb, "vsp-enc-eb",   "ahb-vsp", 0x0,
1392              0x1000, BIT(3), 0, 0);
1393 static SPRD_SC_GATE_CLK(vpp_eb,     "vpp-eb",   "ahb-vsp", 0x0,
1394              0x1000, BIT(4), 0, 0);
1395 static SPRD_SC_GATE_CLK(vsp_26m_eb, "vsp-26m-eb",   "ahb-vsp", 0x0,
1396              0x1000, BIT(5), 0, 0);
1397 static SPRD_GATE_CLK(vsp_axi_gate,  "vsp-axi-gate", "ahb-vsp", 0x8,
1398              BIT(0), 0, 0);
1399 static SPRD_GATE_CLK(vsp_enc_gate,  "vsp-enc-gate", "ahb-vsp", 0x8,
1400              BIT(1), 0, 0);
1401 static SPRD_GATE_CLK(vpp_axi_gate,  "vpp-axi-gate", "ahb-vsp", 0x8,
1402              BIT(2), 0, 0);
1403 static SPRD_GATE_CLK(vsp_bm_gate,   "vsp-bm-gate",  "ahb-vsp", 0x8,
1404              BIT(8), 0, 0);
1405 static SPRD_GATE_CLK(vsp_enc_bm_gate, "vsp-enc-bm-gate", "ahb-vsp", 0x8,
1406              BIT(9), 0, 0);
1407 static SPRD_GATE_CLK(vpp_bm_gate,   "vpp-bm-gate",  "ahb-vsp", 0x8,
1408              BIT(10), 0, 0);
1409
1410 static struct sprd_clk_common *sc9860_vsp_gate[] = {
1411     /* address base is 0x61100000 */
1412     &vsp_dec_eb.common,
1413     &vsp_ckg_eb.common,
1414     &vsp_mmu_eb.common,
1415     &vsp_enc_eb.common,
1416     &vpp_eb.common,
1417     &vsp_26m_eb.common,
1418     &vsp_axi_gate.common,
1419     &vsp_enc_gate.common,
1420     &vpp_axi_gate.common,
1421     &vsp_bm_gate.common,
1422     &vsp_enc_bm_gate.common,
1423     &vpp_bm_gate.common,
1424 };
1425
1426 static struct clk_hw_onecell_data sc9860_vsp_gate_hws = {
1427     .hws    = {
1428         [CLK_VSP_DEC_EB]    = &vsp_dec_eb.common.hw,
1429         [CLK_VSP_CKG_EB]    = &vsp_ckg_eb.common.hw,
1430         [CLK_VSP_MMU_EB]    = &vsp_mmu_eb.common.hw,
1431         [CLK_VSP_ENC_EB]    = &vsp_enc_eb.common.hw,
1432         [CLK_VPP_EB]        = &vpp_eb.common.hw,
1433         [CLK_VSP_26M_EB]    = &vsp_26m_eb.common.hw,
1434         [CLK_VSP_AXI_GATE]  = &vsp_axi_gate.common.hw,
1435         [CLK_VSP_ENC_GATE]  = &vsp_enc_gate.common.hw,
1436         [CLK_VPP_AXI_GATE]  = &vpp_axi_gate.common.hw,
1437         [CLK_VSP_BM_GATE]   = &vsp_bm_gate.common.hw,
1438         [CLK_VSP_ENC_BM_GATE]   = &vsp_enc_bm_gate.common.hw,
1439         [CLK_VPP_BM_GATE]   = &vpp_bm_gate.common.hw,
1440     },
1441     .num    = CLK_VSP_GATE_NUM,
1442 };
1443
1444 static const struct sprd_clk_desc sc9860_vsp_gate_desc = {
1445     .clk_clks   = sc9860_vsp_gate,
1446     .num_clk_clks   = ARRAY_SIZE(sc9860_vsp_gate),
1447     .hw_clks    = &sc9860_vsp_gate_hws,
1448 };
1449
1450 static SPRD_MUX_CLK(ahb_cam, "ahb-cam", ahb_parents, 0x20,
1451             0, 2, SC9860_MUX_FLAG);
1452 static const char * const sensor_parents[] = {  "ext-26m",  "twpll-48m",
1453                         "twpll-76m8",   "twpll-96m" };
1454 static SPRD_COMP_CLK(sensor0_clk, "sensor0", sensor_parents, 0x24,
1455              0, 2, 8, 3, 0);
1456 static SPRD_COMP_CLK(sensor1_clk, "sensor1", sensor_parents, 0x28,
1457              0, 2, 8, 3, 0);
1458 static SPRD_COMP_CLK(sensor2_clk, "sensor2", sensor_parents, 0x2c,
1459              0, 2, 8, 3, 0);
1460 static SPRD_GATE_CLK(mipi_csi0_eb, "mipi-csi0-eb", "ahb-cam", 0x4c,
1461              BIT(16), 0, 0);
1462 static SPRD_GATE_CLK(mipi_csi1_eb, "mipi-csi1-eb", "ahb-cam", 0x50,
1463              BIT(16), 0, 0);
1464
1465 static struct sprd_clk_common *sc9860_cam_clk[] = {
1466     /* address base is 0x62000000 */
1467     &ahb_cam.common,
1468     &sensor0_clk.common,
1469     &sensor1_clk.common,
1470     &sensor2_clk.common,
1471     &mipi_csi0_eb.common,
1472     &mipi_csi1_eb.common,
1473 };
1474
1475 static struct clk_hw_onecell_data sc9860_cam_clk_hws = {
1476     .hws    = {
1477         [CLK_AHB_CAM]       = &ahb_cam.common.hw,
1478         [CLK_SENSOR0]       = &sensor0_clk.common.hw,
1479         [CLK_SENSOR1]       = &sensor1_clk.common.hw,
1480         [CLK_SENSOR2]       = &sensor2_clk.common.hw,
1481         [CLK_MIPI_CSI0_EB]  = &mipi_csi0_eb.common.hw,
1482         [CLK_MIPI_CSI1_EB]  = &mipi_csi1_eb.common.hw,
1483     },
1484     .num    = CLK_CAM_NUM,
1485 };
1486
1487 static const struct sprd_clk_desc sc9860_cam_clk_desc = {
1488     .clk_clks   = sc9860_cam_clk,
1489     .num_clk_clks   = ARRAY_SIZE(sc9860_cam_clk),
1490     .hw_clks    = &sc9860_cam_clk_hws,
1491 };
1492
1493 static SPRD_SC_GATE_CLK(dcam0_eb,       "dcam0-eb", "ahb-cam", 0x0,
1494              0x1000, BIT(0), 0, 0);
1495 static SPRD_SC_GATE_CLK(dcam1_eb,       "dcam1-eb", "ahb-cam", 0x0,
1496              0x1000, BIT(1), 0, 0);
1497 static SPRD_SC_GATE_CLK(isp0_eb,        "isp0-eb",  "ahb-cam", 0x0,
1498              0x1000, BIT(2), 0, 0);
1499 static SPRD_SC_GATE_CLK(csi0_eb,        "csi0-eb",  "ahb-cam", 0x0,
1500              0x1000, BIT(3), 0, 0);
1501 static SPRD_SC_GATE_CLK(csi1_eb,        "csi1-eb",  "ahb-cam", 0x0,
1502              0x1000, BIT(4), 0, 0);
1503 static SPRD_SC_GATE_CLK(jpg0_eb,        "jpg0-eb",  "ahb-cam", 0x0,
1504              0x1000, BIT(5), 0, 0);
1505 static SPRD_SC_GATE_CLK(jpg1_eb,        "jpg1-eb",  "ahb-cam", 0x0,
1506              0x1000, BIT(6), 0, 0);
1507 static SPRD_SC_GATE_CLK(cam_ckg_eb, "cam-ckg-eb",   "ahb-cam", 0x0,
1508              0x1000, BIT(7), 0, 0);
1509 static SPRD_SC_GATE_CLK(cam_mmu_eb, "cam-mmu-eb",   "ahb-cam", 0x0,
1510              0x1000, BIT(8), 0, 0);
1511 static SPRD_SC_GATE_CLK(isp1_eb,        "isp1-eb",  "ahb-cam", 0x0,
1512              0x1000, BIT(9), 0, 0);
1513 static SPRD_SC_GATE_CLK(cpp_eb,     "cpp-eb",   "ahb-cam", 0x0,
1514              0x1000, BIT(10), 0, 0);
1515 static SPRD_SC_GATE_CLK(mmu_pf_eb,      "mmu-pf-eb",    "ahb-cam", 0x0,
1516              0x1000, BIT(11), 0, 0);
1517 static SPRD_SC_GATE_CLK(isp2_eb,        "isp2-eb",  "ahb-cam", 0x0,
1518              0x1000, BIT(12), 0, 0);
1519 static SPRD_SC_GATE_CLK(dcam2isp_if_eb, "dcam2isp-if-eb",   "ahb-cam", 0x0,
1520              0x1000, BIT(13), 0, 0);
1521 static SPRD_SC_GATE_CLK(isp2dcam_if_eb, "isp2dcam-if-eb",   "ahb-cam", 0x0,
1522              0x1000, BIT(14), 0, 0);
1523 static SPRD_SC_GATE_CLK(isp_lclk_eb,    "isp-lclk-eb",  "ahb-cam", 0x0,
1524              0x1000, BIT(15), 0, 0);
1525 static SPRD_SC_GATE_CLK(isp_iclk_eb,    "isp-iclk-eb",  "ahb-cam", 0x0,
1526              0x1000, BIT(16), 0, 0);
1527 static SPRD_SC_GATE_CLK(isp_mclk_eb,    "isp-mclk-eb",  "ahb-cam", 0x0,
1528              0x1000, BIT(17), 0, 0);
1529 static SPRD_SC_GATE_CLK(isp_pclk_eb,    "isp-pclk-eb",  "ahb-cam", 0x0,
1530              0x1000, BIT(18), 0, 0);
1531 static SPRD_SC_GATE_CLK(isp_isp2dcam_eb, "isp-isp2dcam-eb", "ahb-cam", 0x0,
1532              0x1000, BIT(19), 0, 0);
1533 static SPRD_SC_GATE_CLK(dcam0_if_eb,    "dcam0-if-eb",  "ahb-cam", 0x0,
1534              0x1000, BIT(20), 0, 0);
1535 static SPRD_SC_GATE_CLK(clk26m_if_eb,   "clk26m-if-eb", "ahb-cam", 0x0,
1536              0x1000, BIT(21), 0, 0);
1537 static SPRD_GATE_CLK(cphy0_gate, "cphy0-gate", "ahb-cam", 0x8,
1538              BIT(0), 0, 0);
1539 static SPRD_GATE_CLK(mipi_csi0_gate, "mipi-csi0-gate", "ahb-cam", 0x8,
1540              BIT(1), 0, 0);
1541 static SPRD_GATE_CLK(cphy1_gate,    "cphy1-gate",   "ahb-cam", 0x8,
1542              BIT(2), 0, 0);
1543 static SPRD_GATE_CLK(mipi_csi1,     "mipi-csi1",    "ahb-cam", 0x8,
1544              BIT(3), 0, 0);
1545 static SPRD_GATE_CLK(dcam0_axi_gate,    "dcam0-axi-gate", "ahb-cam", 0x8,
1546              BIT(4), 0, 0);
1547 static SPRD_GATE_CLK(dcam1_axi_gate,    "dcam1-axi-gate", "ahb-cam", 0x8,
1548              BIT(5), 0, 0);
1549 static SPRD_GATE_CLK(sensor0_gate,  "sensor0-gate", "ahb-cam", 0x8,
1550              BIT(6), 0, 0);
1551 static SPRD_GATE_CLK(sensor1_gate,  "sensor1-gate", "ahb-cam", 0x8,
1552              BIT(7), 0, 0);
1553 static SPRD_GATE_CLK(jpg0_axi_gate, "jpg0-axi-gate", "ahb-cam", 0x8,
1554              BIT(8), 0, 0);
1555 static SPRD_GATE_CLK(gpg1_axi_gate, "gpg1-axi-gate", "ahb-cam", 0x8,
1556              BIT(9), 0, 0);
1557 static SPRD_GATE_CLK(isp0_axi_gate, "isp0-axi-gate", "ahb-cam", 0x8,
1558              BIT(10), 0, 0);
1559 static SPRD_GATE_CLK(isp1_axi_gate, "isp1-axi-gate", "ahb-cam", 0x8,
1560              BIT(11), 0, 0);
1561 static SPRD_GATE_CLK(isp2_axi_gate, "isp2-axi-gate", "ahb-cam", 0x8,
1562              BIT(12), 0, 0);
1563 static SPRD_GATE_CLK(cpp_axi_gate,  "cpp-axi-gate", "ahb-cam", 0x8,
1564              BIT(13), 0, 0);
1565 static SPRD_GATE_CLK(d0_if_axi_gate,    "d0-if-axi-gate", "ahb-cam", 0x8,
1566              BIT(14), 0, 0);
1567 static SPRD_GATE_CLK(d2i_if_axi_gate, "d2i-if-axi-gate", "ahb-cam", 0x8,
1568              BIT(15), 0, 0);
1569 static SPRD_GATE_CLK(i2d_if_axi_gate, "i2d-if-axi-gate", "ahb-cam", 0x8,
1570              BIT(16), 0, 0);
1571 static SPRD_GATE_CLK(spare_axi_gate, "spare-axi-gate",  "ahb-cam", 0x8,
1572              BIT(17), 0, 0);
1573 static SPRD_GATE_CLK(sensor2_gate, "sensor2-gate",  "ahb-cam", 0x8,
1574              BIT(18), 0, 0);
1575 static SPRD_SC_GATE_CLK(d0if_in_d_en, "d0if-in-d-en", "ahb-cam", 0x28,
1576              0x1000, BIT(0), 0, 0);
1577 static SPRD_SC_GATE_CLK(d1if_in_d_en, "d1if-in-d-en", "ahb-cam", 0x28,
1578              0x1000, BIT(1), 0, 0);
1579 static SPRD_SC_GATE_CLK(d0if_in_d2i_en, "d0if-in-d2i-en", "ahb-cam", 0x28,
1580              0x1000, BIT(2), 0, 0);
1581 static SPRD_SC_GATE_CLK(d1if_in_d2i_en, "d1if-in-d2i-en",   "ahb-cam", 0x28,
1582              0x1000, BIT(3), 0, 0);
1583 static SPRD_SC_GATE_CLK(ia_in_d2i_en, "ia-in-d2i-en",   "ahb-cam", 0x28,
1584              0x1000, BIT(4), 0, 0);
1585 static SPRD_SC_GATE_CLK(ib_in_d2i_en,   "ib-in-d2i-en", "ahb-cam", 0x28,
1586              0x1000, BIT(5), 0, 0);
1587 static SPRD_SC_GATE_CLK(ic_in_d2i_en,   "ic-in-d2i-en", "ahb-cam", 0x28,
1588              0x1000, BIT(6), 0, 0);
1589 static SPRD_SC_GATE_CLK(ia_in_i_en, "ia-in-i-en",   "ahb-cam", 0x28,
1590              0x1000, BIT(7), 0, 0);
1591 static SPRD_SC_GATE_CLK(ib_in_i_en, "ib-in-i-en",   "ahb-cam", 0x28,
1592              0x1000, BIT(8), 0, 0);
1593 static SPRD_SC_GATE_CLK(ic_in_i_en, "ic-in-i-en",   "ahb-cam", 0x28,
1594              0x1000, BIT(9), 0, 0);
1595
1596 static struct sprd_clk_common *sc9860_cam_gate[] = {
1597     /* address base is 0x62100000 */
1598     &dcam0_eb.common,
1599     &dcam1_eb.common,
1600     &isp0_eb.common,
1601     &csi0_eb.common,
1602     &csi1_eb.common,
1603     &jpg0_eb.common,
1604     &jpg1_eb.common,
1605     &cam_ckg_eb.common,
1606     &cam_mmu_eb.common,
1607     &isp1_eb.common,
1608     &cpp_eb.common,
1609     &mmu_pf_eb.common,
1610     &isp2_eb.common,
1611     &dcam2isp_if_eb.common,
1612     &isp2dcam_if_eb.common,
1613     &isp_lclk_eb.common,
1614     &isp_iclk_eb.common,
1615     &isp_mclk_eb.common,
1616     &isp_pclk_eb.common,
1617     &isp_isp2dcam_eb.common,
1618     &dcam0_if_eb.common,
1619     &clk26m_if_eb.common,
1620     &cphy0_gate.common,
1621     &mipi_csi0_gate.common,
1622     &cphy1_gate.common,
1623     &mipi_csi1.common,
1624     &dcam0_axi_gate.common,
1625     &dcam1_axi_gate.common,
1626     &sensor0_gate.common,
1627     &sensor1_gate.common,
1628     &jpg0_axi_gate.common,
1629     &gpg1_axi_gate.common,
1630     &isp0_axi_gate.common,
1631     &isp1_axi_gate.common,
1632     &isp2_axi_gate.common,
1633     &cpp_axi_gate.common,
1634     &d0_if_axi_gate.common,
1635     &d2i_if_axi_gate.common,
1636     &i2d_if_axi_gate.common,
1637     &spare_axi_gate.common,
1638     &sensor2_gate.common,
1639     &d0if_in_d_en.common,
1640     &d1if_in_d_en.common,
1641     &d0if_in_d2i_en.common,
1642     &d1if_in_d2i_en.common,
1643     &ia_in_d2i_en.common,
1644     &ib_in_d2i_en.common,
1645     &ic_in_d2i_en.common,
1646     &ia_in_i_en.common,
1647     &ib_in_i_en.common,
1648     &ic_in_i_en.common,
1649 };
1650
1651 static struct clk_hw_onecell_data sc9860_cam_gate_hws = {
1652     .hws    = {
1653         [CLK_DCAM0_EB]      = &dcam0_eb.common.hw,
1654         [CLK_DCAM1_EB]      = &dcam1_eb.common.hw,
1655         [CLK_ISP0_EB]       = &isp0_eb.common.hw,
1656         [CLK_CSI0_EB]       = &csi0_eb.common.hw,
1657         [CLK_CSI1_EB]       = &csi1_eb.common.hw,
1658         [CLK_JPG0_EB]       = &jpg0_eb.common.hw,
1659         [CLK_JPG1_EB]       = &jpg1_eb.common.hw,
1660         [CLK_CAM_CKG_EB]    = &cam_ckg_eb.common.hw,
1661         [CLK_CAM_MMU_EB]    = &cam_mmu_eb.common.hw,
1662         [CLK_ISP1_EB]       = &isp1_eb.common.hw,
1663         [CLK_CPP_EB]        = &cpp_eb.common.hw,
1664         [CLK_MMU_PF_EB]     = &mmu_pf_eb.common.hw,
1665         [CLK_ISP2_EB]       = &isp2_eb.common.hw,
1666         [CLK_DCAM2ISP_IF_EB]    = &dcam2isp_if_eb.common.hw,
1667         [CLK_ISP2DCAM_IF_EB]    = &isp2dcam_if_eb.common.hw,
1668         [CLK_ISP_LCLK_EB]   = &isp_lclk_eb.common.hw,
1669         [CLK_ISP_ICLK_EB]   = &isp_iclk_eb.common.hw,
1670         [CLK_ISP_MCLK_EB]   = &isp_mclk_eb.common.hw,
1671         [CLK_ISP_PCLK_EB]   = &isp_pclk_eb.common.hw,
1672         [CLK_ISP_ISP2DCAM_EB]   = &isp_isp2dcam_eb.common.hw,
1673         [CLK_DCAM0_IF_EB]   = &dcam0_if_eb.common.hw,
1674         [CLK_CLK26M_IF_EB]  = &clk26m_if_eb.common.hw,
1675         [CLK_CPHY0_GATE]    = &cphy0_gate.common.hw,
1676         [CLK_MIPI_CSI0_GATE]    = &mipi_csi0_gate.common.hw,
1677         [CLK_CPHY1_GATE]    = &cphy1_gate.common.hw,
1678         [CLK_MIPI_CSI1]     = &mipi_csi1.common.hw,
1679         [CLK_DCAM0_AXI_GATE]    = &dcam0_axi_gate.common.hw,
1680         [CLK_DCAM1_AXI_GATE]    = &dcam1_axi_gate.common.hw,
1681         [CLK_SENSOR0_GATE]  = &sensor0_gate.common.hw,
1682         [CLK_SENSOR1_GATE]  = &sensor1_gate.common.hw,
1683         [CLK_JPG0_AXI_GATE] = &jpg0_axi_gate.common.hw,
1684         [CLK_GPG1_AXI_GATE] = &gpg1_axi_gate.common.hw,
1685         [CLK_ISP0_AXI_GATE] = &isp0_axi_gate.common.hw,
1686         [CLK_ISP1_AXI_GATE] = &isp1_axi_gate.common.hw,
1687         [CLK_ISP2_AXI_GATE] = &isp2_axi_gate.common.hw,
1688         [CLK_CPP_AXI_GATE]  = &cpp_axi_gate.common.hw,
1689         [CLK_D0_IF_AXI_GATE]    = &d0_if_axi_gate.common.hw,
1690         [CLK_D2I_IF_AXI_GATE]   = &d2i_if_axi_gate.common.hw,
1691         [CLK_I2D_IF_AXI_GATE]   = &i2d_if_axi_gate.common.hw,
1692         [CLK_SPARE_AXI_GATE]    = &spare_axi_gate.common.hw,
1693         [CLK_SENSOR2_GATE]  = &sensor2_gate.common.hw,
1694         [CLK_D0IF_IN_D_EN]  = &d0if_in_d_en.common.hw,
1695         [CLK_D1IF_IN_D_EN]  = &d1if_in_d_en.common.hw,
1696         [CLK_D0IF_IN_D2I_EN]    = &d0if_in_d2i_en.common.hw,
1697         [CLK_D1IF_IN_D2I_EN]    = &d1if_in_d2i_en.common.hw,
1698         [CLK_IA_IN_D2I_EN]  = &ia_in_d2i_en.common.hw,
1699         [CLK_IB_IN_D2I_EN]  = &ib_in_d2i_en.common.hw,
1700         [CLK_IC_IN_D2I_EN]  = &ic_in_d2i_en.common.hw,
1701         [CLK_IA_IN_I_EN]    = &ia_in_i_en.common.hw,
1702         [CLK_IB_IN_I_EN]    = &ib_in_i_en.common.hw,
1703         [CLK_IC_IN_I_EN]    = &ic_in_i_en.common.hw,
1704     },
1705     .num    = CLK_CAM_GATE_NUM,
1706 };
1707
1708 static const struct sprd_clk_desc sc9860_cam_gate_desc = {
1709     .clk_clks   = sc9860_cam_gate,
1710     .num_clk_clks   = ARRAY_SIZE(sc9860_cam_gate),
1711     .hw_clks    = &sc9860_cam_gate_hws,
1712 };
1713
1714 static SPRD_MUX_CLK(ahb_disp, "ahb-disp", ahb_parents, 0x20,
1715             0, 2, SC9860_MUX_FLAG);
1716 static SPRD_COMP_CLK(dispc0_dpi, "dispc0-dpi", dispc_parents,   0x34,
1717              0, 2, 8, 2, 0);
1718 static SPRD_COMP_CLK(dispc1_dpi, "dispc1-dpi", dispc_parents,   0x40,
1719              0, 2, 8, 2, 0);
1720
1721 static struct sprd_clk_common *sc9860_disp_clk[] = {
1722     /* address base is 0x63000000 */
1723     &ahb_disp.common,
1724     &dispc0_dpi.common,
1725     &dispc1_dpi.common,
1726 };
1727
1728 static struct clk_hw_onecell_data sc9860_disp_clk_hws = {
1729     .hws    = {
1730         [CLK_AHB_DISP]      = &ahb_disp.common.hw,
1731         [CLK_DISPC0_DPI]    = &dispc0_dpi.common.hw,
1732         [CLK_DISPC1_DPI]    = &dispc1_dpi.common.hw,
1733     },
1734     .num    = CLK_DISP_NUM,
1735 };
1736
1737 static const struct sprd_clk_desc sc9860_disp_clk_desc = {
1738     .clk_clks   = sc9860_disp_clk,
1739     .num_clk_clks   = ARRAY_SIZE(sc9860_disp_clk),
1740     .hw_clks    = &sc9860_disp_clk_hws,
1741 };
1742
1743 static SPRD_SC_GATE_CLK(dispc0_eb,  "dispc0-eb",    "ahb-disp", 0x0,
1744              0x1000, BIT(0), 0, 0);
1745 static SPRD_SC_GATE_CLK(dispc1_eb,  "dispc1-eb",    "ahb-disp", 0x0,
1746              0x1000, BIT(1), 0, 0);
1747 static SPRD_SC_GATE_CLK(dispc_mmu_eb,   "dispc-mmu-eb", "ahb-disp", 0x0,
1748              0x1000, BIT(2), 0, 0);
1749 static SPRD_SC_GATE_CLK(gsp0_eb,        "gsp0-eb",  "ahb-disp", 0x0,
1750              0x1000, BIT(3), 0, 0);
1751 static SPRD_SC_GATE_CLK(gsp1_eb,        "gsp1-eb",  "ahb-disp", 0x0,
1752              0x1000, BIT(4), 0, 0);
1753 static SPRD_SC_GATE_CLK(gsp0_mmu_eb,    "gsp0-mmu-eb",  "ahb-disp", 0x0,
1754              0x1000, BIT(5), 0, 0);
1755 static SPRD_SC_GATE_CLK(gsp1_mmu_eb,    "gsp1-mmu-eb",  "ahb-disp", 0x0,
1756              0x1000, BIT(6), 0, 0);
1757 static SPRD_SC_GATE_CLK(dsi0_eb,        "dsi0-eb",  "ahb-disp", 0x0,
1758              0x1000, BIT(7), 0, 0);
1759 static SPRD_SC_GATE_CLK(dsi1_eb,        "dsi1-eb",  "ahb-disp", 0x0,
1760              0x1000, BIT(8), 0, 0);
1761 static SPRD_SC_GATE_CLK(disp_ckg_eb,    "disp-ckg-eb",  "ahb-disp", 0x0,
1762              0x1000, BIT(9), 0, 0);
1763 static SPRD_SC_GATE_CLK(disp_gpu_eb,    "disp-gpu-eb",  "ahb-disp", 0x0,
1764              0x1000, BIT(10), 0, 0);
1765 static SPRD_SC_GATE_CLK(gpu_mtx_eb, "gpu-mtx-eb",   "ahb-disp", 0x0,
1766              0x1000, BIT(13), 0, 0);
1767 static SPRD_SC_GATE_CLK(gsp_mtx_eb, "gsp-mtx-eb",   "ahb-disp", 0x0,
1768              0x1000, BIT(14), 0, 0);
1769 static SPRD_SC_GATE_CLK(tmc_mtx_eb, "tmc-mtx-eb",   "ahb-disp", 0x0,
1770              0x1000, BIT(15), 0, 0);
1771 static SPRD_SC_GATE_CLK(dispc_mtx_eb,   "dispc-mtx-eb", "ahb-disp", 0x0,
1772              0x1000, BIT(16), 0, 0);
1773 static SPRD_GATE_CLK(dphy0_gate,    "dphy0-gate",   "ahb-disp", 0x8,
1774              BIT(0), 0, 0);
1775 static SPRD_GATE_CLK(dphy1_gate,    "dphy1-gate",   "ahb-disp", 0x8,
1776              BIT(1), 0, 0);
1777 static SPRD_GATE_CLK(gsp0_a_gate,   "gsp0-a-gate",  "ahb-disp", 0x8,
1778              BIT(2), 0, 0);
1779 static SPRD_GATE_CLK(gsp1_a_gate,   "gsp1-a-gate",  "ahb-disp", 0x8,
1780              BIT(3), 0, 0);
1781 static SPRD_GATE_CLK(gsp0_f_gate,   "gsp0-f-gate",  "ahb-disp", 0x8,
1782              BIT(4), 0, 0);
1783 static SPRD_GATE_CLK(gsp1_f_gate,   "gsp1-f-gate",  "ahb-disp", 0x8,
1784              BIT(5), 0, 0);
1785 static SPRD_GATE_CLK(d_mtx_f_gate,  "d-mtx-f-gate", "ahb-disp", 0x8,
1786              BIT(6), 0, 0);
1787 static SPRD_GATE_CLK(d_mtx_a_gate,  "d-mtx-a-gate", "ahb-disp", 0x8,
1788              BIT(7), 0, 0);
1789 static SPRD_GATE_CLK(d_noc_f_gate,  "d-noc-f-gate", "ahb-disp", 0x8,
1790              BIT(8), 0, 0);
1791 static SPRD_GATE_CLK(d_noc_a_gate,  "d-noc-a-gate", "ahb-disp", 0x8,
1792              BIT(9), 0, 0);
1793 static SPRD_GATE_CLK(gsp_mtx_f_gate, "gsp-mtx-f-gate", "ahb-disp",  0x8,
1794              BIT(10), 0, 0);
1795 static SPRD_GATE_CLK(gsp_mtx_a_gate, "gsp-mtx-a-gate", "ahb-disp",  0x8,
1796              BIT(11), 0, 0);
1797 static SPRD_GATE_CLK(gsp_noc_f_gate, "gsp-noc-f-gate", "ahb-disp",  0x8,
1798              BIT(12), 0, 0);
1799 static SPRD_GATE_CLK(gsp_noc_a_gate, "gsp-noc-a-gate", "ahb-disp",  0x8,
1800              BIT(13), 0, 0);
1801 static SPRD_GATE_CLK(dispm0idle_gate, "dispm0idle-gate", "ahb-disp", 0x8,
1802              BIT(14), 0, 0);
1803 static SPRD_GATE_CLK(gspm0idle_gate, "gspm0idle-gate", "ahb-disp",  0x8,
1804              BIT(15), 0, 0);
1805
1806 static struct sprd_clk_common *sc9860_disp_gate[] = {
1807     /* address base is 0x63100000 */
1808     &dispc0_eb.common,
1809     &dispc1_eb.common,
1810     &dispc_mmu_eb.common,
1811     &gsp0_eb.common,
1812     &gsp1_eb.common,
1813     &gsp0_mmu_eb.common,
1814     &gsp1_mmu_eb.common,
1815     &dsi0_eb.common,
1816     &dsi1_eb.common,
1817     &disp_ckg_eb.common,
1818     &disp_gpu_eb.common,
1819     &gpu_mtx_eb.common,
1820     &gsp_mtx_eb.common,
1821     &tmc_mtx_eb.common,
1822     &dispc_mtx_eb.common,
1823     &dphy0_gate.common,
1824     &dphy1_gate.common,
1825     &gsp0_a_gate.common,
1826     &gsp1_a_gate.common,
1827     &gsp0_f_gate.common,
1828     &gsp1_f_gate.common,
1829     &d_mtx_f_gate.common,
1830     &d_mtx_a_gate.common,
1831     &d_noc_f_gate.common,
1832     &d_noc_a_gate.common,
1833     &gsp_mtx_f_gate.common,
1834     &gsp_mtx_a_gate.common,
1835     &gsp_noc_f_gate.common,
1836     &gsp_noc_a_gate.common,
1837     &dispm0idle_gate.common,
1838     &gspm0idle_gate.common,
1839 };
1840
1841 static struct clk_hw_onecell_data sc9860_disp_gate_hws = {
1842     .hws    = {
1843         [CLK_DISPC0_EB]     = &dispc0_eb.common.hw,
1844         [CLK_DISPC1_EB]     = &dispc1_eb.common.hw,
1845         [CLK_DISPC_MMU_EB]  = &dispc_mmu_eb.common.hw,
1846         [CLK_GSP0_EB]       = &gsp0_eb.common.hw,
1847         [CLK_GSP1_EB]       = &gsp1_eb.common.hw,
1848         [CLK_GSP0_MMU_EB]   = &gsp0_mmu_eb.common.hw,
1849         [CLK_GSP1_MMU_EB]   = &gsp1_mmu_eb.common.hw,
1850         [CLK_DSI0_EB]       = &dsi0_eb.common.hw,
1851         [CLK_DSI1_EB]       = &dsi1_eb.common.hw,
1852         [CLK_DISP_CKG_EB]   = &disp_ckg_eb.common.hw,
1853         [CLK_DISP_GPU_EB]   = &disp_gpu_eb.common.hw,
1854         [CLK_GPU_MTX_EB]    = &gpu_mtx_eb.common.hw,
1855         [CLK_GSP_MTX_EB]    = &gsp_mtx_eb.common.hw,
1856         [CLK_TMC_MTX_EB]    = &tmc_mtx_eb.common.hw,
1857         [CLK_DISPC_MTX_EB]  = &dispc_mtx_eb.common.hw,
1858         [CLK_DPHY0_GATE]    = &dphy0_gate.common.hw,
1859         [CLK_DPHY1_GATE]    = &dphy1_gate.common.hw,
1860         [CLK_GSP0_A_GATE]   = &gsp0_a_gate.common.hw,
1861         [CLK_GSP1_A_GATE]   = &gsp1_a_gate.common.hw,
1862         [CLK_GSP0_F_GATE]   = &gsp0_f_gate.common.hw,
1863         [CLK_GSP1_F_GATE]   = &gsp1_f_gate.common.hw,
1864         [CLK_D_MTX_F_GATE]  = &d_mtx_f_gate.common.hw,
1865         [CLK_D_MTX_A_GATE]  = &d_mtx_a_gate.common.hw,
1866         [CLK_D_NOC_F_GATE]  = &d_noc_f_gate.common.hw,
1867         [CLK_D_NOC_A_GATE]  = &d_noc_a_gate.common.hw,
1868         [CLK_GSP_MTX_F_GATE]    = &gsp_mtx_f_gate.common.hw,
1869         [CLK_GSP_MTX_A_GATE]    = &gsp_mtx_a_gate.common.hw,
1870         [CLK_GSP_NOC_F_GATE]    = &gsp_noc_f_gate.common.hw,
1871         [CLK_GSP_NOC_A_GATE]    = &gsp_noc_a_gate.common.hw,
1872         [CLK_DISPM0IDLE_GATE]   = &dispm0idle_gate.common.hw,
1873         [CLK_GSPM0IDLE_GATE]    = &gspm0idle_gate.common.hw,
1874     },
1875     .num    = CLK_DISP_GATE_NUM,
1876 };
1877
1878 static const struct sprd_clk_desc sc9860_disp_gate_desc = {
1879     .clk_clks   = sc9860_disp_gate,
1880     .num_clk_clks   = ARRAY_SIZE(sc9860_disp_gate),
1881     .hw_clks    = &sc9860_disp_gate_hws,
1882 };
1883
1884 static SPRD_SC_GATE_CLK(sim0_eb,    "sim0-eb",  "ap-apb", 0x0,
1885              0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
1886 static SPRD_SC_GATE_CLK(iis0_eb,    "iis0-eb",  "ap-apb", 0x0,
1887              0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
1888 static SPRD_SC_GATE_CLK(iis1_eb,    "iis1-eb",  "ap-apb", 0x0,
1889              0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
1890 static SPRD_SC_GATE_CLK(iis2_eb,    "iis2-eb",  "ap-apb", 0x0,
1891              0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
1892 static SPRD_SC_GATE_CLK(iis3_eb,    "iis3-eb",  "ap-apb", 0x0,
1893              0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
1894 static SPRD_SC_GATE_CLK(spi0_eb,    "spi0-eb",  "ap-apb", 0x0,
1895              0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
1896 static SPRD_SC_GATE_CLK(spi1_eb,    "spi1-eb",  "ap-apb", 0x0,
1897              0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
1898 static SPRD_SC_GATE_CLK(spi2_eb,    "spi2-eb",  "ap-apb", 0x0,
1899              0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
1900 static SPRD_SC_GATE_CLK(i2c0_eb,    "i2c0-eb",  "ap-apb", 0x0,
1901              0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
1902 static SPRD_SC_GATE_CLK(i2c1_eb,    "i2c1-eb",  "ap-apb", 0x0,
1903              0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
1904 static SPRD_SC_GATE_CLK(i2c2_eb,    "i2c2-eb",  "ap-apb", 0x0,
1905              0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
1906 static SPRD_SC_GATE_CLK(i2c3_eb,    "i2c3-eb",  "ap-apb", 0x0,
1907              0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
1908 static SPRD_SC_GATE_CLK(i2c4_eb,    "i2c4-eb",  "ap-apb", 0x0,
1909              0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
1910 static SPRD_SC_GATE_CLK(i2c5_eb,    "i2c5-eb",  "ap-apb", 0x0,
1911              0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
1912 static SPRD_SC_GATE_CLK(uart0_eb,   "uart0-eb", "ap-apb", 0x0,
1913              0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
1914 static SPRD_SC_GATE_CLK(uart1_eb,   "uart1-eb", "ap-apb", 0x0,
1915              0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
1916 static SPRD_SC_GATE_CLK(uart2_eb,   "uart2-eb", "ap-apb", 0x0,
1917              0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
1918 static SPRD_SC_GATE_CLK(uart3_eb,   "uart3-eb", "ap-apb", 0x0,
1919              0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
1920 static SPRD_SC_GATE_CLK(uart4_eb,   "uart4-eb", "ap-apb", 0x0,
1921              0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
1922 static SPRD_SC_GATE_CLK(ap_ckg_eb,  "ap-ckg-eb",    "ap-apb", 0x0,
1923              0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
1924 static SPRD_SC_GATE_CLK(spi3_eb,    "spi3-eb",  "ap-apb", 0x0,
1925              0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
1926
1927 static struct sprd_clk_common *sc9860_apapb_gate[] = {
1928     /* address base is 0x70b00000 */
1929     &sim0_eb.common,
1930     &iis0_eb.common,
1931     &iis1_eb.common,
1932     &iis2_eb.common,
1933     &iis3_eb.common,
1934     &spi0_eb.common,
1935     &spi1_eb.common,
1936     &spi2_eb.common,
1937     &i2c0_eb.common,
1938     &i2c1_eb.common,
1939     &i2c2_eb.common,
1940     &i2c3_eb.common,
1941     &i2c4_eb.common,
1942     &i2c5_eb.common,
1943     &uart0_eb.common,
1944     &uart1_eb.common,
1945     &uart2_eb.common,
1946     &uart3_eb.common,
1947     &uart4_eb.common,
1948     &ap_ckg_eb.common,
1949     &spi3_eb.common,
1950 };
1951
1952 static struct clk_hw_onecell_data sc9860_apapb_gate_hws = {
1953     .hws    = {
1954         [CLK_SIM0_EB]       = &sim0_eb.common.hw,
1955         [CLK_IIS0_EB]       = &iis0_eb.common.hw,
1956         [CLK_IIS1_EB]       = &iis1_eb.common.hw,
1957         [CLK_IIS2_EB]       = &iis2_eb.common.hw,
1958         [CLK_IIS3_EB]       = &iis3_eb.common.hw,
1959         [CLK_SPI0_EB]       = &spi0_eb.common.hw,
1960         [CLK_SPI1_EB]       = &spi1_eb.common.hw,
1961         [CLK_SPI2_EB]       = &spi2_eb.common.hw,
1962         [CLK_I2C0_EB]       = &i2c0_eb.common.hw,
1963         [CLK_I2C1_EB]       = &i2c1_eb.common.hw,
1964         [CLK_I2C2_EB]       = &i2c2_eb.common.hw,
1965         [CLK_I2C3_EB]       = &i2c3_eb.common.hw,
1966         [CLK_I2C4_EB]       = &i2c4_eb.common.hw,
1967         [CLK_I2C5_EB]       = &i2c5_eb.common.hw,
1968         [CLK_UART0_EB]      = &uart0_eb.common.hw,
1969         [CLK_UART1_EB]      = &uart1_eb.common.hw,
1970         [CLK_UART2_EB]      = &uart2_eb.common.hw,
1971         [CLK_UART3_EB]      = &uart3_eb.common.hw,
1972         [CLK_UART4_EB]      = &uart4_eb.common.hw,
1973         [CLK_AP_CKG_EB]     = &ap_ckg_eb.common.hw,
1974         [CLK_SPI3_EB]       = &spi3_eb.common.hw,
1975     },
1976     .num    = CLK_APAPB_GATE_NUM,
1977 };
1978
1979 static const struct sprd_clk_desc sc9860_apapb_gate_desc = {
1980     .clk_clks   = sc9860_apapb_gate,
1981     .num_clk_clks   = ARRAY_SIZE(sc9860_apapb_gate),
1982     .hw_clks    = &sc9860_apapb_gate_hws,
1983 };
1984
1985 static const struct of_device_id sprd_sc9860_clk_ids[] = {
1986     { .compatible = "sprd,sc9860-pmu-gate",     /* 0x402b */
1987       .data = &sc9860_pmu_gate_desc },
1988     { .compatible = "sprd,sc9860-pll",      /* 0x4040 */
1989       .data = &sc9860_pll_desc },
1990     { .compatible = "sprd,sc9860-ap-clk",       /* 0x2000 */
1991       .data = &sc9860_ap_clk_desc },
1992     { .compatible = "sprd,sc9860-aon-prediv",   /* 0x402d */
1993       .data = &sc9860_aon_prediv_desc },
1994     { .compatible = "sprd,sc9860-apahb-gate",   /* 0x2021 */
1995       .data = &sc9860_apahb_gate_desc },
1996     { .compatible = "sprd,sc9860-aon-gate",     /* 0x402e */
1997       .data = &sc9860_aon_gate_desc },
1998     { .compatible = "sprd,sc9860-aonsecure-clk",    /* 0x4088 */
1999       .data = &sc9860_aonsecure_clk_desc },
2000     { .compatible = "sprd,sc9860-agcp-gate",    /* 0x415e */
2001       .data = &sc9860_agcp_gate_desc },
2002     { .compatible = "sprd,sc9860-gpu-clk",      /* 0x6020 */
2003       .data = &sc9860_gpu_clk_desc },
2004     { .compatible = "sprd,sc9860-vsp-clk",      /* 0x6100 */
2005       .data = &sc9860_vsp_clk_desc },
2006     { .compatible = "sprd,sc9860-vsp-gate",     /* 0x6110 */
2007       .data = &sc9860_vsp_gate_desc },
2008     { .compatible = "sprd,sc9860-cam-clk",      /* 0x6200 */
2009       .data = &sc9860_cam_clk_desc },
2010     { .compatible = "sprd,sc9860-cam-gate",     /* 0x6210 */
2011       .data = &sc9860_cam_gate_desc },
2012     { .compatible = "sprd,sc9860-disp-clk",     /* 0x6300 */
2013       .data = &sc9860_disp_clk_desc },
2014     { .compatible = "sprd,sc9860-disp-gate",    /* 0x6310 */
2015       .data = &sc9860_disp_gate_desc },
2016     { .compatible = "sprd,sc9860-apapb-gate",   /* 0x70b0 */
2017       .data = &sc9860_apapb_gate_desc },
2018     { }
2019 };
2020 MODULE_DEVICE_TABLE(of, sprd_sc9860_clk_ids);
2021
2022 static int sc9860_clk_probe(struct platform_device *pdev)
2023 {
2024     const struct of_device_id *match;
2025     const struct sprd_clk_desc *desc;
2026     int ret;
2027
2028     match = of_match_node(sprd_sc9860_clk_ids, pdev->dev.of_node);
2029     if (!match) {
2030         pr_err("%s: of_match_node() failed", __func__);
2031         return -ENODEV;
2032     }
2033
2034     desc = match->data;
2035     ret = sprd_clk_regmap_init(pdev, desc);
2036     if (ret)
2037         return ret;
2038
2039     return sprd_clk_probe(&pdev->dev, desc->hw_clks);
2040 }
2041
2042 static struct platform_driver sc9860_clk_driver = {
2043     .probe  = sc9860_clk_probe,
2044     .driver = {
2045         .name   = "sc9860-clk",
2046         .of_match_table = sprd_sc9860_clk_ids,
2047     },
2048 };
2049 module_platform_driver(sc9860_clk_driver);
2050
2051 MODULE_DESCRIPTION("Spreadtrum SC9860 Clock Driver");
2052 MODULE_LICENSE("GPL v2");
2053 MODULE_ALIAS("platform:sc9860-clk");