clk/sprd/pll.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 //
0003 // Spreadtrum pll clock driver
0004 //
0005 // Copyright (C) 2015~2017 Spreadtrum, Inc.
0006 // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
0007
0008 #ifndef _SPRD_PLL_H_
0009 #define _SPRD_PLL_H_
0010
0011 #include "common.h"
0012
0013 struct reg_cfg {
0014     u32 val;
0015     u32 msk;
0016 };
0017
0018 struct clk_bit_field {
0019     u8 shift;
0020     u8 width;
0021 };
0022
0023 enum {
0024     PLL_LOCK_DONE,
0025     PLL_DIV_S,
0026     PLL_MOD_EN,
0027     PLL_SDM_EN,
0028     PLL_REFIN,
0029     PLL_IBIAS,
0030     PLL_N,
0031     PLL_NINT,
0032     PLL_KINT,
0033     PLL_PREDIV,
0034     PLL_POSTDIV,
0035
0036     PLL_FACT_MAX
0037 };
0038
0039 /*
0040  * struct sprd_pll - definition of adjustable pll clock
0041  *
0042  * @reg:    registers used to set the configuration of pll clock,
0043  *      reg[0] shows how many registers this pll clock uses.
0044  * @itable: pll ibias table, itable[0] means how many items this
0045  *      table includes
0046  * @udelay  delay time after setting rate
0047  * @factors used to calculate the pll clock rate
0048  * @fvco:   fvco threshold rate
0049  * @fflag:  fvco flag
0050  */
0051 struct sprd_pll {
0052     u32 regs_num;
0053     const u64 *itable;
0054     const struct clk_bit_field *factors;
0055     u16 udelay;
0056     u16 k1;
0057     u16 k2;
0058     u16 fflag;
0059     u64 fvco;
0060
0061     struct sprd_clk_common  common;
0062 };
0063
0064 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg,  \
0065                 _regs_num, _itable, _factors,   \
0066                 _udelay, _k1, _k2, _fflag,      \
0067                 _fvco, _fn)             \
0068     struct sprd_pll _struct = {             \
0069         .regs_num   = _regs_num,            \
0070         .itable     = _itable,          \
0071         .factors    = _factors,         \
0072         .udelay     = _udelay,          \
0073         .k1     = _k1,              \
0074         .k2     = _k2,              \
0075         .fflag      = _fflag,           \
0076         .fvco       = _fvco,            \
0077         .common     = {             \
0078             .regmap     = NULL,         \
0079             .reg        = _reg,         \
0080             .hw.init    = _fn(_name, _parent,   \
0081                           &sprd_pll_ops, 0),\
0082         },                      \
0083     }
0084
0085 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg,  \
0086                     _regs_num, _itable, _factors,   \
0087                     _udelay, _k1, _k2, _fflag, _fvco)   \
0088     SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num,   \
0089                 _itable, _factors, _udelay, _k1, _k2,   \
0090                 _fflag, _fvco, CLK_HW_INIT)
0091
0092 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg,       \
0093                    _regs_num, _itable, _factors,        \
0094                    _udelay, _k1, _k2)           \
0095     SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg,  \
0096                     _regs_num, _itable, _factors,   \
0097                     _udelay, _k1, _k2, 0, 0)
0098
0099 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg,      \
0100                 _regs_num, _itable, _factors, _udelay)  \
0101     SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg,  \
0102                     _regs_num, _itable, _factors,   \
0103                     _udelay, 1000, 1000, 0, 0)
0104
0105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num,  \
0106              _itable, _factors, _udelay, _k1, _k2,      \
0107              _fflag, _fvco)                 \
0108     SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num,   \
0109                 _itable, _factors, _udelay, _k1, _k2,   \
0110                 _fflag, _fvco, CLK_HW_INIT_FW_NAME)
0111
0112 #define SPRD_PLL_HW(_struct, _name, _parent, _reg, _regs_num, _itable,  \
0113             _factors, _udelay, _k1, _k2, _fflag, _fvco)     \
0114     SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num,   \
0115                 _itable, _factors, _udelay, _k1, _k2,   \
0116                 _fflag, _fvco, CLK_HW_INIT_HW)
0117
0118 static inline struct sprd_pll *hw_to_sprd_pll(struct clk_hw *hw)
0119 {
0120     struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
0121
0122     return container_of(common, struct sprd_pll, common);
0123 }
0124
0125 extern const struct clk_ops sprd_pll_ops;
0126
0127 #endif /* _SPRD_PLL_H_ */