clk/sprd/mux.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 //
0003 // Spreadtrum multiplexer clock driver
0004 //
0005 // Copyright (C) 2017 Spreadtrum, Inc.
0006 // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
0007
0008 #ifndef _SPRD_MUX_H_
0009 #define _SPRD_MUX_H_
0010
0011 #include "common.h"
0012
0013 /**
0014  * struct sprd_mux_ssel - Mux clock's source select bits in its register
0015  * @shift: Bit offset of the divider in its register
0016  * @width: Width of the divider field in its register
0017  * @table: For some mux clocks, not all sources are used on some special
0018  *     chips, this matches the value of mux clock's register and the
0019  *     sources which are used for this mux clock
0020  */
0021 struct sprd_mux_ssel {
0022     u8      shift;
0023     u8      width;
0024     const u8    *table;
0025 };
0026
0027 struct sprd_mux {
0028     struct sprd_mux_ssel mux;
0029     struct sprd_clk_common  common;
0030 };
0031
0032 #define _SPRD_MUX_CLK(_shift, _width, _table)       \
0033     {                       \
0034         .shift  = _shift,           \
0035         .width  = _width,           \
0036         .table  = _table,           \
0037     }
0038
0039 #define SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table,   \
0040                 _reg, _shift, _width, _flags, _fn)  \
0041     struct sprd_mux _struct = {                 \
0042         .mux    = _SPRD_MUX_CLK(_shift, _width, _table),    \
0043         .common = {                     \
0044             .regmap     = NULL,             \
0045             .reg        = _reg,             \
0046             .hw.init = _fn(_name, _parents,         \
0047                        &sprd_mux_ops, _flags),      \
0048         }                           \
0049     }
0050
0051 #define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table,        \
0052                _reg, _shift, _width, _flags)        \
0053     SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table,   \
0054                 _reg, _shift, _width, _flags,       \
0055                 CLK_HW_INIT_PARENTS)
0056
0057 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg,        \
0058              _shift, _width, _flags)            \
0059     SPRD_MUX_CLK_TABLE(_struct, _name, _parents, NULL,  \
0060                _reg, _shift, _width, _flags)
0061
0062 #define SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, _table,   \
0063                 _reg, _shift, _width, _flags)       \
0064     SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table,   \
0065                 _reg, _shift, _width, _flags,       \
0066                 CLK_HW_INIT_PARENTS_DATA)
0067
0068 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg,       \
0069               _shift, _width, _flags)           \
0070     SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, NULL,     \
0071                 _reg, _shift, _width, _flags)
0072
0073 static inline struct sprd_mux *hw_to_sprd_mux(const struct clk_hw *hw)
0074 {
0075     struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
0076
0077     return container_of(common, struct sprd_mux, common);
0078 }
0079
0080 extern const struct clk_ops sprd_mux_ops;
0081
0082 u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,
0083                   const struct sprd_mux_ssel *mux);
0084 int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,
0085                    const struct sprd_mux_ssel *mux,
0086                    u8 index);
0087
0088 #endif /* _SPRD_MUX_H_ */