clk/spear/spear6xx_clock.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SPEAr6xx machines clock framework source file
0004  *
0005  * Copyright (C) 2012 ST Microelectronics
0006  * Viresh Kumar <vireshk@kernel.org>
0007  */
0008
0009 #include <linux/clkdev.h>
0010 #include <linux/io.h>
0011 #include <linux/spinlock_types.h>
0012 #include "clk.h"
0013
0014 static DEFINE_SPINLOCK(_lock);
0015
0016 #define PLL1_CTR            (misc_base + 0x008)
0017 #define PLL1_FRQ            (misc_base + 0x00C)
0018 #define PLL2_CTR            (misc_base + 0x014)
0019 #define PLL2_FRQ            (misc_base + 0x018)
0020 #define PLL_CLK_CFG         (misc_base + 0x020)
0021     /* PLL_CLK_CFG register masks */
0022     #define MCTR_CLK_SHIFT      28
0023     #define MCTR_CLK_MASK       3
0024
0025 #define CORE_CLK_CFG            (misc_base + 0x024)
0026     /* CORE CLK CFG register masks */
0027     #define HCLK_RATIO_SHIFT    10
0028     #define HCLK_RATIO_MASK     2
0029     #define PCLK_RATIO_SHIFT    8
0030     #define PCLK_RATIO_MASK     2
0031
0032 #define PERIP_CLK_CFG           (misc_base + 0x028)
0033     /* PERIP_CLK_CFG register masks */
0034     #define CLCD_CLK_SHIFT      2
0035     #define CLCD_CLK_MASK       2
0036     #define UART_CLK_SHIFT      4
0037     #define UART_CLK_MASK       1
0038     #define FIRDA_CLK_SHIFT     5
0039     #define FIRDA_CLK_MASK      2
0040     #define GPT0_CLK_SHIFT      8
0041     #define GPT1_CLK_SHIFT      10
0042     #define GPT2_CLK_SHIFT      11
0043     #define GPT3_CLK_SHIFT      12
0044     #define GPT_CLK_MASK        1
0045
0046 #define PERIP1_CLK_ENB          (misc_base + 0x02C)
0047     /* PERIP1_CLK_ENB register masks */
0048     #define UART0_CLK_ENB       3
0049     #define UART1_CLK_ENB       4
0050     #define SSP0_CLK_ENB        5
0051     #define SSP1_CLK_ENB        6
0052     #define I2C_CLK_ENB     7
0053     #define JPEG_CLK_ENB        8
0054     #define FSMC_CLK_ENB        9
0055     #define FIRDA_CLK_ENB       10
0056     #define GPT2_CLK_ENB        11
0057     #define GPT3_CLK_ENB        12
0058     #define GPIO2_CLK_ENB       13
0059     #define SSP2_CLK_ENB        14
0060     #define ADC_CLK_ENB     15
0061     #define GPT1_CLK_ENB        11
0062     #define RTC_CLK_ENB     17
0063     #define GPIO1_CLK_ENB       18
0064     #define DMA_CLK_ENB     19
0065     #define SMI_CLK_ENB     21
0066     #define CLCD_CLK_ENB        22
0067     #define GMAC_CLK_ENB        23
0068     #define USBD_CLK_ENB        24
0069     #define USBH0_CLK_ENB       25
0070     #define USBH1_CLK_ENB       26
0071
0072 #define PRSC0_CLK_CFG           (misc_base + 0x044)
0073 #define PRSC1_CLK_CFG           (misc_base + 0x048)
0074 #define PRSC2_CLK_CFG           (misc_base + 0x04C)
0075
0076 #define CLCD_CLK_SYNT           (misc_base + 0x05C)
0077 #define FIRDA_CLK_SYNT          (misc_base + 0x060)
0078 #define UART_CLK_SYNT           (misc_base + 0x064)
0079
0080 /* vco rate configuration table, in ascending order of rates */
0081 static struct pll_rate_tbl pll_rtbl[] = {
0082     {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
0083     {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
0084     {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
0085 };
0086
0087 /* aux rate configuration table, in ascending order of rates */
0088 static struct aux_rate_tbl aux_rtbl[] = {
0089     /* For PLL1 = 332 MHz */
0090     {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
0091     {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
0092     {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
0093     {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
0094 };
0095
0096 static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
0097 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
0098 static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
0099 static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
0100 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
0101 static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
0102 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
0103     "pll2_clk", };
0104
0105 /* gpt rate configuration table, in ascending order of rates */
0106 static struct gpt_rate_tbl gpt_rtbl[] = {
0107     /* For pll1 = 332 MHz */
0108     {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
0109     {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
0110     {.mscale = 1, .nscale = 0}, /* 83 MHz */
0111 };
0112
0113 void __init spear6xx_clk_init(void __iomem *misc_base)
0114 {
0115     struct clk *clk, *clk1;
0116
0117     clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
0118     clk_register_clkdev(clk, "osc_32k_clk", NULL);
0119
0120     clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000);
0121     clk_register_clkdev(clk, "osc_30m_clk", NULL);
0122
0123     /* clock derived from 32 KHz osc clk */
0124     clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
0125             PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
0126     clk_register_clkdev(clk, NULL, "rtc-spear");
0127
0128     /* clock derived from 30 MHz osc clk */
0129     clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
0130             48000000);
0131     clk_register_clkdev(clk, "pll3_clk", NULL);
0132
0133     clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
0134             0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
0135             &_lock, &clk1, NULL);
0136     clk_register_clkdev(clk, "vco1_clk", NULL);
0137     clk_register_clkdev(clk1, "pll1_clk", NULL);
0138
0139     clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
0140             0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
0141             &_lock, &clk1, NULL);
0142     clk_register_clkdev(clk, "vco2_clk", NULL);
0143     clk_register_clkdev(clk1, "pll2_clk", NULL);
0144
0145     clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
0146             1);
0147     clk_register_clkdev(clk, NULL, "fc880000.wdt");
0148
0149     /* clock derived from pll1 clk */
0150     clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
0151             CLK_SET_RATE_PARENT, 1, 1);
0152     clk_register_clkdev(clk, "cpu_clk", NULL);
0153
0154     clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
0155             CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
0156             HCLK_RATIO_MASK, 0, &_lock);
0157     clk_register_clkdev(clk, "ahb_clk", NULL);
0158
0159     clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
0160             UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
0161             &_lock, &clk1);
0162     clk_register_clkdev(clk, "uart_syn_clk", NULL);
0163     clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
0164
0165     clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
0166             ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
0167             PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
0168             &_lock);
0169     clk_register_clkdev(clk, "uart_mclk", NULL);
0170
0171     clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
0172             UART0_CLK_ENB, 0, &_lock);
0173     clk_register_clkdev(clk, NULL, "d0000000.serial");
0174
0175     clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
0176             UART1_CLK_ENB, 0, &_lock);
0177     clk_register_clkdev(clk, NULL, "d0080000.serial");
0178
0179     clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
0180             0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
0181             &_lock, &clk1);
0182     clk_register_clkdev(clk, "firda_syn_clk", NULL);
0183     clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
0184
0185     clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
0186             ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
0187             PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
0188             &_lock);
0189     clk_register_clkdev(clk, "firda_mclk", NULL);
0190
0191     clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
0192             PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
0193     clk_register_clkdev(clk, NULL, "firda");
0194
0195     clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
0196             0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
0197             &_lock, &clk1);
0198     clk_register_clkdev(clk, "clcd_syn_clk", NULL);
0199     clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
0200
0201     clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
0202             ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
0203             PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
0204             &_lock);
0205     clk_register_clkdev(clk, "clcd_mclk", NULL);
0206
0207     clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
0208             PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
0209     clk_register_clkdev(clk, NULL, "clcd");
0210
0211     /* gpt clocks */
0212     clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
0213             gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
0214     clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
0215
0216     clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
0217             ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
0218             PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
0219     clk_register_clkdev(clk, NULL, "gpt0");
0220
0221     clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
0222             ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
0223             PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
0224     clk_register_clkdev(clk, "gpt1_mclk", NULL);
0225
0226     clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
0227             PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
0228     clk_register_clkdev(clk, NULL, "gpt1");
0229
0230     clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
0231             gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
0232     clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
0233
0234     clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
0235             ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
0236             PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
0237     clk_register_clkdev(clk, "gpt2_mclk", NULL);
0238
0239     clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
0240             PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
0241     clk_register_clkdev(clk, NULL, "gpt2");
0242
0243     clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
0244             gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
0245     clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
0246
0247     clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
0248             ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
0249             PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
0250     clk_register_clkdev(clk, "gpt3_mclk", NULL);
0251
0252     clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
0253             PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
0254     clk_register_clkdev(clk, NULL, "gpt3");
0255
0256     /* clock derived from pll3 clk */
0257     clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
0258             PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
0259     clk_register_clkdev(clk, NULL, "e1800000.ehci");
0260     clk_register_clkdev(clk, NULL, "e1900000.ohci");
0261
0262     clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
0263             PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
0264     clk_register_clkdev(clk, NULL, "e2000000.ehci");
0265     clk_register_clkdev(clk, NULL, "e2100000.ohci");
0266
0267     clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
0268             USBD_CLK_ENB, 0, &_lock);
0269     clk_register_clkdev(clk, NULL, "designware_udc");
0270
0271     /* clock derived from ahb clk */
0272     clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
0273             1);
0274     clk_register_clkdev(clk, "ahbmult2_clk", NULL);
0275
0276     clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
0277             ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
0278             PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
0279     clk_register_clkdev(clk, "ddr_clk", NULL);
0280
0281     clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
0282             CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
0283             PCLK_RATIO_MASK, 0, &_lock);
0284     clk_register_clkdev(clk, "apb_clk", NULL);
0285
0286     clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
0287             DMA_CLK_ENB, 0, &_lock);
0288     clk_register_clkdev(clk, NULL, "fc400000.dma");
0289
0290     clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
0291             FSMC_CLK_ENB, 0, &_lock);
0292     clk_register_clkdev(clk, NULL, "d1800000.flash");
0293
0294     clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
0295             GMAC_CLK_ENB, 0, &_lock);
0296     clk_register_clkdev(clk, NULL, "e0800000.ethernet");
0297
0298     clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
0299             I2C_CLK_ENB, 0, &_lock);
0300     clk_register_clkdev(clk, NULL, "d0200000.i2c");
0301
0302     clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
0303             JPEG_CLK_ENB, 0, &_lock);
0304     clk_register_clkdev(clk, NULL, "jpeg");
0305
0306     clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
0307             SMI_CLK_ENB, 0, &_lock);
0308     clk_register_clkdev(clk, NULL, "fc000000.flash");
0309
0310     /* clock derived from apb clk */
0311     clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
0312             ADC_CLK_ENB, 0, &_lock);
0313     clk_register_clkdev(clk, NULL, "d820b000.adc");
0314
0315     clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
0316     clk_register_clkdev(clk, NULL, "f0100000.gpio");
0317
0318     clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
0319             GPIO1_CLK_ENB, 0, &_lock);
0320     clk_register_clkdev(clk, NULL, "fc980000.gpio");
0321
0322     clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
0323             GPIO2_CLK_ENB, 0, &_lock);
0324     clk_register_clkdev(clk, NULL, "d8100000.gpio");
0325
0326     clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
0327             SSP0_CLK_ENB, 0, &_lock);
0328     clk_register_clkdev(clk, NULL, "ssp-pl022.0");
0329
0330     clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
0331             SSP1_CLK_ENB, 0, &_lock);
0332     clk_register_clkdev(clk, NULL, "ssp-pl022.1");
0333
0334     clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
0335             SSP2_CLK_ENB, 0, &_lock);
0336     clk_register_clkdev(clk, NULL, "ssp-pl022.2");
0337 }