clk/spear/clk.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Clock framework definitions for SPEAr platform
0004  *
0005  * Copyright (C) 2012 ST Microelectronics
0006  * Viresh Kumar <vireshk@kernel.org>
0007  */
0008
0009 #ifndef __SPEAR_CLK_H
0010 #define __SPEAR_CLK_H
0011
0012 #include <linux/clk-provider.h>
0013 #include <linux/spinlock_types.h>
0014 #include <linux/types.h>
0015
0016 /* Auxiliary Synth clk */
0017 /* Default masks */
0018 #define AUX_EQ_SEL_SHIFT    30
0019 #define AUX_EQ_SEL_MASK     1
0020 #define AUX_EQ1_SEL     0
0021 #define AUX_EQ2_SEL     1
0022 #define AUX_XSCALE_SHIFT    16
0023 #define AUX_XSCALE_MASK     0xFFF
0024 #define AUX_YSCALE_SHIFT    0
0025 #define AUX_YSCALE_MASK     0xFFF
0026 #define AUX_SYNT_ENB        31
0027
0028 struct aux_clk_masks {
0029     u32 eq_sel_mask;
0030     u32 eq_sel_shift;
0031     u32 eq1_mask;
0032     u32 eq2_mask;
0033     u32 xscale_sel_mask;
0034     u32 xscale_sel_shift;
0035     u32 yscale_sel_mask;
0036     u32 yscale_sel_shift;
0037     u32 enable_bit;
0038 };
0039
0040 struct aux_rate_tbl {
0041     u16 xscale;
0042     u16 yscale;
0043     u8 eq;
0044 };
0045
0046 struct clk_aux {
0047     struct          clk_hw hw;
0048     void __iomem        *reg;
0049     const struct aux_clk_masks *masks;
0050     struct aux_rate_tbl *rtbl;
0051     u8          rtbl_cnt;
0052     spinlock_t      *lock;
0053 };
0054
0055 /* Fractional Synth clk */
0056 struct frac_rate_tbl {
0057     u32 div;
0058 };
0059
0060 struct clk_frac {
0061     struct          clk_hw hw;
0062     void __iomem        *reg;
0063     struct frac_rate_tbl    *rtbl;
0064     u8          rtbl_cnt;
0065     spinlock_t      *lock;
0066 };
0067
0068 /* GPT clk */
0069 struct gpt_rate_tbl {
0070     u16 mscale;
0071     u16 nscale;
0072 };
0073
0074 struct clk_gpt {
0075     struct          clk_hw hw;
0076     void __iomem        *reg;
0077     struct gpt_rate_tbl *rtbl;
0078     u8          rtbl_cnt;
0079     spinlock_t      *lock;
0080 };
0081
0082 /* VCO-PLL clk */
0083 struct pll_rate_tbl {
0084     u8 mode;
0085     u16 m;
0086     u8 n;
0087     u8 p;
0088 };
0089
0090 struct clk_vco {
0091     struct          clk_hw hw;
0092     void __iomem        *mode_reg;
0093     void __iomem        *cfg_reg;
0094     struct pll_rate_tbl *rtbl;
0095     u8          rtbl_cnt;
0096     spinlock_t      *lock;
0097 };
0098
0099 struct clk_pll {
0100     struct          clk_hw hw;
0101     struct clk_vco      *vco;
0102     const char      *parent[1];
0103     spinlock_t      *lock;
0104 };
0105
0106 typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
0107         int index);
0108
0109 /* clk register routines */
0110 struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
0111         const char *parent_name, unsigned long flags, void __iomem *reg,
0112         const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
0113         u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk);
0114 struct clk *clk_register_frac(const char *name, const char *parent_name,
0115         unsigned long flags, void __iomem *reg,
0116         struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock);
0117 struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
0118         long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
0119         rtbl_cnt, spinlock_t *lock);
0120 struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
0121         const char *vco_gate_name, const char *parent_name,
0122         unsigned long flags, void __iomem *mode_reg, void __iomem
0123         *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
0124         spinlock_t *lock, struct clk **pll_clk,
0125         struct clk **vco_gate_clk);
0126
0127 long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
0128         unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
0129         int *index);
0130
0131 #endif /* __SPEAR_CLK_H */