clk/spear/clk-vco-pll.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2012 ST Microelectronics
0004  * Viresh Kumar <vireshk@kernel.org>
0005  *
0006  * VCO-PLL clock implementation
0007  */
0008
0009 #define pr_fmt(fmt) "clk-vco-pll: " fmt
0010
0011 #include <linux/clk-provider.h>
0012 #include <linux/slab.h>
0013 #include <linux/io.h>
0014 #include <linux/err.h>
0015 #include "clk.h"
0016
0017 /*
0018  * DOC: VCO-PLL clock
0019  *
0020  * VCO and PLL rate are derived from following equations:
0021  *
0022  * In normal mode
0023  * vco = (2 * M[15:8] * Fin)/N
0024  *
0025  * In Dithered mode
0026  * vco = (2 * M[15:0] * Fin)/(256 * N)
0027  *
0028  * pll_rate = pll/2^p
0029  *
0030  * vco and pll are very closely bound to each other, "vco needs to program:
0031  * mode, m & n" and "pll needs to program p", both share common enable/disable
0032  * logic.
0033  *
0034  * clk_register_vco_pll() registers instances of both vco & pll.
0035  * CLK_SET_RATE_PARENT flag is forced for pll, as it will always pass its
0036  * set_rate to vco. A single rate table exists for both the clocks, which
0037  * configures m, n and p.
0038  */
0039
0040 /* PLL_CTR register masks */
0041 #define PLL_MODE_NORMAL     0
0042 #define PLL_MODE_FRACTION   1
0043 #define PLL_MODE_DITH_DSM   2
0044 #define PLL_MODE_DITH_SSM   3
0045 #define PLL_MODE_MASK       3
0046 #define PLL_MODE_SHIFT      3
0047 #define PLL_ENABLE      2
0048
0049 #define PLL_LOCK_SHIFT      0
0050 #define PLL_LOCK_MASK       1
0051
0052 /* PLL FRQ register masks */
0053 #define PLL_NORM_FDBK_M_MASK    0xFF
0054 #define PLL_NORM_FDBK_M_SHIFT   24
0055 #define PLL_DITH_FDBK_M_MASK    0xFFFF
0056 #define PLL_DITH_FDBK_M_SHIFT   16
0057 #define PLL_DIV_P_MASK      0x7
0058 #define PLL_DIV_P_SHIFT     8
0059 #define PLL_DIV_N_MASK      0xFF
0060 #define PLL_DIV_N_SHIFT     0
0061
0062 #define to_clk_vco(_hw) container_of(_hw, struct clk_vco, hw)
0063 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
0064
0065 /* Calculates pll clk rate for specific value of mode, m, n and p */
0066 static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl,
0067         unsigned long prate, int index, unsigned long *pll_rate)
0068 {
0069     unsigned long rate = prate;
0070     unsigned int mode;
0071
0072     mode = rtbl[index].mode ? 256 : 1;
0073     rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n));
0074
0075     if (pll_rate)
0076         *pll_rate = (rate / (1 << rtbl[index].p)) * 10000;
0077
0078     return rate * 10000;
0079 }
0080
0081 static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate,
0082                 unsigned long *prate, int *index)
0083 {
0084     struct clk_pll *pll = to_clk_pll(hw);
0085     unsigned long prev_rate, vco_prev_rate, rate = 0;
0086     unsigned long vco_parent_rate =
0087         clk_hw_get_rate(clk_hw_get_parent(clk_hw_get_parent(hw)));
0088
0089     if (!prate) {
0090         pr_err("%s: prate is must for pll clk\n", __func__);
0091         return -EINVAL;
0092     }
0093
0094     for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) {
0095         prev_rate = rate;
0096         vco_prev_rate = *prate;
0097         *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,
0098                 &rate);
0099         if (drate < rate) {
0100             /* previous clock was best */
0101             if (*index) {
0102                 rate = prev_rate;
0103                 *prate = vco_prev_rate;
0104                 (*index)--;
0105             }
0106             break;
0107         }
0108     }
0109
0110     return rate;
0111 }
0112
0113 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long drate,
0114                 unsigned long *prate)
0115 {
0116     int unused;
0117
0118     return clk_pll_round_rate_index(hw, drate, prate, &unused);
0119 }
0120
0121 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long
0122         parent_rate)
0123 {
0124     struct clk_pll *pll = to_clk_pll(hw);
0125     unsigned long flags = 0;
0126     unsigned int p;
0127
0128     if (pll->vco->lock)
0129         spin_lock_irqsave(pll->vco->lock, flags);
0130
0131     p = readl_relaxed(pll->vco->cfg_reg);
0132
0133     if (pll->vco->lock)
0134         spin_unlock_irqrestore(pll->vco->lock, flags);
0135
0136     p = (p >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
0137
0138     return parent_rate / (1 << p);
0139 }
0140
0141 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long drate,
0142                 unsigned long prate)
0143 {
0144     struct clk_pll *pll = to_clk_pll(hw);
0145     struct pll_rate_tbl *rtbl = pll->vco->rtbl;
0146     unsigned long flags = 0, val;
0147     int i = 0;
0148
0149     clk_pll_round_rate_index(hw, drate, NULL, &i);
0150
0151     if (pll->vco->lock)
0152         spin_lock_irqsave(pll->vco->lock, flags);
0153
0154     val = readl_relaxed(pll->vco->cfg_reg);
0155     val &= ~(PLL_DIV_P_MASK << PLL_DIV_P_SHIFT);
0156     val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT;
0157     writel_relaxed(val, pll->vco->cfg_reg);
0158
0159     if (pll->vco->lock)
0160         spin_unlock_irqrestore(pll->vco->lock, flags);
0161
0162     return 0;
0163 }
0164
0165 static const struct clk_ops clk_pll_ops = {
0166     .recalc_rate = clk_pll_recalc_rate,
0167     .round_rate = clk_pll_round_rate,
0168     .set_rate = clk_pll_set_rate,
0169 };
0170
0171 static inline unsigned long vco_calc_rate(struct clk_hw *hw,
0172         unsigned long prate, int index)
0173 {
0174     struct clk_vco *vco = to_clk_vco(hw);
0175
0176     return pll_calc_rate(vco->rtbl, prate, index, NULL);
0177 }
0178
0179 static long clk_vco_round_rate(struct clk_hw *hw, unsigned long drate,
0180         unsigned long *prate)
0181 {
0182     struct clk_vco *vco = to_clk_vco(hw);
0183     int unused;
0184
0185     return clk_round_rate_index(hw, drate, *prate, vco_calc_rate,
0186             vco->rtbl_cnt, &unused);
0187 }
0188
0189 static unsigned long clk_vco_recalc_rate(struct clk_hw *hw,
0190         unsigned long parent_rate)
0191 {
0192     struct clk_vco *vco = to_clk_vco(hw);
0193     unsigned long flags = 0;
0194     unsigned int num = 2, den = 0, val, mode = 0;
0195
0196     if (vco->lock)
0197         spin_lock_irqsave(vco->lock, flags);
0198
0199     mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
0200
0201     val = readl_relaxed(vco->cfg_reg);
0202
0203     if (vco->lock)
0204         spin_unlock_irqrestore(vco->lock, flags);
0205
0206     den = (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
0207
0208     /* calculate numerator & denominator */
0209     if (!mode) {
0210         /* Normal mode */
0211         num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
0212     } else {
0213         /* Dithered mode */
0214         num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
0215         den *= 256;
0216     }
0217
0218     if (!den) {
0219         WARN(1, "%s: denominator can't be zero\n", __func__);
0220         return 0;
0221     }
0222
0223     return (((parent_rate / 10000) * num) / den) * 10000;
0224 }
0225
0226 /* Configures new clock rate of vco */
0227 static int clk_vco_set_rate(struct clk_hw *hw, unsigned long drate,
0228                 unsigned long prate)
0229 {
0230     struct clk_vco *vco = to_clk_vco(hw);
0231     struct pll_rate_tbl *rtbl = vco->rtbl;
0232     unsigned long flags = 0, val;
0233     int i;
0234
0235     clk_round_rate_index(hw, drate, prate, vco_calc_rate, vco->rtbl_cnt,
0236             &i);
0237
0238     if (vco->lock)
0239         spin_lock_irqsave(vco->lock, flags);
0240
0241     val = readl_relaxed(vco->mode_reg);
0242     val &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
0243     val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT;
0244     writel_relaxed(val, vco->mode_reg);
0245
0246     val = readl_relaxed(vco->cfg_reg);
0247     val &= ~(PLL_DIV_N_MASK << PLL_DIV_N_SHIFT);
0248     val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT;
0249
0250     val &= ~(PLL_DITH_FDBK_M_MASK << PLL_DITH_FDBK_M_SHIFT);
0251     if (rtbl[i].mode)
0252         val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) <<
0253             PLL_DITH_FDBK_M_SHIFT;
0254     else
0255         val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) <<
0256             PLL_NORM_FDBK_M_SHIFT;
0257
0258     writel_relaxed(val, vco->cfg_reg);
0259
0260     if (vco->lock)
0261         spin_unlock_irqrestore(vco->lock, flags);
0262
0263     return 0;
0264 }
0265
0266 static const struct clk_ops clk_vco_ops = {
0267     .recalc_rate = clk_vco_recalc_rate,
0268     .round_rate = clk_vco_round_rate,
0269     .set_rate = clk_vco_set_rate,
0270 };
0271
0272 struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
0273         const char *vco_gate_name, const char *parent_name,
0274         unsigned long flags, void __iomem *mode_reg, void __iomem
0275         *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
0276         spinlock_t *lock, struct clk **pll_clk,
0277         struct clk **vco_gate_clk)
0278 {
0279     struct clk_vco *vco;
0280     struct clk_pll *pll;
0281     struct clk *vco_clk, *tpll_clk, *tvco_gate_clk;
0282     struct clk_init_data vco_init, pll_init;
0283     const char **vco_parent_name;
0284
0285     if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg ||
0286             !rtbl || !rtbl_cnt) {
0287         pr_err("Invalid arguments passed");
0288         return ERR_PTR(-EINVAL);
0289     }
0290
0291     vco = kzalloc(sizeof(*vco), GFP_KERNEL);
0292     if (!vco)
0293         return ERR_PTR(-ENOMEM);
0294
0295     pll = kzalloc(sizeof(*pll), GFP_KERNEL);
0296     if (!pll)
0297         goto free_vco;
0298
0299     /* struct clk_vco assignments */
0300     vco->mode_reg = mode_reg;
0301     vco->cfg_reg = cfg_reg;
0302     vco->rtbl = rtbl;
0303     vco->rtbl_cnt = rtbl_cnt;
0304     vco->lock = lock;
0305     vco->hw.init = &vco_init;
0306
0307     pll->vco = vco;
0308     pll->hw.init = &pll_init;
0309
0310     if (vco_gate_name) {
0311         tvco_gate_clk = clk_register_gate(NULL, vco_gate_name,
0312                 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock);
0313         if (IS_ERR_OR_NULL(tvco_gate_clk))
0314             goto free_pll;
0315
0316         if (vco_gate_clk)
0317             *vco_gate_clk = tvco_gate_clk;
0318         vco_parent_name = &vco_gate_name;
0319     } else {
0320         vco_parent_name = &parent_name;
0321     }
0322
0323     vco_init.name = vco_name;
0324     vco_init.ops = &clk_vco_ops;
0325     vco_init.flags = flags;
0326     vco_init.parent_names = vco_parent_name;
0327     vco_init.num_parents = 1;
0328
0329     pll_init.name = pll_name;
0330     pll_init.ops = &clk_pll_ops;
0331     pll_init.flags = CLK_SET_RATE_PARENT;
0332     pll_init.parent_names = &vco_name;
0333     pll_init.num_parents = 1;
0334
0335     vco_clk = clk_register(NULL, &vco->hw);
0336     if (IS_ERR_OR_NULL(vco_clk))
0337         goto free_pll;
0338
0339     tpll_clk = clk_register(NULL, &pll->hw);
0340     if (IS_ERR_OR_NULL(tpll_clk))
0341         goto free_pll;
0342
0343     if (pll_clk)
0344         *pll_clk = tpll_clk;
0345
0346     return vco_clk;
0347
0348 free_pll:
0349     kfree(pll);
0350 free_vco:
0351     kfree(vco);
0352
0353     pr_err("Failed to register vco pll clock\n");
0354
0355     return ERR_PTR(-ENOMEM);
0356 }