clk/spear/clk-aux-synth.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2012 ST Microelectronics
0004  * Viresh Kumar <vireshk@kernel.org>
0005  *
0006  * Auxiliary Synthesizer clock implementation
0007  */
0008
0009 #define pr_fmt(fmt) "clk-aux-synth: " fmt
0010
0011 #include <linux/clk-provider.h>
0012 #include <linux/slab.h>
0013 #include <linux/io.h>
0014 #include <linux/err.h>
0015 #include "clk.h"
0016
0017 /*
0018  * DOC: Auxiliary Synthesizer clock
0019  *
0020  * Aux synth gives rate for different values of eq, x and y
0021  *
0022  * Fout from synthesizer can be given from two equations:
0023  * Fout1 = (Fin * X/Y)/2        EQ1
0024  * Fout2 = Fin * X/Y            EQ2
0025  */
0026
0027 #define to_clk_aux(_hw) container_of(_hw, struct clk_aux, hw)
0028
0029 static const  struct aux_clk_masks default_aux_masks = {
0030     .eq_sel_mask = AUX_EQ_SEL_MASK,
0031     .eq_sel_shift = AUX_EQ_SEL_SHIFT,
0032     .eq1_mask = AUX_EQ1_SEL,
0033     .eq2_mask = AUX_EQ2_SEL,
0034     .xscale_sel_mask = AUX_XSCALE_MASK,
0035     .xscale_sel_shift = AUX_XSCALE_SHIFT,
0036     .yscale_sel_mask = AUX_YSCALE_MASK,
0037     .yscale_sel_shift = AUX_YSCALE_SHIFT,
0038     .enable_bit = AUX_SYNT_ENB,
0039 };
0040
0041 static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate,
0042         int index)
0043 {
0044     struct clk_aux *aux = to_clk_aux(hw);
0045     struct aux_rate_tbl *rtbl = aux->rtbl;
0046     u8 eq = rtbl[index].eq ? 1 : 2;
0047
0048     return (((prate / 10000) * rtbl[index].xscale) /
0049             (rtbl[index].yscale * eq)) * 10000;
0050 }
0051
0052 static long clk_aux_round_rate(struct clk_hw *hw, unsigned long drate,
0053         unsigned long *prate)
0054 {
0055     struct clk_aux *aux = to_clk_aux(hw);
0056     int unused;
0057
0058     return clk_round_rate_index(hw, drate, *prate, aux_calc_rate,
0059             aux->rtbl_cnt, &unused);
0060 }
0061
0062 static unsigned long clk_aux_recalc_rate(struct clk_hw *hw,
0063         unsigned long parent_rate)
0064 {
0065     struct clk_aux *aux = to_clk_aux(hw);
0066     unsigned int num = 1, den = 1, val, eqn;
0067     unsigned long flags = 0;
0068
0069     if (aux->lock)
0070         spin_lock_irqsave(aux->lock, flags);
0071
0072     val = readl_relaxed(aux->reg);
0073
0074     if (aux->lock)
0075         spin_unlock_irqrestore(aux->lock, flags);
0076
0077     eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask;
0078     if (eqn == aux->masks->eq1_mask)
0079         den = 2;
0080
0081     /* calculate numerator */
0082     num = (val >> aux->masks->xscale_sel_shift) &
0083         aux->masks->xscale_sel_mask;
0084
0085     /* calculate denominator */
0086     den *= (val >> aux->masks->yscale_sel_shift) &
0087         aux->masks->yscale_sel_mask;
0088
0089     if (!den)
0090         return 0;
0091
0092     return (((parent_rate / 10000) * num) / den) * 10000;
0093 }
0094
0095 /* Configures new clock rate of aux */
0096 static int clk_aux_set_rate(struct clk_hw *hw, unsigned long drate,
0097                 unsigned long prate)
0098 {
0099     struct clk_aux *aux = to_clk_aux(hw);
0100     struct aux_rate_tbl *rtbl = aux->rtbl;
0101     unsigned long val, flags = 0;
0102     int i;
0103
0104     clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt,
0105             &i);
0106
0107     if (aux->lock)
0108         spin_lock_irqsave(aux->lock, flags);
0109
0110     val = readl_relaxed(aux->reg) &
0111         ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift);
0112     val |= (rtbl[i].eq & aux->masks->eq_sel_mask) <<
0113         aux->masks->eq_sel_shift;
0114     val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift);
0115     val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) <<
0116         aux->masks->xscale_sel_shift;
0117     val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift);
0118     val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) <<
0119         aux->masks->yscale_sel_shift;
0120     writel_relaxed(val, aux->reg);
0121
0122     if (aux->lock)
0123         spin_unlock_irqrestore(aux->lock, flags);
0124
0125     return 0;
0126 }
0127
0128 static const struct clk_ops clk_aux_ops = {
0129     .recalc_rate = clk_aux_recalc_rate,
0130     .round_rate = clk_aux_round_rate,
0131     .set_rate = clk_aux_set_rate,
0132 };
0133
0134 struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
0135         const char *parent_name, unsigned long flags, void __iomem *reg,
0136             const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
0137         u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk)
0138 {
0139     struct clk_aux *aux;
0140     struct clk_init_data init;
0141     struct clk *clk;
0142
0143     if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
0144         pr_err("Invalid arguments passed");
0145         return ERR_PTR(-EINVAL);
0146     }
0147
0148     aux = kzalloc(sizeof(*aux), GFP_KERNEL);
0149     if (!aux)
0150         return ERR_PTR(-ENOMEM);
0151
0152     /* struct clk_aux assignments */
0153     if (!masks)
0154         aux->masks = &default_aux_masks;
0155     else
0156         aux->masks = masks;
0157
0158     aux->reg = reg;
0159     aux->rtbl = rtbl;
0160     aux->rtbl_cnt = rtbl_cnt;
0161     aux->lock = lock;
0162     aux->hw.init = &init;
0163
0164     init.name = aux_name;
0165     init.ops = &clk_aux_ops;
0166     init.flags = flags;
0167     init.parent_names = &parent_name;
0168     init.num_parents = 1;
0169
0170     clk = clk_register(NULL, &aux->hw);
0171     if (IS_ERR_OR_NULL(clk))
0172         goto free_aux;
0173
0174     if (gate_name) {
0175         struct clk *tgate_clk;
0176
0177         tgate_clk = clk_register_gate(NULL, gate_name, aux_name,
0178                 CLK_SET_RATE_PARENT, reg,
0179                 aux->masks->enable_bit, 0, lock);
0180         if (IS_ERR_OR_NULL(tgate_clk))
0181             goto free_aux;
0182
0183         if (gate_clk)
0184             *gate_clk = tgate_clk;
0185     }
0186
0187     return clk;
0188
0189 free_aux:
0190     kfree(aux);
0191     pr_err("clk register failed\n");
0192
0193     return NULL;
0194 }