clk/socfpga/stratix10-clk.h

0001 /* SPDX-License-Identifier:    GPL-2.0 */
0002 /*
0003  * Copyright (C) 2017, Intel Corporation
0004  */
0005
0006 #ifndef __STRATIX10_CLK_H
0007 #define __STRATIX10_CLK_H
0008
0009 struct stratix10_clock_data {
0010     struct clk_hw_onecell_data  clk_data;
0011     void __iomem        *base;
0012 };
0013
0014 struct stratix10_pll_clock {
0015     unsigned int        id;
0016     const char      *name;
0017     const struct clk_parent_data    *parent_data;
0018     u8          num_parents;
0019     unsigned long       flags;
0020     unsigned long       offset;
0021 };
0022
0023 struct stratix10_perip_c_clock {
0024     unsigned int        id;
0025     const char      *name;
0026     const char      *parent_name;
0027     const struct clk_parent_data    *parent_data;
0028     u8          num_parents;
0029     unsigned long       flags;
0030     unsigned long       offset;
0031 };
0032
0033 struct n5x_perip_c_clock {
0034     unsigned int        id;
0035     const char      *name;
0036     const char      *parent_name;
0037     const char      *const *parent_names;
0038     u8          num_parents;
0039     unsigned long       flags;
0040     unsigned long       offset;
0041     unsigned long       shift;
0042 };
0043
0044 struct stratix10_perip_cnt_clock {
0045     unsigned int        id;
0046     const char      *name;
0047     const char      *parent_name;
0048     const struct clk_parent_data    *parent_data;
0049     u8          num_parents;
0050     unsigned long       flags;
0051     unsigned long       offset;
0052     u8          fixed_divider;
0053     unsigned long       bypass_reg;
0054     unsigned long       bypass_shift;
0055 };
0056
0057 struct stratix10_gate_clock {
0058     unsigned int        id;
0059     const char      *name;
0060     const char      *parent_name;
0061     const struct clk_parent_data    *parent_data;
0062     u8          num_parents;
0063     unsigned long       flags;
0064     unsigned long       gate_reg;
0065     u8          gate_idx;
0066     unsigned long       div_reg;
0067     u8          div_offset;
0068     u8          div_width;
0069     unsigned long       bypass_reg;
0070     u8          bypass_shift;
0071     u8          fixed_div;
0072 };
0073
0074 struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
0075                  void __iomem *reg);
0076 struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
0077                 void __iomem *reg);
0078 struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
0079                  void __iomem *reg);
0080 struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
0081                 void __iomem *reg);
0082 struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
0083                 void __iomem *reg);
0084 struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
0085                     void __iomem *reg);
0086 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks,
0087                   void __iomem *reg);
0088 struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks,
0089                   void __iomem *reg);
0090 #endif  /* __STRATIX10_CLK_H */