clk/socfpga/clk.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
0004  *
0005  * based on drivers/clk/tegra/clk.h
0006  */
0007
0008 #ifndef __SOCFPGA_CLK_H
0009 #define __SOCFPGA_CLK_H
0010
0011 #include <linux/clk-provider.h>
0012
0013 /* Clock Manager offsets */
0014 #define CLKMGR_CTRL     0x0
0015 #define CLKMGR_BYPASS       0x4
0016 #define CLKMGR_DBCTRL       0x10
0017 #define CLKMGR_L4SRC        0x70
0018 #define CLKMGR_PERPLL_SRC   0xAC
0019
0020 #define SOCFPGA_MAX_PARENTS     5
0021
0022 #define streq(a, b) (strcmp((a), (b)) == 0)
0023 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
0024     ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
0025
0026 #define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \
0027     ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
0028
0029 extern void __iomem *clk_mgr_base_addr;
0030 extern void __iomem *clk_mgr_a10_base_addr;
0031
0032 void __init socfpga_pll_init(struct device_node *node);
0033 void __init socfpga_periph_init(struct device_node *node);
0034 void __init socfpga_gate_init(struct device_node *node);
0035 void socfpga_a10_pll_init(struct device_node *node);
0036 void socfpga_a10_periph_init(struct device_node *node);
0037 void socfpga_a10_gate_init(struct device_node *node);
0038
0039 struct socfpga_pll {
0040     struct clk_gate hw;
0041 };
0042
0043 struct socfpga_gate_clk {
0044     struct clk_gate hw;
0045     char *parent_name;
0046     u32 fixed_div;
0047     void __iomem *div_reg;
0048     void __iomem *bypass_reg;
0049     struct regmap *sys_mgr_base_addr;
0050     u32 width;  /* only valid if div_reg != 0 */
0051     u32 shift;  /* only valid if div_reg != 0 */
0052     u32 bypass_shift;      /* only valid if bypass_reg != 0 */
0053     u32 clk_phase[2];
0054 };
0055
0056 struct socfpga_periph_clk {
0057     struct clk_gate hw;
0058     char *parent_name;
0059     u32 fixed_div;
0060     void __iomem *div_reg;
0061     void __iomem *bypass_reg;
0062     u32 width;      /* only valid if div_reg != 0 */
0063     u32 shift;      /* only valid if div_reg != 0 */
0064     u32 bypass_shift;      /* only valid if bypass_reg != 0 */
0065 };
0066
0067 #endif /* SOCFPGA_CLK_H */