clk/socfpga/clk-s10.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2017, Intel Corporation
0004  */
0005 #include <linux/slab.h>
0006 #include <linux/clk-provider.h>
0007 #include <linux/of_device.h>
0008 #include <linux/of_address.h>
0009 #include <linux/platform_device.h>
0010
0011 #include <dt-bindings/clock/stratix10-clock.h>
0012
0013 #include "stratix10-clk.h"
0014
0015 static const struct clk_parent_data pll_mux[] = {
0016     { .fw_name = "osc1",
0017       .name = "osc1" },
0018     { .fw_name = "cb-intosc-hs-div2-clk",
0019       .name = "cb-intosc-hs-div2-clk" },
0020     { .fw_name = "f2s-free-clk",
0021       .name = "f2s-free-clk" },
0022 };
0023
0024 static const struct clk_parent_data cntr_mux[] = {
0025     { .fw_name =  "main_pll",
0026       .name = "main_pll", },
0027     { .fw_name = "periph_pll",
0028       .name = "periph_pll", },
0029     { .fw_name = "osc1",
0030       .name = "osc1", },
0031     { .fw_name = "cb-intosc-hs-div2-clk",
0032       .name = "cb-intosc-hs-div2-clk", },
0033     { .fw_name = "f2s-free-clk",
0034       .name = "f2s-free-clk", },
0035 };
0036
0037 static const struct clk_parent_data boot_mux[] = {
0038     { .fw_name = "osc1",
0039       .name = "osc1" },
0040     { .fw_name = "cb-intosc-hs-div2-clk",
0041       .name = "cb-intosc-hs-div2-clk" },
0042 };
0043
0044 static const struct clk_parent_data noc_free_mux[] = {
0045     { .fw_name = "main_noc_base_clk",
0046       .name = "main_noc_base_clk", },
0047     { .fw_name = "peri_noc_base_clk",
0048       .name = "peri_noc_base_clk", },
0049     { .fw_name = "osc1",
0050       .name = "osc1", },
0051     { .fw_name = "cb-intosc-hs-div2-clk",
0052       .name = "cb-intosc-hs-div2-clk", },
0053     { .fw_name = "f2s-free-clk",
0054       .name = "f2s-free-clk", },
0055 };
0056
0057 static const struct clk_parent_data emaca_free_mux[] = {
0058     { .fw_name = "peri_emaca_clk",
0059       .name = "peri_emaca_clk", },
0060     { .fw_name = "boot_clk",
0061       .name = "boot_clk", },
0062 };
0063
0064 static const struct clk_parent_data emacb_free_mux[] = {
0065     { .fw_name = "peri_emacb_clk",
0066       .name = "peri_emacb_clk", },
0067     { .fw_name = "boot_clk",
0068       .name = "boot_clk", },
0069 };
0070
0071 static const struct clk_parent_data emac_ptp_free_mux[] = {
0072     { .fw_name = "peri_emac_ptp_clk",
0073       .name = "peri_emac_ptp_clk", },
0074     { .fw_name = "boot_clk",
0075       .name = "boot_clk", },
0076 };
0077
0078 static const struct clk_parent_data gpio_db_free_mux[] = {
0079     { .fw_name = "peri_gpio_db_clk",
0080       .name = "peri_gpio_db_clk", },
0081     { .fw_name = "boot_clk",
0082       .name = "boot_clk", },
0083 };
0084
0085 static const struct clk_parent_data sdmmc_free_mux[] = {
0086     { .fw_name = "main_sdmmc_clk",
0087       .name = "main_sdmmc_clk", },
0088     { .fw_name = "boot_clk",
0089       .name = "boot_clk", },
0090 };
0091
0092 static const struct clk_parent_data s2f_usr1_free_mux[] = {
0093     { .fw_name = "peri_s2f_usr1_clk",
0094       .name = "peri_s2f_usr1_clk", },
0095     { .fw_name = "boot_clk",
0096       .name = "boot_clk", },
0097 };
0098
0099 static const struct clk_parent_data psi_ref_free_mux[] = {
0100     { .fw_name = "peri_psi_ref_clk",
0101       .name = "peri_psi_ref_clk", },
0102     { .fw_name = "boot_clk",
0103       .name = "boot_clk", },
0104 };
0105
0106 static const struct clk_parent_data mpu_mux[] = {
0107     { .fw_name = "mpu_free_clk",
0108       .name = "mpu_free_clk", },
0109     { .fw_name = "boot_clk",
0110       .name = "boot_clk", },
0111 };
0112
0113 static const struct clk_parent_data s2f_usr0_mux[] = {
0114     { .fw_name = "f2s-free-clk",
0115       .name = "f2s-free-clk", },
0116     { .fw_name = "boot_clk",
0117       .name = "boot_clk", },
0118 };
0119
0120 static const struct clk_parent_data emac_mux[] = {
0121     { .fw_name = "emaca_free_clk",
0122       .name = "emaca_free_clk", },
0123     { .fw_name = "emacb_free_clk",
0124       .name = "emacb_free_clk", },
0125 };
0126
0127 static const struct clk_parent_data noc_mux[] = {
0128     { .fw_name = "noc_free_clk",
0129       .name = "noc_free_clk", },
0130     { .fw_name = "boot_clk",
0131       .name = "boot_clk", },
0132 };
0133
0134 static const struct clk_parent_data mpu_free_mux[] = {
0135     { .fw_name = "main_mpu_base_clk",
0136       .name = "main_mpu_base_clk", },
0137     { .fw_name = "peri_mpu_base_clk",
0138       .name = "peri_mpu_base_clk", },
0139     { .fw_name = "osc1",
0140       .name = "osc1", },
0141     { .fw_name = "cb-intosc-hs-div2-clk",
0142       .name = "cb-intosc-hs-div2-clk", },
0143     { .fw_name = "f2s-free-clk",
0144       .name = "f2s-free-clk", },
0145 };
0146
0147 static const struct clk_parent_data sdmmc_mux[] = {
0148     { .fw_name = "sdmmc_free_clk",
0149       .name = "sdmmc_free_clk", },
0150     { .fw_name = "boot_clk",
0151       .name = "boot_clk", },
0152 };
0153
0154 static const struct clk_parent_data s2f_user1_mux[] = {
0155     { .fw_name = "s2f_user1_free_clk",
0156       .name = "s2f_user1_free_clk", },
0157     { .fw_name = "boot_clk",
0158       .name = "boot_clk", },
0159 };
0160
0161 static const struct clk_parent_data psi_mux[] = {
0162     { .fw_name = "psi_ref_free_clk",
0163       .name = "psi_ref_free_clk", },
0164     { .fw_name = "boot_clk",
0165       .name = "boot_clk", },
0166 };
0167
0168 static const struct clk_parent_data gpio_db_mux[] = {
0169     { .fw_name = "gpio_db_free_clk",
0170       .name = "gpio_db_free_clk", },
0171     { .fw_name = "boot_clk",
0172       .name = "boot_clk", },
0173 };
0174
0175 static const struct clk_parent_data emac_ptp_mux[] = {
0176     { .fw_name = "emac_ptp_free_clk",
0177       .name = "emac_ptp_free_clk", },
0178     { .fw_name = "boot_clk",
0179       .name = "boot_clk", },
0180 };
0181
0182 /* clocks in AO (always on) controller */
0183 static const struct stratix10_pll_clock s10_pll_clks[] = {
0184     { STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
0185       0x0},
0186     { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
0187       0, 0x74},
0188     { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
0189       0, 0xe4},
0190 };
0191
0192 static const struct stratix10_perip_c_clock s10_main_perip_c_clks[] = {
0193     { STRATIX10_MAIN_MPU_BASE_CLK, "main_mpu_base_clk", "main_pll", NULL, 1, 0, 0x84},
0194     { STRATIX10_MAIN_NOC_BASE_CLK, "main_noc_base_clk", "main_pll", NULL, 1, 0, 0x88},
0195     { STRATIX10_PERI_MPU_BASE_CLK, "peri_mpu_base_clk", "periph_pll", NULL, 1, 0,
0196       0xF4},
0197     { STRATIX10_PERI_NOC_BASE_CLK, "peri_noc_base_clk", "periph_pll", NULL, 1, 0,
0198       0xF8},
0199 };
0200
0201 static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
0202     { STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
0203        0, 0x48, 0, 0, 0},
0204     { STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
0205       0, 0x4C, 0, 0x3C, 1},
0206     { STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0,
0207       0x50, 0, 0, 0},
0208     { STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0,
0209       0x54, 0, 0, 0},
0210     { STRATIX10_MAIN_EMAC_PTP_CLK, "main_emac_ptp_clk", "main_noc_base_clk", NULL, 1, 0,
0211       0x58, 0, 0, 0},
0212     { STRATIX10_MAIN_GPIO_DB_CLK, "main_gpio_db_clk", "main_noc_base_clk", NULL, 1, 0,
0213       0x5C, 0, 0, 0},
0214     { STRATIX10_MAIN_SDMMC_CLK, "main_sdmmc_clk", "main_noc_base_clk", NULL, 1, 0,
0215       0x60, 0, 0, 0},
0216     { STRATIX10_MAIN_S2F_USR0_CLK, "main_s2f_usr0_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
0217       0, 0x64, 0, 0, 0},
0218     { STRATIX10_MAIN_S2F_USR1_CLK, "main_s2f_usr1_clk", "main_noc_base_clk", NULL, 1, 0,
0219       0x68, 0, 0, 0},
0220     { STRATIX10_MAIN_PSI_REF_CLK, "main_psi_ref_clk", "main_noc_base_clk", NULL, 1, 0,
0221       0x6C, 0, 0, 0},
0222     { STRATIX10_PERI_EMACA_CLK, "peri_emaca_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
0223       0, 0xBC, 0, 0, 0},
0224     { STRATIX10_PERI_EMACB_CLK, "peri_emacb_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
0225       0, 0xC0, 0, 0, 0},
0226     { STRATIX10_PERI_EMAC_PTP_CLK, "peri_emac_ptp_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
0227       0, 0xC4, 0, 0, 0},
0228     { STRATIX10_PERI_GPIO_DB_CLK, "peri_gpio_db_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
0229       0, 0xC8, 0, 0, 0},
0230     { STRATIX10_PERI_SDMMC_CLK, "peri_sdmmc_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
0231       0, 0xCC, 0, 0, 0},
0232     { STRATIX10_PERI_S2F_USR0_CLK, "peri_s2f_usr0_clk", "peri_noc_base_clk", NULL, 1, 0,
0233       0xD0, 0, 0, 0},
0234     { STRATIX10_PERI_S2F_USR1_CLK, "peri_s2f_usr1_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
0235       0, 0xD4, 0, 0, 0},
0236     { STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0,
0237       0xD8, 0, 0, 0},
0238     { STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
0239       0, 4, 0x3C, 1},
0240     { STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
0241       0, 0, 2, 0xB0, 0},
0242     { STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
0243       0, 0, 2, 0xB0, 1},
0244     { STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
0245       ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 2, 0xB0, 2},
0246     { STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
0247       ARRAY_SIZE(gpio_db_free_mux), 0, 0, 0, 0xB0, 3},
0248     { STRATIX10_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
0249       ARRAY_SIZE(sdmmc_free_mux), 0, 0, 0, 0xB0, 4},
0250     { STRATIX10_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
0251       ARRAY_SIZE(s2f_usr1_free_mux), 0, 0, 0, 0xB0, 5},
0252     { STRATIX10_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
0253       ARRAY_SIZE(psi_ref_free_mux), 0, 0, 0, 0xB0, 6},
0254 };
0255
0256 static const struct stratix10_gate_clock s10_gate_clks[] = {
0257     { STRATIX10_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x30,
0258       0, 0, 0, 0, 0x3C, 0, 0},
0259     { STRATIX10_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x30,
0260       0, 0, 0, 0, 0, 0, 4},
0261     { STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30,
0262       0, 0, 0, 0, 0, 0, 2},
0263     { STRATIX10_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
0264       1, 0x70, 0, 2, 0x3C, 1, 0},
0265     { STRATIX10_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
0266       2, 0x70, 8, 2, 0x3C, 1, 0},
0267     { STRATIX10_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x30,
0268       3, 0x70, 16, 2, 0x3C, 1, 0},
0269     { STRATIX10_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
0270       4, 0x70, 24, 2, 0x3C, 1, 0},
0271     { STRATIX10_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
0272       4, 0x70, 26, 2, 0x3C, 1, 0},
0273     { STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30,
0274       4, 0x70, 28, 1, 0, 0, 0},
0275     { STRATIX10_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
0276       5, 0, 0, 0, 0x3C, 1, 0},
0277     { STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30,
0278       6, 0, 0, 0, 0, 0, 0},
0279     { STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
0280       0, 0, 0, 0, 0xDC, 26, 0},
0281     { STRATIX10_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
0282       1, 0, 0, 0, 0xDC, 27, 0},
0283     { STRATIX10_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
0284       2, 0, 0, 0, 0xDC, 28, 0},
0285     { STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, ARRAY_SIZE(emac_ptp_mux), 0, 0xA4,
0286       3, 0, 0, 0, 0xB0, 2, 0},
0287     { STRATIX10_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, ARRAY_SIZE(gpio_db_mux), 0, 0xA4,
0288       4, 0xE0, 0, 16, 0xB0, 3, 0},
0289     { STRATIX10_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0xA4,
0290       5, 0, 0, 0, 0xB0, 4, 4},
0291     { STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0xA4,
0292       6, 0, 0, 0, 0xB0, 5, 0},
0293     { STRATIX10_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0xA4,
0294       7, 0, 0, 0, 0xB0, 6, 0},
0295     { STRATIX10_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
0296       8, 0, 0, 0, 0, 0, 0},
0297     { STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
0298       9, 0, 0, 0, 0, 0, 0},
0299     { STRATIX10_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
0300       10, 0, 0, 0, 0, 0, 0},
0301     { STRATIX10_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
0302       10, 0, 0, 0, 0, 0, 4},
0303     { STRATIX10_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
0304       10, 0, 0, 0, 0, 0, 4},
0305 };
0306
0307 static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
0308                     int nums, struct stratix10_clock_data *data)
0309 {
0310     struct clk_hw *hw_clk;
0311     void __iomem *base = data->base;
0312     int i;
0313
0314     for (i = 0; i < nums; i++) {
0315         hw_clk = s10_register_periph(&clks[i], base);
0316         if (IS_ERR(hw_clk)) {
0317             pr_err("%s: failed to register clock %s\n",
0318                    __func__, clks[i].name);
0319             continue;
0320         }
0321         data->clk_data.hws[clks[i].id] = hw_clk;
0322     }
0323     return 0;
0324 }
0325
0326 static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
0327                       int nums, struct stratix10_clock_data *data)
0328 {
0329     struct clk_hw *hw_clk;
0330     void __iomem *base = data->base;
0331     int i;
0332
0333     for (i = 0; i < nums; i++) {
0334         hw_clk = s10_register_cnt_periph(&clks[i], base);
0335         if (IS_ERR(hw_clk)) {
0336             pr_err("%s: failed to register clock %s\n",
0337                    __func__, clks[i].name);
0338             continue;
0339         }
0340         data->clk_data.hws[clks[i].id] = hw_clk;
0341     }
0342
0343     return 0;
0344 }
0345
0346 static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
0347                  int nums, struct stratix10_clock_data *data)
0348 {
0349     struct clk_hw *hw_clk;
0350     void __iomem *base = data->base;
0351     int i;
0352
0353     for (i = 0; i < nums; i++) {
0354         hw_clk = s10_register_gate(&clks[i], base);
0355         if (IS_ERR(hw_clk)) {
0356             pr_err("%s: failed to register clock %s\n",
0357                    __func__, clks[i].name);
0358             continue;
0359         }
0360         data->clk_data.hws[clks[i].id] = hw_clk;
0361     }
0362
0363     return 0;
0364 }
0365
0366 static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
0367                  int nums, struct stratix10_clock_data *data)
0368 {
0369     struct clk_hw *hw_clk;
0370     void __iomem *base = data->base;
0371     int i;
0372
0373     for (i = 0; i < nums; i++) {
0374         hw_clk = s10_register_pll(&clks[i], base);
0375         if (IS_ERR(hw_clk)) {
0376             pr_err("%s: failed to register clock %s\n",
0377                    __func__, clks[i].name);
0378             continue;
0379         }
0380         data->clk_data.hws[clks[i].id] = hw_clk;
0381     }
0382
0383     return 0;
0384 }
0385
0386 static int s10_clkmgr_init(struct platform_device *pdev)
0387 {
0388     struct device_node *np = pdev->dev.of_node;
0389     struct device *dev = &pdev->dev;
0390     struct stratix10_clock_data *clk_data;
0391     void __iomem *base;
0392     int i, num_clks;
0393
0394     base = devm_platform_ioremap_resource(pdev, 0);
0395     if (IS_ERR(base)) {
0396         pr_err("%s: failed to map clock registers\n", __func__);
0397         return PTR_ERR(base);
0398     }
0399
0400     num_clks = STRATIX10_NUM_CLKS;
0401     clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
0402                          num_clks), GFP_KERNEL);
0403     if (!clk_data)
0404         return -ENOMEM;
0405
0406     for (i = 0; i < num_clks; i++)
0407         clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
0408
0409     clk_data->base = base;
0410     clk_data->clk_data.num = num_clks;
0411
0412     s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
0413
0414     s10_clk_register_c_perip(s10_main_perip_c_clks,
0415                  ARRAY_SIZE(s10_main_perip_c_clks), clk_data);
0416
0417     s10_clk_register_cnt_perip(s10_main_perip_cnt_clks,
0418                    ARRAY_SIZE(s10_main_perip_cnt_clks),
0419                    clk_data);
0420
0421     s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks),
0422                   clk_data);
0423
0424     of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
0425     return 0;
0426 }
0427
0428 static int s10_clkmgr_probe(struct platform_device *pdev)
0429 {
0430     return  s10_clkmgr_init(pdev);
0431 }
0432
0433 static const struct of_device_id stratix10_clkmgr_match_table[] = {
0434     { .compatible = "intel,stratix10-clkmgr",
0435       .data = s10_clkmgr_init },
0436     { }
0437 };
0438
0439 static struct platform_driver stratix10_clkmgr_driver = {
0440     .probe      = s10_clkmgr_probe,
0441     .driver     = {
0442         .name   = "stratix10-clkmgr",
0443         .suppress_bind_attrs = true,
0444         .of_match_table = stratix10_clkmgr_match_table,
0445     },
0446 };
0447
0448 static int __init s10_clk_init(void)
0449 {
0450     return platform_driver_register(&stratix10_clkmgr_driver);
0451 }
0452 core_initcall(s10_clk_init);