clk/socfpga/clk-pll.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Copyright 2011-2012 Calxeda, Inc.
0004  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
0005  *
0006  * Based from clk-highbank.c
0007  */
0008 #include <linux/slab.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013
0014 #include "clk.h"
0015
0016 /* Clock bypass bits */
0017 #define MAINPLL_BYPASS      (1<<0)
0018 #define SDRAMPLL_BYPASS     (1<<1)
0019 #define SDRAMPLL_SRC_BYPASS (1<<2)
0020 #define PERPLL_BYPASS       (1<<3)
0021 #define PERPLL_SRC_BYPASS   (1<<4)
0022
0023 #define SOCFPGA_PLL_BG_PWRDWN       0
0024 #define SOCFPGA_PLL_EXT_ENA     1
0025 #define SOCFPGA_PLL_PWR_DOWN        2
0026 #define SOCFPGA_PLL_DIVF_MASK       0x0000FFF8
0027 #define SOCFPGA_PLL_DIVF_SHIFT      3
0028 #define SOCFPGA_PLL_DIVQ_MASK       0x003F0000
0029 #define SOCFPGA_PLL_DIVQ_SHIFT      16
0030
0031 #define CLK_MGR_PLL_CLK_SRC_SHIFT   22
0032 #define CLK_MGR_PLL_CLK_SRC_MASK    0x3
0033
0034 #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
0035
0036 void __iomem *clk_mgr_base_addr;
0037
0038 static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
0039                      unsigned long parent_rate)
0040 {
0041     struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
0042     unsigned long divf, divq, reg;
0043     unsigned long long vco_freq;
0044     unsigned long bypass;
0045
0046     reg = readl(socfpgaclk->hw.reg);
0047     bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
0048     if (bypass & MAINPLL_BYPASS)
0049         return parent_rate;
0050
0051     divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
0052     divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
0053     vco_freq = (unsigned long long)parent_rate * (divf + 1);
0054     do_div(vco_freq, (1 + divq));
0055     return (unsigned long)vco_freq;
0056 }
0057
0058 static u8 clk_pll_get_parent(struct clk_hw *hwclk)
0059 {
0060     u32 pll_src;
0061     struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
0062
0063     pll_src = readl(socfpgaclk->hw.reg);
0064     return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
0065             CLK_MGR_PLL_CLK_SRC_MASK;
0066 }
0067
0068 static const struct clk_ops clk_pll_ops = {
0069     .recalc_rate = clk_pll_recalc_rate,
0070     .get_parent = clk_pll_get_parent,
0071 };
0072
0073 static __init struct clk_hw *__socfpga_pll_init(struct device_node *node,
0074     const struct clk_ops *ops)
0075 {
0076     u32 reg;
0077     struct clk_hw *hw_clk;
0078     struct socfpga_pll *pll_clk;
0079     const char *clk_name = node->name;
0080     const char *parent_name[SOCFPGA_MAX_PARENTS];
0081     struct clk_init_data init;
0082     struct device_node *clkmgr_np;
0083     int err;
0084
0085     of_property_read_u32(node, "reg", &reg);
0086
0087     pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
0088     if (WARN_ON(!pll_clk))
0089         return NULL;
0090
0091     clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
0092     clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
0093     of_node_put(clkmgr_np);
0094     BUG_ON(!clk_mgr_base_addr);
0095     pll_clk->hw.reg = clk_mgr_base_addr + reg;
0096
0097     of_property_read_string(node, "clock-output-names", &clk_name);
0098
0099     init.name = clk_name;
0100     init.ops = ops;
0101     init.flags = 0;
0102
0103     init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
0104     init.parent_names = parent_name;
0105     pll_clk->hw.hw.init = &init;
0106
0107     pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
0108
0109     hw_clk = &pll_clk->hw.hw;
0110
0111     err = clk_hw_register(NULL, hw_clk);
0112     if (err) {
0113         kfree(pll_clk);
0114         return ERR_PTR(err);
0115     }
0116     of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
0117     return hw_clk;
0118 }
0119
0120 void __init socfpga_pll_init(struct device_node *node)
0121 {
0122     __socfpga_pll_init(node, &clk_pll_ops);
0123 }