clk/socfpga/clk-periph.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Copyright 2011-2012 Calxeda, Inc.
0004  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
0005  *
0006  * Based from clk-highbank.c
0007  */
0008 #include <linux/slab.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012
0013 #include "clk.h"
0014
0015 #define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
0016
0017 static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
0018                          unsigned long parent_rate)
0019 {
0020     struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
0021     u32 div, val;
0022
0023     if (socfpgaclk->fixed_div) {
0024         div = socfpgaclk->fixed_div;
0025     } else {
0026         if (socfpgaclk->div_reg) {
0027             val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
0028             val &= GENMASK(socfpgaclk->width - 1, 0);
0029             parent_rate /= (val + 1);
0030         }
0031         div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
0032     }
0033
0034     return parent_rate / div;
0035 }
0036
0037 static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
0038 {
0039     u32 clk_src;
0040
0041     clk_src = readl(clk_mgr_base_addr + CLKMGR_DBCTRL);
0042     return clk_src & 0x1;
0043 }
0044
0045 static const struct clk_ops periclk_ops = {
0046     .recalc_rate = clk_periclk_recalc_rate,
0047     .get_parent = clk_periclk_get_parent,
0048 };
0049
0050 static __init void __socfpga_periph_init(struct device_node *node,
0051     const struct clk_ops *ops)
0052 {
0053     u32 reg;
0054     struct clk_hw *hw_clk;
0055     struct socfpga_periph_clk *periph_clk;
0056     const char *clk_name = node->name;
0057     const char *parent_name[SOCFPGA_MAX_PARENTS];
0058     struct clk_init_data init;
0059     int rc;
0060     u32 fixed_div;
0061     u32 div_reg[3];
0062
0063     of_property_read_u32(node, "reg", &reg);
0064
0065     periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
0066     if (WARN_ON(!periph_clk))
0067         return;
0068
0069     periph_clk->hw.reg = clk_mgr_base_addr + reg;
0070
0071     rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
0072     if (!rc) {
0073         periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];
0074         periph_clk->shift = div_reg[1];
0075         periph_clk->width = div_reg[2];
0076     } else {
0077         periph_clk->div_reg = NULL;
0078     }
0079
0080     rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
0081     if (rc)
0082         periph_clk->fixed_div = 0;
0083     else
0084         periph_clk->fixed_div = fixed_div;
0085
0086     of_property_read_string(node, "clock-output-names", &clk_name);
0087
0088     init.name = clk_name;
0089     init.ops = ops;
0090     init.flags = 0;
0091
0092     init.num_parents = of_clk_parent_fill(node, parent_name,
0093                           SOCFPGA_MAX_PARENTS);
0094     init.parent_names = parent_name;
0095
0096     periph_clk->hw.hw.init = &init;
0097     hw_clk = &periph_clk->hw.hw;
0098
0099     if (clk_hw_register(NULL, hw_clk)) {
0100         kfree(periph_clk);
0101         return;
0102     }
0103     rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
0104 }
0105
0106 void __init socfpga_periph_init(struct device_node *node)
0107 {
0108     __socfpga_periph_init(node, &periclk_ops);
0109 }