clk/socfpga/clk-periph-a10.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2015 Altera Corporation. All rights reserved
0004  */
0005 #include <linux/slab.h>
0006 #include <linux/clk-provider.h>
0007 #include <linux/io.h>
0008 #include <linux/of.h>
0009
0010 #include "clk.h"
0011
0012 #define CLK_MGR_FREE_SHIFT      16
0013 #define CLK_MGR_FREE_MASK       0x7
0014
0015 #define SOCFPGA_MPU_FREE_CLK        "mpu_free_clk"
0016 #define SOCFPGA_NOC_FREE_CLK        "noc_free_clk"
0017 #define SOCFPGA_SDMMC_FREE_CLK      "sdmmc_free_clk"
0018 #define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
0019
0020 static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
0021                          unsigned long parent_rate)
0022 {
0023     struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
0024     u32 div;
0025
0026     if (socfpgaclk->fixed_div) {
0027         div = socfpgaclk->fixed_div;
0028     } else if (socfpgaclk->div_reg) {
0029         div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
0030         div &= GENMASK(socfpgaclk->width - 1, 0);
0031         div += 1;
0032     } else {
0033         div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
0034     }
0035
0036     return parent_rate / div;
0037 }
0038
0039 static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
0040 {
0041     struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
0042     u32 clk_src;
0043     const char *name = clk_hw_get_name(hwclk);
0044
0045     clk_src = readl(socfpgaclk->hw.reg);
0046     if (streq(name, SOCFPGA_MPU_FREE_CLK) ||
0047         streq(name, SOCFPGA_NOC_FREE_CLK) ||
0048         streq(name, SOCFPGA_SDMMC_FREE_CLK))
0049         return (clk_src >> CLK_MGR_FREE_SHIFT) &
0050             CLK_MGR_FREE_MASK;
0051     else
0052         return 0;
0053 }
0054
0055 static const struct clk_ops periclk_ops = {
0056     .recalc_rate = clk_periclk_recalc_rate,
0057     .get_parent = clk_periclk_get_parent,
0058 };
0059
0060 static __init void __socfpga_periph_init(struct device_node *node,
0061     const struct clk_ops *ops)
0062 {
0063     u32 reg;
0064     struct clk_hw *hw_clk;
0065     struct socfpga_periph_clk *periph_clk;
0066     const char *clk_name = node->name;
0067     const char *parent_name[SOCFPGA_MAX_PARENTS];
0068     struct clk_init_data init;
0069     int rc;
0070     u32 fixed_div;
0071     u32 div_reg[3];
0072
0073     of_property_read_u32(node, "reg", &reg);
0074
0075     periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
0076     if (WARN_ON(!periph_clk))
0077         return;
0078
0079     periph_clk->hw.reg = clk_mgr_a10_base_addr + reg;
0080
0081     rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
0082     if (!rc) {
0083         periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];
0084         periph_clk->shift = div_reg[1];
0085         periph_clk->width = div_reg[2];
0086     } else {
0087         periph_clk->div_reg = NULL;
0088     }
0089
0090     rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
0091     if (rc)
0092         periph_clk->fixed_div = 0;
0093     else
0094         periph_clk->fixed_div = fixed_div;
0095
0096     of_property_read_string(node, "clock-output-names", &clk_name);
0097
0098     init.name = clk_name;
0099     init.ops = ops;
0100     init.flags = 0;
0101
0102     init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
0103     init.parent_names = parent_name;
0104
0105     periph_clk->hw.hw.init = &init;
0106
0107     hw_clk = &periph_clk->hw.hw;
0108
0109     if (clk_hw_register(NULL, hw_clk)) {
0110         kfree(periph_clk);
0111         return;
0112     }
0113     rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
0114     if (rc < 0) {
0115         pr_err("Could not register clock provider for node:%s\n",
0116                clk_name);
0117         goto err_clk;
0118     }
0119
0120     return;
0121
0122 err_clk:
0123     clk_hw_unregister(hw_clk);
0124 }
0125
0126 void __init socfpga_a10_periph_init(struct device_node *node)
0127 {
0128     __socfpga_periph_init(node, &periclk_ops);
0129 }