clk/socfpga/clk-gate.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Copyright 2011-2012 Calxeda, Inc.
0004  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
0005  *
0006  * Based from clk-highbank.c
0007  */
0008 #include <linux/slab.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/io.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/of.h>
0013 #include <linux/regmap.h>
0014
0015 #include "clk.h"
0016
0017 #define SOCFPGA_L4_MP_CLK       "l4_mp_clk"
0018 #define SOCFPGA_L4_SP_CLK       "l4_sp_clk"
0019 #define SOCFPGA_NAND_CLK        "nand_clk"
0020 #define SOCFPGA_NAND_X_CLK      "nand_x_clk"
0021 #define SOCFPGA_MMC_CLK         "sdmmc_clk"
0022 #define SOCFPGA_GPIO_DB_CLK_OFFSET  0xA8
0023
0024 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
0025
0026 /* SDMMC Group for System Manager defines */
0027 #define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
0028
0029 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
0030 {
0031     u32 l4_src;
0032     u32 perpll_src;
0033     const char *name = clk_hw_get_name(hwclk);
0034
0035     if (streq(name, SOCFPGA_L4_MP_CLK)) {
0036         l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
0037         return l4_src & 0x1;
0038     }
0039     if (streq(name, SOCFPGA_L4_SP_CLK)) {
0040         l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
0041         return !!(l4_src & 2);
0042     }
0043
0044     perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
0045     if (streq(name, SOCFPGA_MMC_CLK))
0046         return perpll_src & 0x3;
0047     if (streq(name, SOCFPGA_NAND_CLK) ||
0048         streq(name, SOCFPGA_NAND_X_CLK))
0049         return (perpll_src >> 2) & 3;
0050
0051     /* QSPI clock */
0052     return (perpll_src >> 4) & 3;
0053
0054 }
0055
0056 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
0057 {
0058     u32 src_reg;
0059     const char *name = clk_hw_get_name(hwclk);
0060
0061     if (streq(name, SOCFPGA_L4_MP_CLK)) {
0062         src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
0063         src_reg &= ~0x1;
0064         src_reg |= parent;
0065         writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
0066     } else if (streq(name, SOCFPGA_L4_SP_CLK)) {
0067         src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
0068         src_reg &= ~0x2;
0069         src_reg |= (parent << 1);
0070         writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
0071     } else {
0072         src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
0073         if (streq(name, SOCFPGA_MMC_CLK)) {
0074             src_reg &= ~0x3;
0075             src_reg |= parent;
0076         } else if (streq(name, SOCFPGA_NAND_CLK) ||
0077             streq(name, SOCFPGA_NAND_X_CLK)) {
0078             src_reg &= ~0xC;
0079             src_reg |= (parent << 2);
0080         } else {/* QSPI clock */
0081             src_reg &= ~0x30;
0082             src_reg |= (parent << 4);
0083         }
0084         writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
0085     }
0086
0087     return 0;
0088 }
0089
0090 static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
0091     unsigned long parent_rate)
0092 {
0093     struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
0094     u32 div = 1, val;
0095
0096     if (socfpgaclk->fixed_div)
0097         div = socfpgaclk->fixed_div;
0098     else if (socfpgaclk->div_reg) {
0099         val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
0100         val &= GENMASK(socfpgaclk->width - 1, 0);
0101         /* Check for GPIO_DB_CLK by its offset */
0102         if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
0103             div = val + 1;
0104         else
0105             div = (1 << val);
0106     }
0107
0108     return parent_rate / div;
0109 }
0110
0111 static int socfpga_clk_prepare(struct clk_hw *hwclk)
0112 {
0113     struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
0114     struct regmap *sys_mgr_base_addr;
0115     int i;
0116     u32 hs_timing;
0117     u32 clk_phase[2];
0118
0119     if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
0120         sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
0121         if (IS_ERR(sys_mgr_base_addr)) {
0122             pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
0123             return -EINVAL;
0124         }
0125
0126         for (i = 0; i < 2; i++) {
0127             switch (socfpgaclk->clk_phase[i]) {
0128             case 0:
0129                 clk_phase[i] = 0;
0130                 break;
0131             case 45:
0132                 clk_phase[i] = 1;
0133                 break;
0134             case 90:
0135                 clk_phase[i] = 2;
0136                 break;
0137             case 135:
0138                 clk_phase[i] = 3;
0139                 break;
0140             case 180:
0141                 clk_phase[i] = 4;
0142                 break;
0143             case 225:
0144                 clk_phase[i] = 5;
0145                 break;
0146             case 270:
0147                 clk_phase[i] = 6;
0148                 break;
0149             case 315:
0150                 clk_phase[i] = 7;
0151                 break;
0152             default:
0153                 clk_phase[i] = 0;
0154                 break;
0155             }
0156         }
0157         hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
0158         regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
0159             hs_timing);
0160     }
0161     return 0;
0162 }
0163
0164 static struct clk_ops gateclk_ops = {
0165     .prepare = socfpga_clk_prepare,
0166     .recalc_rate = socfpga_clk_recalc_rate,
0167     .get_parent = socfpga_clk_get_parent,
0168     .set_parent = socfpga_clk_set_parent,
0169 };
0170
0171 void __init socfpga_gate_init(struct device_node *node)
0172 {
0173     u32 clk_gate[2];
0174     u32 div_reg[3];
0175     u32 clk_phase[2];
0176     u32 fixed_div;
0177     struct clk_hw *hw_clk;
0178     struct socfpga_gate_clk *socfpga_clk;
0179     const char *clk_name = node->name;
0180     const char *parent_name[SOCFPGA_MAX_PARENTS];
0181     struct clk_init_data init;
0182     struct clk_ops *ops;
0183     int rc;
0184     int err;
0185
0186     socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
0187     if (WARN_ON(!socfpga_clk))
0188         return;
0189
0190     ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
0191     if (WARN_ON(!ops))
0192         return;
0193
0194     rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
0195     if (rc)
0196         clk_gate[0] = 0;
0197
0198     if (clk_gate[0]) {
0199         socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
0200         socfpga_clk->hw.bit_idx = clk_gate[1];
0201
0202         ops->enable = clk_gate_ops.enable;
0203         ops->disable = clk_gate_ops.disable;
0204     }
0205
0206     rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
0207     if (rc)
0208         socfpga_clk->fixed_div = 0;
0209     else
0210         socfpga_clk->fixed_div = fixed_div;
0211
0212     rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
0213     if (!rc) {
0214         socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
0215         socfpga_clk->shift = div_reg[1];
0216         socfpga_clk->width = div_reg[2];
0217     } else {
0218         socfpga_clk->div_reg = NULL;
0219     }
0220
0221     rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
0222     if (!rc) {
0223         socfpga_clk->clk_phase[0] = clk_phase[0];
0224         socfpga_clk->clk_phase[1] = clk_phase[1];
0225     }
0226
0227     of_property_read_string(node, "clock-output-names", &clk_name);
0228
0229     init.name = clk_name;
0230     init.ops = ops;
0231     init.flags = 0;
0232
0233     init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
0234     if (init.num_parents < 2) {
0235         ops->get_parent = NULL;
0236         ops->set_parent = NULL;
0237     }
0238
0239     init.parent_names = parent_name;
0240     socfpga_clk->hw.hw.init = &init;
0241
0242     hw_clk = &socfpga_clk->hw.hw;
0243
0244     err = clk_hw_register(NULL, hw_clk);
0245     if (err) {
0246         kfree(socfpga_clk);
0247         return;
0248     }
0249     rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
0250     if (WARN_ON(rc))
0251         return;
0252 }