clk/socfpga/clk-gate-s10.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2017, Intel Corporation
0004  */
0005 #include <linux/clk-provider.h>
0006 #include <linux/io.h>
0007 #include <linux/slab.h>
0008 #include "stratix10-clk.h"
0009 #include "clk.h"
0010
0011 #define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk"
0012 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
0013
0014 #define SOCFPGA_EMAC0_CLK       "emac0_clk"
0015 #define SOCFPGA_EMAC1_CLK       "emac1_clk"
0016 #define SOCFPGA_EMAC2_CLK       "emac2_clk"
0017 #define AGILEX_BYPASS_OFFSET        0xC
0018 #define STRATIX10_BYPASS_OFFSET     0x2C
0019 #define BOOTCLK_BYPASS          2
0020
0021 static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
0022                           unsigned long parent_rate)
0023 {
0024     struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
0025     u32 div = 1, val;
0026
0027     if (socfpgaclk->fixed_div) {
0028         div = socfpgaclk->fixed_div;
0029     } else if (socfpgaclk->div_reg) {
0030         val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
0031         val &= GENMASK(socfpgaclk->width - 1, 0);
0032         div = (1 << val);
0033     }
0034     return parent_rate / div;
0035 }
0036
0037 static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
0038                           unsigned long parent_rate)
0039 {
0040     struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
0041     u32 div, val;
0042
0043     val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
0044     val &= GENMASK(socfpgaclk->width - 1, 0);
0045     div = (1 << val);
0046     div = div ? 4 : 1;
0047
0048     return parent_rate / div;
0049 }
0050
0051 static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
0052 {
0053     struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
0054     u32 mask, second_bypass;
0055     u8 parent = 0;
0056     const char *name = clk_hw_get_name(hwclk);
0057
0058     if (socfpgaclk->bypass_reg) {
0059         mask = (0x1 << socfpgaclk->bypass_shift);
0060         parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
0061               socfpgaclk->bypass_shift);
0062     }
0063
0064     if (streq(name, SOCFPGA_EMAC0_CLK) ||
0065         streq(name, SOCFPGA_EMAC1_CLK) ||
0066         streq(name, SOCFPGA_EMAC2_CLK)) {
0067         second_bypass = readl(socfpgaclk->bypass_reg -
0068                       STRATIX10_BYPASS_OFFSET);
0069         /* EMACA bypass to bootclk @0xB0 offset */
0070         if (second_bypass & 0x1)
0071             if (parent == 0) /* only applicable if parent is maca */
0072                 parent = BOOTCLK_BYPASS;
0073
0074         if (second_bypass & 0x2)
0075             if (parent == 1) /* only applicable if parent is macb */
0076                 parent = BOOTCLK_BYPASS;
0077     }
0078     return parent;
0079 }
0080
0081 static u8 socfpga_agilex_gate_get_parent(struct clk_hw *hwclk)
0082 {
0083     struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
0084     u32 mask, second_bypass;
0085     u8 parent = 0;
0086     const char *name = clk_hw_get_name(hwclk);
0087
0088     if (socfpgaclk->bypass_reg) {
0089         mask = (0x1 << socfpgaclk->bypass_shift);
0090         parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
0091               socfpgaclk->bypass_shift);
0092     }
0093
0094     if (streq(name, SOCFPGA_EMAC0_CLK) ||
0095         streq(name, SOCFPGA_EMAC1_CLK) ||
0096         streq(name, SOCFPGA_EMAC2_CLK)) {
0097         second_bypass = readl(socfpgaclk->bypass_reg -
0098                       AGILEX_BYPASS_OFFSET);
0099         /* EMACA bypass to bootclk @0x88 offset */
0100         if (second_bypass & 0x1)
0101             if (parent == 0) /* only applicable if parent is maca */
0102                 parent = BOOTCLK_BYPASS;
0103
0104         if (second_bypass & 0x2)
0105             if (parent == 1) /* only applicable if parent is macb */
0106                 parent = BOOTCLK_BYPASS;
0107     }
0108
0109     return parent;
0110 }
0111
0112 static struct clk_ops gateclk_ops = {
0113     .recalc_rate = socfpga_gate_clk_recalc_rate,
0114     .get_parent = socfpga_gate_get_parent,
0115 };
0116
0117 static const struct clk_ops agilex_gateclk_ops = {
0118     .recalc_rate = socfpga_gate_clk_recalc_rate,
0119     .get_parent = socfpga_agilex_gate_get_parent,
0120 };
0121
0122 static const struct clk_ops dbgclk_ops = {
0123     .recalc_rate = socfpga_dbg_clk_recalc_rate,
0124     .get_parent = socfpga_gate_get_parent,
0125 };
0126
0127 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
0128 {
0129     struct clk_hw *hw_clk;
0130     struct socfpga_gate_clk *socfpga_clk;
0131     struct clk_init_data init;
0132     const char *parent_name = clks->parent_name;
0133     int ret;
0134
0135     socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
0136     if (!socfpga_clk)
0137         return NULL;
0138
0139     socfpga_clk->hw.reg = regbase + clks->gate_reg;
0140     socfpga_clk->hw.bit_idx = clks->gate_idx;
0141
0142     gateclk_ops.enable = clk_gate_ops.enable;
0143     gateclk_ops.disable = clk_gate_ops.disable;
0144
0145     socfpga_clk->fixed_div = clks->fixed_div;
0146
0147     if (clks->div_reg)
0148         socfpga_clk->div_reg = regbase + clks->div_reg;
0149     else
0150         socfpga_clk->div_reg = NULL;
0151
0152     socfpga_clk->width = clks->div_width;
0153     socfpga_clk->shift = clks->div_offset;
0154
0155     if (clks->bypass_reg)
0156         socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
0157     else
0158         socfpga_clk->bypass_reg = NULL;
0159     socfpga_clk->bypass_shift = clks->bypass_shift;
0160
0161     if (streq(clks->name, "cs_pdbg_clk"))
0162         init.ops = &dbgclk_ops;
0163     else
0164         init.ops = &gateclk_ops;
0165
0166     init.name = clks->name;
0167     init.flags = clks->flags;
0168
0169     init.num_parents = clks->num_parents;
0170     init.parent_names = parent_name ? &parent_name : NULL;
0171     if (init.parent_names == NULL)
0172         init.parent_data = clks->parent_data;
0173     socfpga_clk->hw.hw.init = &init;
0174
0175     hw_clk = &socfpga_clk->hw.hw;
0176
0177     ret = clk_hw_register(NULL, &socfpga_clk->hw.hw);
0178     if (ret) {
0179         kfree(socfpga_clk);
0180         return ERR_PTR(ret);
0181     }
0182     return hw_clk;
0183 }
0184
0185 struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
0186 {
0187     struct clk_hw *hw_clk;
0188     struct socfpga_gate_clk *socfpga_clk;
0189     struct clk_init_data init;
0190     const char *parent_name = clks->parent_name;
0191     int ret;
0192
0193     socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
0194     if (!socfpga_clk)
0195         return NULL;
0196
0197     socfpga_clk->hw.reg = regbase + clks->gate_reg;
0198     socfpga_clk->hw.bit_idx = clks->gate_idx;
0199
0200     gateclk_ops.enable = clk_gate_ops.enable;
0201     gateclk_ops.disable = clk_gate_ops.disable;
0202
0203     socfpga_clk->fixed_div = clks->fixed_div;
0204
0205     if (clks->div_reg)
0206         socfpga_clk->div_reg = regbase + clks->div_reg;
0207     else
0208         socfpga_clk->div_reg = NULL;
0209
0210     socfpga_clk->width = clks->div_width;
0211     socfpga_clk->shift = clks->div_offset;
0212
0213     if (clks->bypass_reg)
0214         socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
0215     else
0216         socfpga_clk->bypass_reg = NULL;
0217     socfpga_clk->bypass_shift = clks->bypass_shift;
0218
0219     if (streq(clks->name, "cs_pdbg_clk"))
0220         init.ops = &dbgclk_ops;
0221     else
0222         init.ops = &agilex_gateclk_ops;
0223
0224     init.name = clks->name;
0225     init.flags = clks->flags;
0226
0227     init.num_parents = clks->num_parents;
0228     init.parent_names = parent_name ? &parent_name : NULL;
0229     if (init.parent_names == NULL)
0230         init.parent_data = clks->parent_data;
0231     socfpga_clk->hw.hw.init = &init;
0232
0233     hw_clk = &socfpga_clk->hw.hw;
0234
0235     ret = clk_hw_register(NULL, &socfpga_clk->hw.hw);
0236     if (ret) {
0237         kfree(socfpga_clk);
0238         return ERR_PTR(ret);
0239     }
0240     return hw_clk;
0241 }