clk/sifive/fu740-prci.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2020-2021 SiFive, Inc.
0004  * Copyright (C) 2020-2021 Zong Li
0005  */
0006
0007 #ifndef __SIFIVE_CLK_FU740_PRCI_H
0008 #define __SIFIVE_CLK_FU740_PRCI_H
0009
0010 #include <linux/module.h>
0011
0012 #include <dt-bindings/clock/sifive-fu740-prci.h>
0013
0014 #include "sifive-prci.h"
0015
0016 /* PRCI integration data for each WRPLL instance */
0017
0018 static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = {
0019     .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
0020     .cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
0021     .enable_bypass = sifive_prci_coreclksel_use_hfclk,
0022     .disable_bypass = sifive_prci_coreclksel_use_final_corepll,
0023 };
0024
0025 static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = {
0026     .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
0027     .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
0028 };
0029
0030 static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = {
0031     .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
0032     .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
0033 };
0034
0035 static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = {
0036     .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
0037     .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
0038     .enable_bypass = sifive_prci_corepllsel_use_corepll,
0039     .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
0040 };
0041
0042 static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = {
0043     .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
0044     .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
0045     .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
0046     .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
0047 };
0048
0049 static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = {
0050     .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
0051     .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
0052 };
0053
0054 /* Linux clock framework integration */
0055
0056 static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
0057     .set_rate = sifive_prci_wrpll_set_rate,
0058     .round_rate = sifive_prci_wrpll_round_rate,
0059     .recalc_rate = sifive_prci_wrpll_recalc_rate,
0060     .enable = sifive_prci_clock_enable,
0061     .disable = sifive_prci_clock_disable,
0062     .is_enabled = sifive_clk_is_enabled,
0063 };
0064
0065 static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
0066     .recalc_rate = sifive_prci_wrpll_recalc_rate,
0067 };
0068
0069 static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
0070     .recalc_rate = sifive_prci_tlclksel_recalc_rate,
0071 };
0072
0073 static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
0074     .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
0075 };
0076
0077 static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
0078     .enable = sifive_prci_pcie_aux_clock_enable,
0079     .disable = sifive_prci_pcie_aux_clock_disable,
0080     .is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
0081 };
0082
0083 /* List of clock controls provided by the PRCI */
0084 static struct __prci_clock __prci_init_clocks_fu740[] = {
0085     [FU740_PRCI_CLK_COREPLL] = {
0086         .name = "corepll",
0087         .parent_name = "hfclk",
0088         .ops = &sifive_fu740_prci_wrpll_clk_ops,
0089         .pwd = &sifive_fu740_prci_corepll_data,
0090     },
0091     [FU740_PRCI_CLK_DDRPLL] = {
0092         .name = "ddrpll",
0093         .parent_name = "hfclk",
0094         .ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
0095         .pwd = &sifive_fu740_prci_ddrpll_data,
0096     },
0097     [FU740_PRCI_CLK_GEMGXLPLL] = {
0098         .name = "gemgxlpll",
0099         .parent_name = "hfclk",
0100         .ops = &sifive_fu740_prci_wrpll_clk_ops,
0101         .pwd = &sifive_fu740_prci_gemgxlpll_data,
0102     },
0103     [FU740_PRCI_CLK_DVFSCOREPLL] = {
0104         .name = "dvfscorepll",
0105         .parent_name = "hfclk",
0106         .ops = &sifive_fu740_prci_wrpll_clk_ops,
0107         .pwd = &sifive_fu740_prci_dvfscorepll_data,
0108     },
0109     [FU740_PRCI_CLK_HFPCLKPLL] = {
0110         .name = "hfpclkpll",
0111         .parent_name = "hfclk",
0112         .ops = &sifive_fu740_prci_wrpll_clk_ops,
0113         .pwd = &sifive_fu740_prci_hfpclkpll_data,
0114     },
0115     [FU740_PRCI_CLK_CLTXPLL] = {
0116         .name = "cltxpll",
0117         .parent_name = "hfclk",
0118         .ops = &sifive_fu740_prci_wrpll_clk_ops,
0119         .pwd = &sifive_fu740_prci_cltxpll_data,
0120     },
0121     [FU740_PRCI_CLK_TLCLK] = {
0122         .name = "tlclk",
0123         .parent_name = "corepll",
0124         .ops = &sifive_fu740_prci_tlclksel_clk_ops,
0125     },
0126     [FU740_PRCI_CLK_PCLK] = {
0127         .name = "pclk",
0128         .parent_name = "hfpclkpll",
0129         .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
0130     },
0131     [FU740_PRCI_CLK_PCIE_AUX] = {
0132         .name = "pcie_aux",
0133         .parent_name = "hfclk",
0134         .ops = &sifive_fu740_prci_pcie_aux_clk_ops,
0135     },
0136 };
0137
0138 static const struct prci_clk_desc prci_clk_fu740 = {
0139     .clks = __prci_init_clocks_fu740,
0140     .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740),
0141 };
0142
0143 #endif /* __SIFIVE_CLK_FU740_PRCI_H */