clk/sifive/fu540-prci.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2018-2021 SiFive, Inc.
0004  * Copyright (C) 2018-2019 Wesley Terpstra
0005  * Copyright (C) 2018-2019 Paul Walmsley
0006  * Copyright (C) 2020-2021 Zong Li
0007  *
0008  * The FU540 PRCI implements clock and reset control for the SiFive
0009  * FU540-C000 chip.  This driver assumes that it has sole control
0010  * over all PRCI resources.
0011  *
0012  * This driver is based on the PRCI driver written by Wesley Terpstra:
0013  * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
0014  *
0015  * References:
0016  * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
0017  */
0018
0019 #ifndef __SIFIVE_CLK_FU540_PRCI_H
0020 #define __SIFIVE_CLK_FU540_PRCI_H
0021
0022
0023 #include <linux/module.h>
0024
0025 #include <dt-bindings/clock/sifive-fu540-prci.h>
0026
0027 #include "sifive-prci.h"
0028
0029 /* PRCI integration data for each WRPLL instance */
0030
0031 static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = {
0032     .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
0033     .cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
0034     .enable_bypass = sifive_prci_coreclksel_use_hfclk,
0035     .disable_bypass = sifive_prci_coreclksel_use_corepll,
0036 };
0037
0038 static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = {
0039     .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
0040     .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
0041 };
0042
0043 static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = {
0044     .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
0045     .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
0046 };
0047
0048 /* Linux clock framework integration */
0049
0050 static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
0051     .set_rate = sifive_prci_wrpll_set_rate,
0052     .round_rate = sifive_prci_wrpll_round_rate,
0053     .recalc_rate = sifive_prci_wrpll_recalc_rate,
0054     .enable = sifive_prci_clock_enable,
0055     .disable = sifive_prci_clock_disable,
0056     .is_enabled = sifive_clk_is_enabled,
0057 };
0058
0059 static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
0060     .recalc_rate = sifive_prci_wrpll_recalc_rate,
0061 };
0062
0063 static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
0064     .recalc_rate = sifive_prci_tlclksel_recalc_rate,
0065 };
0066
0067 /* List of clock controls provided by the PRCI */
0068 static struct __prci_clock __prci_init_clocks_fu540[] = {
0069     [FU540_PRCI_CLK_COREPLL] = {
0070         .name = "corepll",
0071         .parent_name = "hfclk",
0072         .ops = &sifive_fu540_prci_wrpll_clk_ops,
0073         .pwd = &sifive_fu540_prci_corepll_data,
0074     },
0075     [FU540_PRCI_CLK_DDRPLL] = {
0076         .name = "ddrpll",
0077         .parent_name = "hfclk",
0078         .ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
0079         .pwd = &sifive_fu540_prci_ddrpll_data,
0080     },
0081     [FU540_PRCI_CLK_GEMGXLPLL] = {
0082         .name = "gemgxlpll",
0083         .parent_name = "hfclk",
0084         .ops = &sifive_fu540_prci_wrpll_clk_ops,
0085         .pwd = &sifive_fu540_prci_gemgxlpll_data,
0086     },
0087     [FU540_PRCI_CLK_TLCLK] = {
0088         .name = "tlclk",
0089         .parent_name = "corepll",
0090         .ops = &sifive_fu540_prci_tlclksel_clk_ops,
0091     },
0092 };
0093
0094 static const struct prci_clk_desc prci_clk_fu540 = {
0095     .clks = __prci_init_clocks_fu540,
0096     .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
0097 };
0098
0099 #endif /* __SIFIVE_CLK_FU540_PRCI_H */