clk/samsung/clk.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0004  * Copyright (c) 2013 Linaro Ltd.
0005  * Author: Thomas Abraham <thomas.ab@samsung.com>
0006  *
0007  * Common Clock Framework support for all Samsung platforms
0008 */
0009
0010 #ifndef __SAMSUNG_CLK_H
0011 #define __SAMSUNG_CLK_H
0012
0013 #include <linux/clk-provider.h>
0014 #include "clk-pll.h"
0015
0016 /**
0017  * struct samsung_clk_provider: information about clock provider
0018  * @reg_base: virtual address for the register base.
0019  * @lock: maintains exclusion between callbacks for a given clock-provider.
0020  * @clk_data: holds clock related data like clk_hw* and number of clocks.
0021  */
0022 struct samsung_clk_provider {
0023     void __iomem *reg_base;
0024     struct device *dev;
0025     spinlock_t lock;
0026     /* clk_data must be the last entry due to variable length 'hws' array */
0027     struct clk_hw_onecell_data clk_data;
0028 };
0029
0030 /**
0031  * struct samsung_clock_alias: information about mux clock
0032  * @id: platform specific id of the clock.
0033  * @dev_name: name of the device to which this clock belongs.
0034  * @alias: optional clock alias name to be assigned to this clock.
0035  */
0036 struct samsung_clock_alias {
0037     unsigned int        id;
0038     const char      *dev_name;
0039     const char      *alias;
0040 };
0041
0042 #define ALIAS(_id, dname, a)    \
0043     {                           \
0044         .id     = _id,              \
0045         .dev_name   = dname,            \
0046         .alias      = a,                \
0047     }
0048
0049 #define MHZ (1000 * 1000)
0050
0051 /**
0052  * struct samsung_fixed_rate_clock: information about fixed-rate clock
0053  * @id: platform specific id of the clock.
0054  * @name: name of this fixed-rate clock.
0055  * @parent_name: optional parent clock name.
0056  * @flags: optional fixed-rate clock flags.
0057  * @fixed-rate: fixed clock rate of this clock.
0058  */
0059 struct samsung_fixed_rate_clock {
0060     unsigned int        id;
0061     char            *name;
0062     const char      *parent_name;
0063     unsigned long       flags;
0064     unsigned long       fixed_rate;
0065 };
0066
0067 #define FRATE(_id, cname, pname, f, frate)      \
0068     {                       \
0069         .id     = _id,          \
0070         .name       = cname,        \
0071         .parent_name    = pname,        \
0072         .flags      = f,            \
0073         .fixed_rate = frate,        \
0074     }
0075
0076 /*
0077  * struct samsung_fixed_factor_clock: information about fixed-factor clock
0078  * @id: platform specific id of the clock.
0079  * @name: name of this fixed-factor clock.
0080  * @parent_name: parent clock name.
0081  * @mult: fixed multiplication factor.
0082  * @div: fixed division factor.
0083  * @flags: optional fixed-factor clock flags.
0084  */
0085 struct samsung_fixed_factor_clock {
0086     unsigned int        id;
0087     char            *name;
0088     const char      *parent_name;
0089     unsigned long       mult;
0090     unsigned long       div;
0091     unsigned long       flags;
0092 };
0093
0094 #define FFACTOR(_id, cname, pname, m, d, f)     \
0095     {                       \
0096         .id     = _id,          \
0097         .name       = cname,        \
0098         .parent_name    = pname,        \
0099         .mult       = m,            \
0100         .div        = d,            \
0101         .flags      = f,            \
0102     }
0103
0104 /**
0105  * struct samsung_mux_clock: information about mux clock
0106  * @id: platform specific id of the clock.
0107  * @name: name of this mux clock.
0108  * @parent_names: array of pointer to parent clock names.
0109  * @num_parents: number of parents listed in @parent_names.
0110  * @flags: optional flags for basic clock.
0111  * @offset: offset of the register for configuring the mux.
0112  * @shift: starting bit location of the mux control bit-field in @reg.
0113  * @width: width of the mux control bit-field in @reg.
0114  * @mux_flags: flags for mux-type clock.
0115  */
0116 struct samsung_mux_clock {
0117     unsigned int        id;
0118     const char      *name;
0119     const char      *const *parent_names;
0120     u8          num_parents;
0121     unsigned long       flags;
0122     unsigned long       offset;
0123     u8          shift;
0124     u8          width;
0125     u8          mux_flags;
0126 };
0127
0128 #define __MUX(_id, cname, pnames, o, s, w, f, mf)       \
0129     {                           \
0130         .id     = _id,              \
0131         .name       = cname,            \
0132         .parent_names   = pnames,           \
0133         .num_parents    = ARRAY_SIZE(pnames),       \
0134         .flags      = (f) | CLK_SET_RATE_NO_REPARENT, \
0135         .offset     = o,                \
0136         .shift      = s,                \
0137         .width      = w,                \
0138         .mux_flags  = mf,               \
0139     }
0140
0141 #define MUX(_id, cname, pnames, o, s, w)            \
0142     __MUX(_id, cname, pnames, o, s, w, 0, 0)
0143
0144 #define MUX_F(_id, cname, pnames, o, s, w, f, mf)       \
0145     __MUX(_id, cname, pnames, o, s, w, f, mf)
0146
0147 /**
0148  * @id: platform specific id of the clock.
0149  * struct samsung_div_clock: information about div clock
0150  * @name: name of this div clock.
0151  * @parent_name: name of the parent clock.
0152  * @flags: optional flags for basic clock.
0153  * @offset: offset of the register for configuring the div.
0154  * @shift: starting bit location of the div control bit-field in @reg.
0155  * @div_flags: flags for div-type clock.
0156  */
0157 struct samsung_div_clock {
0158     unsigned int        id;
0159     const char      *name;
0160     const char      *parent_name;
0161     unsigned long       flags;
0162     unsigned long       offset;
0163     u8          shift;
0164     u8          width;
0165     u8          div_flags;
0166     struct clk_div_table    *table;
0167 };
0168
0169 #define __DIV(_id, cname, pname, o, s, w, f, df, t) \
0170     {                           \
0171         .id     = _id,              \
0172         .name       = cname,            \
0173         .parent_name    = pname,            \
0174         .flags      = f,                \
0175         .offset     = o,                \
0176         .shift      = s,                \
0177         .width      = w,                \
0178         .div_flags  = df,               \
0179         .table      = t,                \
0180     }
0181
0182 #define DIV(_id, cname, pname, o, s, w)             \
0183     __DIV(_id, cname, pname, o, s, w, 0, 0, NULL)
0184
0185 #define DIV_F(_id, cname, pname, o, s, w, f, df)        \
0186     __DIV(_id, cname, pname, o, s, w, f, df, NULL)
0187
0188 #define DIV_T(_id, cname, pname, o, s, w, t)            \
0189     __DIV(_id, cname, pname, o, s, w, 0, 0, t)
0190
0191 /**
0192  * struct samsung_gate_clock: information about gate clock
0193  * @id: platform specific id of the clock.
0194  * @name: name of this gate clock.
0195  * @parent_name: name of the parent clock.
0196  * @flags: optional flags for basic clock.
0197  * @offset: offset of the register for configuring the gate.
0198  * @bit_idx: bit index of the gate control bit-field in @reg.
0199  * @gate_flags: flags for gate-type clock.
0200  */
0201 struct samsung_gate_clock {
0202     unsigned int        id;
0203     const char      *name;
0204     const char      *parent_name;
0205     unsigned long       flags;
0206     unsigned long       offset;
0207     u8          bit_idx;
0208     u8          gate_flags;
0209 };
0210
0211 #define __GATE(_id, cname, pname, o, b, f, gf)          \
0212     {                           \
0213         .id     = _id,              \
0214         .name       = cname,            \
0215         .parent_name    = pname,            \
0216         .flags      = f,                \
0217         .offset     = o,                \
0218         .bit_idx    = b,                \
0219         .gate_flags = gf,               \
0220     }
0221
0222 #define GATE(_id, cname, pname, o, b, f, gf)            \
0223     __GATE(_id, cname, pname, o, b, f, gf)
0224
0225 #define PNAME(x) static const char * const x[] __initconst
0226
0227 /**
0228  * struct samsung_clk_reg_dump: register dump of clock controller registers.
0229  * @offset: clock register offset from the controller base address.
0230  * @value: the value to be register at offset.
0231  */
0232 struct samsung_clk_reg_dump {
0233     u32 offset;
0234     u32 value;
0235 };
0236
0237 /**
0238  * struct samsung_pll_clock: information about pll clock
0239  * @id: platform specific id of the clock.
0240  * @name: name of this pll clock.
0241  * @parent_name: name of the parent clock.
0242  * @flags: optional flags for basic clock.
0243  * @con_offset: offset of the register for configuring the PLL.
0244  * @lock_offset: offset of the register for locking the PLL.
0245  * @type: Type of PLL to be registered.
0246  */
0247 struct samsung_pll_clock {
0248     unsigned int        id;
0249     const char      *name;
0250     const char      *parent_name;
0251     unsigned long       flags;
0252     int         con_offset;
0253     int         lock_offset;
0254     enum samsung_pll_type   type;
0255     const struct samsung_pll_rate_table *rate_table;
0256 };
0257
0258 #define __PLL(_typ, _id, _name, _pname, _flags, _lock, _con, _rtable)   \
0259     {                               \
0260         .id     = _id,                  \
0261         .type       = _typ,                 \
0262         .name       = _name,                \
0263         .parent_name    = _pname,               \
0264         .flags      = _flags,               \
0265         .con_offset = _con,                 \
0266         .lock_offset    = _lock,                \
0267         .rate_table = _rtable,              \
0268     }
0269
0270 #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \
0271     __PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock,    \
0272           _con, _rtable)
0273
0274 struct samsung_cpu_clock {
0275     unsigned int    id;
0276     const char  *name;
0277     unsigned int    parent_id;
0278     unsigned int    alt_parent_id;
0279     unsigned long   flags;
0280     int     offset;
0281     const struct exynos_cpuclk_cfg_data *cfg;
0282 };
0283
0284 #define CPU_CLK(_id, _name, _pid, _apid, _flags, _offset, _cfg) \
0285     {                           \
0286         .id       = _id,            \
0287         .name         = _name,          \
0288         .parent_id    = _pid,           \
0289         .alt_parent_id    = _apid,          \
0290         .flags        = _flags,         \
0291         .offset       = _offset,            \
0292         .cfg          = _cfg,           \
0293     }
0294
0295 struct samsung_clock_reg_cache {
0296     struct list_head node;
0297     void __iomem *reg_base;
0298     struct samsung_clk_reg_dump *rdump;
0299     unsigned int rd_num;
0300     const struct samsung_clk_reg_dump *rsuspend;
0301     unsigned int rsuspend_num;
0302 };
0303
0304 struct samsung_cmu_info {
0305     /* list of pll clocks and respective count */
0306     const struct samsung_pll_clock *pll_clks;
0307     unsigned int nr_pll_clks;
0308     /* list of mux clocks and respective count */
0309     const struct samsung_mux_clock *mux_clks;
0310     unsigned int nr_mux_clks;
0311     /* list of div clocks and respective count */
0312     const struct samsung_div_clock *div_clks;
0313     unsigned int nr_div_clks;
0314     /* list of gate clocks and respective count */
0315     const struct samsung_gate_clock *gate_clks;
0316     unsigned int nr_gate_clks;
0317     /* list of fixed clocks and respective count */
0318     const struct samsung_fixed_rate_clock *fixed_clks;
0319     unsigned int nr_fixed_clks;
0320     /* list of fixed factor clocks and respective count */
0321     const struct samsung_fixed_factor_clock *fixed_factor_clks;
0322     unsigned int nr_fixed_factor_clks;
0323     /* total number of clocks with IDs assigned*/
0324     unsigned int nr_clk_ids;
0325     /* list of cpu clocks and respective count */
0326     const struct samsung_cpu_clock *cpu_clks;
0327     unsigned int nr_cpu_clks;
0328
0329     /* list and number of clocks registers */
0330     const unsigned long *clk_regs;
0331     unsigned int nr_clk_regs;
0332
0333     /* list and number of clocks registers to set before suspend */
0334     const struct samsung_clk_reg_dump *suspend_regs;
0335     unsigned int nr_suspend_regs;
0336     /* name of the parent clock needed for CMU register access */
0337     const char *clk_name;
0338 };
0339
0340 struct samsung_clk_provider * samsung_clk_init(
0341             struct device_node *np, void __iomem *base,
0342             unsigned long nr_clks);
0343 void samsung_clk_of_add_provider(struct device_node *np,
0344             struct samsung_clk_provider *ctx);
0345 void samsung_clk_of_register_fixed_ext(
0346             struct samsung_clk_provider *ctx,
0347             struct samsung_fixed_rate_clock *fixed_rate_clk,
0348             unsigned int nr_fixed_rate_clk,
0349             const struct of_device_id *clk_matches);
0350
0351 void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
0352             struct clk_hw *clk_hw, unsigned int id);
0353
0354 void samsung_clk_register_alias(struct samsung_clk_provider *ctx,
0355             const struct samsung_clock_alias *list,
0356             unsigned int nr_clk);
0357 void samsung_clk_register_fixed_rate(
0358             struct samsung_clk_provider *ctx,
0359             const struct samsung_fixed_rate_clock *clk_list,
0360             unsigned int nr_clk);
0361 void samsung_clk_register_fixed_factor(
0362             struct samsung_clk_provider *ctx,
0363             const struct samsung_fixed_factor_clock *list,
0364             unsigned int nr_clk);
0365 void samsung_clk_register_mux(struct samsung_clk_provider *ctx,
0366             const struct samsung_mux_clock *clk_list,
0367             unsigned int nr_clk);
0368 void samsung_clk_register_div(struct samsung_clk_provider *ctx,
0369             const struct samsung_div_clock *clk_list,
0370             unsigned int nr_clk);
0371 void samsung_clk_register_gate(struct samsung_clk_provider *ctx,
0372             const struct samsung_gate_clock *clk_list,
0373             unsigned int nr_clk);
0374 void samsung_clk_register_pll(struct samsung_clk_provider *ctx,
0375             const struct samsung_pll_clock *pll_list,
0376             unsigned int nr_clk, void __iomem *base);
0377 void samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
0378         const struct samsung_cpu_clock *list, unsigned int nr_clk);
0379
0380 struct samsung_clk_provider *samsung_cmu_register_one(
0381             struct device_node *,
0382             const struct samsung_cmu_info *);
0383
0384 #ifdef CONFIG_PM_SLEEP
0385 void samsung_clk_extended_sleep_init(void __iomem *reg_base,
0386             const unsigned long *rdump,
0387             unsigned long nr_rdump,
0388             const struct samsung_clk_reg_dump *rsuspend,
0389             unsigned long nr_rsuspend);
0390 #else
0391 static inline void samsung_clk_extended_sleep_init(void __iomem *reg_base,
0392             const unsigned long *rdump,
0393             unsigned long nr_rdump,
0394             const struct samsung_clk_reg_dump *rsuspend,
0395             unsigned long nr_rsuspend) {}
0396 #endif
0397 #define samsung_clk_sleep_init(reg_base, rdump, nr_rdump) \
0398     samsung_clk_extended_sleep_init(reg_base, rdump, nr_rdump, NULL, 0)
0399
0400 void samsung_clk_save(void __iomem *base,
0401             struct samsung_clk_reg_dump *rd,
0402             unsigned int num_regs);
0403 void samsung_clk_restore(void __iomem *base,
0404             const struct samsung_clk_reg_dump *rd,
0405             unsigned int num_regs);
0406 struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
0407             const unsigned long *rdump,
0408             unsigned long nr_rdump);
0409
0410 #endif /* __SAMSUNG_CLK_H */