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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0004  * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
0005  *
0006  * Based on clock drivers for S3C64xx and Exynos4 SoCs.
0007  *
0008  * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
0009  */
0010 
0011 #include <linux/clk-provider.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 
0015 #include "clk.h"
0016 #include "clk-pll.h"
0017 
0018 #include <dt-bindings/clock/s5pv210.h>
0019 
0020 /* S5PC110/S5PV210 clock controller register offsets */
0021 #define APLL_LOCK       0x0000
0022 #define MPLL_LOCK       0x0008
0023 #define EPLL_LOCK       0x0010
0024 #define VPLL_LOCK       0x0020
0025 #define APLL_CON0       0x0100
0026 #define APLL_CON1       0x0104
0027 #define MPLL_CON        0x0108
0028 #define EPLL_CON0       0x0110
0029 #define EPLL_CON1       0x0114
0030 #define VPLL_CON        0x0120
0031 #define CLK_SRC0        0x0200
0032 #define CLK_SRC1        0x0204
0033 #define CLK_SRC2        0x0208
0034 #define CLK_SRC3        0x020c
0035 #define CLK_SRC4        0x0210
0036 #define CLK_SRC5        0x0214
0037 #define CLK_SRC6        0x0218
0038 #define CLK_SRC_MASK0       0x0280
0039 #define CLK_SRC_MASK1       0x0284
0040 #define CLK_DIV0        0x0300
0041 #define CLK_DIV1        0x0304
0042 #define CLK_DIV2        0x0308
0043 #define CLK_DIV3        0x030c
0044 #define CLK_DIV4        0x0310
0045 #define CLK_DIV5        0x0314
0046 #define CLK_DIV6        0x0318
0047 #define CLK_DIV7        0x031c
0048 #define CLK_GATE_MAIN0      0x0400
0049 #define CLK_GATE_MAIN1      0x0404
0050 #define CLK_GATE_MAIN2      0x0408
0051 #define CLK_GATE_PERI0      0x0420
0052 #define CLK_GATE_PERI1      0x0424
0053 #define CLK_GATE_SCLK0      0x0440
0054 #define CLK_GATE_SCLK1      0x0444
0055 #define CLK_GATE_IP0        0x0460
0056 #define CLK_GATE_IP1        0x0464
0057 #define CLK_GATE_IP2        0x0468
0058 #define CLK_GATE_IP3        0x046c
0059 #define CLK_GATE_IP4        0x0470
0060 #define CLK_GATE_BLOCK      0x0480
0061 #define CLK_GATE_IP5        0x0484
0062 #define CLK_OUT         0x0500
0063 #define MISC            0xe000
0064 #define OM_STAT         0xe100
0065 
0066 /* IDs of PLLs available on S5PV210/S5P6442 SoCs */
0067 enum {
0068     apll,
0069     mpll,
0070     epll,
0071     vpll,
0072 };
0073 
0074 /* IDs of external clocks (used for legacy boards) */
0075 enum {
0076     xxti,
0077     xusbxti,
0078 };
0079 
0080 static void __iomem *reg_base;
0081 
0082 /* List of registers that need to be preserved across suspend/resume. */
0083 static unsigned long s5pv210_clk_regs[] __initdata = {
0084     CLK_SRC0,
0085     CLK_SRC1,
0086     CLK_SRC2,
0087     CLK_SRC3,
0088     CLK_SRC4,
0089     CLK_SRC5,
0090     CLK_SRC6,
0091     CLK_SRC_MASK0,
0092     CLK_SRC_MASK1,
0093     CLK_DIV0,
0094     CLK_DIV1,
0095     CLK_DIV2,
0096     CLK_DIV3,
0097     CLK_DIV4,
0098     CLK_DIV5,
0099     CLK_DIV6,
0100     CLK_DIV7,
0101     CLK_GATE_MAIN0,
0102     CLK_GATE_MAIN1,
0103     CLK_GATE_MAIN2,
0104     CLK_GATE_PERI0,
0105     CLK_GATE_PERI1,
0106     CLK_GATE_SCLK0,
0107     CLK_GATE_SCLK1,
0108     CLK_GATE_IP0,
0109     CLK_GATE_IP1,
0110     CLK_GATE_IP2,
0111     CLK_GATE_IP3,
0112     CLK_GATE_IP4,
0113     CLK_GATE_IP5,
0114     CLK_GATE_BLOCK,
0115     APLL_LOCK,
0116     MPLL_LOCK,
0117     EPLL_LOCK,
0118     VPLL_LOCK,
0119     APLL_CON0,
0120     APLL_CON1,
0121     MPLL_CON,
0122     EPLL_CON0,
0123     EPLL_CON1,
0124     VPLL_CON,
0125     CLK_OUT,
0126 };
0127 
0128 /* Mux parent lists. */
0129 static const char *const fin_pll_p[] __initconst = {
0130     "xxti",
0131     "xusbxti"
0132 };
0133 
0134 static const char *const mout_apll_p[] __initconst = {
0135     "fin_pll",
0136     "fout_apll"
0137 };
0138 
0139 static const char *const mout_mpll_p[] __initconst = {
0140     "fin_pll",
0141     "fout_mpll"
0142 };
0143 
0144 static const char *const mout_epll_p[] __initconst = {
0145     "fin_pll",
0146     "fout_epll"
0147 };
0148 
0149 static const char *const mout_vpllsrc_p[] __initconst = {
0150     "fin_pll",
0151     "sclk_hdmi27m"
0152 };
0153 
0154 static const char *const mout_vpll_p[] __initconst = {
0155     "mout_vpllsrc",
0156     "fout_vpll"
0157 };
0158 
0159 static const char *const mout_group1_p[] __initconst = {
0160     "dout_a2m",
0161     "mout_mpll",
0162     "mout_epll",
0163     "mout_vpll"
0164 };
0165 
0166 static const char *const mout_group2_p[] __initconst = {
0167     "xxti",
0168     "xusbxti",
0169     "sclk_hdmi27m",
0170     "sclk_usbphy0",
0171     "sclk_usbphy1",
0172     "sclk_hdmiphy",
0173     "mout_mpll",
0174     "mout_epll",
0175     "mout_vpll",
0176 };
0177 
0178 static const char *const mout_audio0_p[] __initconst = {
0179     "xxti",
0180     "pcmcdclk0",
0181     "sclk_hdmi27m",
0182     "sclk_usbphy0",
0183     "sclk_usbphy1",
0184     "sclk_hdmiphy",
0185     "mout_mpll",
0186     "mout_epll",
0187     "mout_vpll",
0188 };
0189 
0190 static const char *const mout_audio1_p[] __initconst = {
0191     "i2scdclk1",
0192     "pcmcdclk1",
0193     "sclk_hdmi27m",
0194     "sclk_usbphy0",
0195     "sclk_usbphy1",
0196     "sclk_hdmiphy",
0197     "mout_mpll",
0198     "mout_epll",
0199     "mout_vpll",
0200 };
0201 
0202 static const char *const mout_audio2_p[] __initconst = {
0203     "i2scdclk2",
0204     "pcmcdclk2",
0205     "sclk_hdmi27m",
0206     "sclk_usbphy0",
0207     "sclk_usbphy1",
0208     "sclk_hdmiphy",
0209     "mout_mpll",
0210     "mout_epll",
0211     "mout_vpll",
0212 };
0213 
0214 static const char *const mout_spdif_p[] __initconst = {
0215     "dout_audio0",
0216     "dout_audio1",
0217     "dout_audio3",
0218 };
0219 
0220 static const char *const mout_group3_p[] __initconst = {
0221     "mout_apll",
0222     "mout_mpll"
0223 };
0224 
0225 static const char *const mout_group4_p[] __initconst = {
0226     "mout_mpll",
0227     "dout_a2m"
0228 };
0229 
0230 static const char *const mout_flash_p[] __initconst = {
0231     "dout_hclkd",
0232     "dout_hclkp"
0233 };
0234 
0235 static const char *const mout_dac_p[] __initconst = {
0236     "mout_vpll",
0237     "sclk_hdmiphy"
0238 };
0239 
0240 static const char *const mout_hdmi_p[] __initconst = {
0241     "sclk_hdmiphy",
0242     "dout_tblk"
0243 };
0244 
0245 static const char *const mout_mixer_p[] __initconst = {
0246     "mout_dac",
0247     "mout_hdmi"
0248 };
0249 
0250 static const char *const mout_vpll_6442_p[] __initconst = {
0251     "fin_pll",
0252     "fout_vpll"
0253 };
0254 
0255 static const char *const mout_mixer_6442_p[] __initconst = {
0256     "mout_vpll",
0257     "dout_mixer"
0258 };
0259 
0260 static const char *const mout_d0sync_6442_p[] __initconst = {
0261     "mout_dsys",
0262     "div_apll"
0263 };
0264 
0265 static const char *const mout_d1sync_6442_p[] __initconst = {
0266     "mout_psys",
0267     "div_apll"
0268 };
0269 
0270 static const char *const mout_group2_6442_p[] __initconst = {
0271     "fin_pll",
0272     "none",
0273     "none",
0274     "sclk_usbphy0",
0275     "none",
0276     "none",
0277     "mout_mpll",
0278     "mout_epll",
0279     "mout_vpll",
0280 };
0281 
0282 static const char *const mout_audio0_6442_p[] __initconst = {
0283     "fin_pll",
0284     "pcmcdclk0",
0285     "none",
0286     "sclk_usbphy0",
0287     "none",
0288     "none",
0289     "mout_mpll",
0290     "mout_epll",
0291     "mout_vpll",
0292 };
0293 
0294 static const char *const mout_audio1_6442_p[] __initconst = {
0295     "i2scdclk1",
0296     "pcmcdclk1",
0297     "none",
0298     "sclk_usbphy0",
0299     "none",
0300     "none",
0301     "mout_mpll",
0302     "mout_epll",
0303     "mout_vpll",
0304     "fin_pll",
0305 };
0306 
0307 static const char *const mout_clksel_p[] __initconst = {
0308     "fout_apll_clkout",
0309     "fout_mpll_clkout",
0310     "fout_epll",
0311     "fout_vpll",
0312     "sclk_usbphy0",
0313     "sclk_usbphy1",
0314     "sclk_hdmiphy",
0315     "rtc",
0316     "rtc_tick",
0317     "dout_hclkm",
0318     "dout_pclkm",
0319     "dout_hclkd",
0320     "dout_pclkd",
0321     "dout_hclkp",
0322     "dout_pclkp",
0323     "dout_apll_clkout",
0324     "dout_hpm",
0325     "xxti",
0326     "xusbxti",
0327     "div_dclk"
0328 };
0329 
0330 static const char *const mout_clksel_6442_p[] __initconst = {
0331     "fout_apll_clkout",
0332     "fout_mpll_clkout",
0333     "fout_epll",
0334     "fout_vpll",
0335     "sclk_usbphy0",
0336     "none",
0337     "none",
0338     "rtc",
0339     "rtc_tick",
0340     "none",
0341     "none",
0342     "dout_hclkd",
0343     "dout_pclkd",
0344     "dout_hclkp",
0345     "dout_pclkp",
0346     "dout_apll_clkout",
0347     "none",
0348     "fin_pll",
0349     "none",
0350     "div_dclk"
0351 };
0352 
0353 static const char *const mout_clkout_p[] __initconst = {
0354     "dout_clkout",
0355     "none",
0356     "xxti",
0357     "xusbxti"
0358 };
0359 
0360 /* Common fixed factor clocks. */
0361 static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = {
0362     FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0),
0363     FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0),
0364     FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0),
0365 };
0366 
0367 /* PLL input mux (fin_pll), which needs to be registered before PLLs. */
0368 static const struct samsung_mux_clock early_mux_clks[] __initconst = {
0369     MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1,
0370                     CLK_MUX_READ_ONLY, 0),
0371 };
0372 
0373 /* Common clock muxes. */
0374 static const struct samsung_mux_clock mux_clks[] __initconst = {
0375     MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1),
0376     MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1),
0377     MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1),
0378     MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1),
0379     MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1),
0380     MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1),
0381     MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1),
0382 
0383     MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
0384 };
0385 
0386 /* S5PV210-specific clock muxes. */
0387 static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = {
0388     MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1),
0389 
0390     MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1),
0391     MUX(MOUT_CSIS, "mout_csis", mout_group2_p, CLK_SRC1, 24, 4),
0392     MUX(MOUT_FIMD, "mout_fimd", mout_group2_p, CLK_SRC1, 20, 4),
0393     MUX(MOUT_CAM1, "mout_cam1", mout_group2_p, CLK_SRC1, 16, 4),
0394     MUX(MOUT_CAM0, "mout_cam0", mout_group2_p, CLK_SRC1, 12, 4),
0395     MUX(MOUT_DAC, "mout_dac", mout_dac_p, CLK_SRC1, 8, 1),
0396     MUX(MOUT_MIXER, "mout_mixer", mout_mixer_p, CLK_SRC1, 4, 1),
0397     MUX(MOUT_HDMI, "mout_hdmi", mout_hdmi_p, CLK_SRC1, 0, 1),
0398 
0399     MUX(MOUT_G2D, "mout_g2d", mout_group1_p, CLK_SRC2, 8, 2),
0400     MUX(MOUT_MFC, "mout_mfc", mout_group1_p, CLK_SRC2, 4, 2),
0401     MUX(MOUT_G3D, "mout_g3d", mout_group1_p, CLK_SRC2, 0, 2),
0402 
0403     MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_p, CLK_SRC3, 20, 4),
0404     MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_p, CLK_SRC3, 16, 4),
0405     MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_p, CLK_SRC3, 12, 4),
0406 
0407     MUX(MOUT_UART3, "mout_uart3", mout_group2_p, CLK_SRC4, 28, 4),
0408     MUX(MOUT_UART2, "mout_uart2", mout_group2_p, CLK_SRC4, 24, 4),
0409     MUX(MOUT_UART1, "mout_uart1", mout_group2_p, CLK_SRC4, 20, 4),
0410     MUX(MOUT_UART0, "mout_uart0", mout_group2_p, CLK_SRC4, 16, 4),
0411     MUX(MOUT_MMC3, "mout_mmc3", mout_group2_p, CLK_SRC4, 12, 4),
0412     MUX(MOUT_MMC2, "mout_mmc2", mout_group2_p, CLK_SRC4, 8, 4),
0413     MUX(MOUT_MMC1, "mout_mmc1", mout_group2_p, CLK_SRC4, 4, 4),
0414     MUX(MOUT_MMC0, "mout_mmc0", mout_group2_p, CLK_SRC4, 0, 4),
0415 
0416     MUX(MOUT_PWM, "mout_pwm", mout_group2_p, CLK_SRC5, 12, 4),
0417     MUX(MOUT_SPI1, "mout_spi1", mout_group2_p, CLK_SRC5, 4, 4),
0418     MUX(MOUT_SPI0, "mout_spi0", mout_group2_p, CLK_SRC5, 0, 4),
0419 
0420     MUX(MOUT_DMC0, "mout_dmc0", mout_group1_p, CLK_SRC6, 24, 2),
0421     MUX(MOUT_PWI, "mout_pwi", mout_group2_p, CLK_SRC6, 20, 4),
0422     MUX(MOUT_HPM, "mout_hpm", mout_group3_p, CLK_SRC6, 16, 1),
0423     MUX(MOUT_SPDIF, "mout_spdif", mout_spdif_p, CLK_SRC6, 12, 2),
0424     MUX(MOUT_AUDIO2, "mout_audio2", mout_audio2_p, CLK_SRC6, 8, 4),
0425     MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_p, CLK_SRC6, 4, 4),
0426     MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_p, CLK_SRC6, 0, 4),
0427 
0428     MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_p, CLK_OUT, 12, 5),
0429 };
0430 
0431 /* S5P6442-specific clock muxes. */
0432 static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = {
0433     MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1),
0434 
0435     MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4),
0436     MUX(MOUT_CAM1, "mout_cam1", mout_group2_6442_p, CLK_SRC1, 16, 4),
0437     MUX(MOUT_CAM0, "mout_cam0", mout_group2_6442_p, CLK_SRC1, 12, 4),
0438     MUX(MOUT_MIXER, "mout_mixer", mout_mixer_6442_p, CLK_SRC1, 4, 1),
0439 
0440     MUX(MOUT_D0SYNC, "mout_d0sync", mout_d0sync_6442_p, CLK_SRC2, 28, 1),
0441     MUX(MOUT_D1SYNC, "mout_d1sync", mout_d1sync_6442_p, CLK_SRC2, 24, 1),
0442 
0443     MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_6442_p, CLK_SRC3, 20, 4),
0444     MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_6442_p, CLK_SRC3, 16, 4),
0445     MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_6442_p, CLK_SRC3, 12, 4),
0446 
0447     MUX(MOUT_UART2, "mout_uart2", mout_group2_6442_p, CLK_SRC4, 24, 4),
0448     MUX(MOUT_UART1, "mout_uart1", mout_group2_6442_p, CLK_SRC4, 20, 4),
0449     MUX(MOUT_UART0, "mout_uart0", mout_group2_6442_p, CLK_SRC4, 16, 4),
0450     MUX(MOUT_MMC2, "mout_mmc2", mout_group2_6442_p, CLK_SRC4, 8, 4),
0451     MUX(MOUT_MMC1, "mout_mmc1", mout_group2_6442_p, CLK_SRC4, 4, 4),
0452     MUX(MOUT_MMC0, "mout_mmc0", mout_group2_6442_p, CLK_SRC4, 0, 4),
0453 
0454     MUX(MOUT_PWM, "mout_pwm", mout_group2_6442_p, CLK_SRC5, 12, 4),
0455     MUX(MOUT_SPI0, "mout_spi0", mout_group2_6442_p, CLK_SRC5, 0, 4),
0456 
0457     MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_6442_p, CLK_SRC6, 4, 4),
0458     MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_6442_p, CLK_SRC6, 0, 4),
0459 
0460     MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_6442_p, CLK_OUT, 12, 5),
0461 };
0462 
0463 /* S5PV210-specific fixed rate clocks generated inside the SoC. */
0464 static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = {
0465     FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, 0, 27000000),
0466     FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000),
0467     FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 48000000),
0468     FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, 0, 48000000),
0469 };
0470 
0471 /* S5P6442-specific fixed rate clocks generated inside the SoC. */
0472 static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = {
0473     FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 30000000),
0474 };
0475 
0476 /* Common clock dividers. */
0477 static const struct samsung_div_clock div_clks[] __initconst = {
0478     DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3),
0479     DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3),
0480     DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3),
0481     DIV(DOUT_APLL, "dout_apll", "mout_msys", CLK_DIV0, 0, 3),
0482 
0483     DIV(DOUT_FIMD, "dout_fimd", "mout_fimd", CLK_DIV1, 20, 4),
0484     DIV(DOUT_CAM1, "dout_cam1", "mout_cam1", CLK_DIV1, 16, 4),
0485     DIV(DOUT_CAM0, "dout_cam0", "mout_cam0", CLK_DIV1, 12, 4),
0486 
0487     DIV(DOUT_FIMC2, "dout_fimc2", "mout_fimc2", CLK_DIV3, 20, 4),
0488     DIV(DOUT_FIMC1, "dout_fimc1", "mout_fimc1", CLK_DIV3, 16, 4),
0489     DIV(DOUT_FIMC0, "dout_fimc0", "mout_fimc0", CLK_DIV3, 12, 4),
0490 
0491     DIV(DOUT_UART2, "dout_uart2", "mout_uart2", CLK_DIV4, 24, 4),
0492     DIV(DOUT_UART1, "dout_uart1", "mout_uart1", CLK_DIV4, 20, 4),
0493     DIV(DOUT_UART0, "dout_uart0", "mout_uart0", CLK_DIV4, 16, 4),
0494     DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV4, 8, 4),
0495     DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV4, 4, 4),
0496     DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV4, 0, 4),
0497 
0498     DIV(DOUT_PWM, "dout_pwm", "mout_pwm", CLK_DIV5, 12, 4),
0499     DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV5, 0, 4),
0500 
0501     DIV(DOUT_FLASH, "dout_flash", "mout_flash", CLK_DIV6, 12, 3),
0502     DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV6, 4, 4),
0503     DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV6, 0, 4),
0504 
0505     DIV(DOUT_CLKOUT, "dout_clkout", "mout_clksel", CLK_OUT, 20, 4),
0506 };
0507 
0508 /* S5PV210-specific clock dividers. */
0509 static const struct samsung_div_clock s5pv210_div_clks[] __initconst = {
0510     DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4),
0511     DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4),
0512     DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3),
0513     DIV(DOUT_HCLKM, "dout_hclkm", "dout_apll", CLK_DIV0, 8, 3),
0514 
0515     DIV(DOUT_CSIS, "dout_csis", "mout_csis", CLK_DIV1, 28, 4),
0516     DIV(DOUT_TBLK, "dout_tblk", "mout_vpll", CLK_DIV1, 0, 4),
0517 
0518     DIV(DOUT_G2D, "dout_g2d", "mout_g2d", CLK_DIV2, 8, 4),
0519     DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV2, 4, 4),
0520     DIV(DOUT_G3D, "dout_g3d", "mout_g3d", CLK_DIV2, 0, 4),
0521 
0522     DIV(DOUT_UART3, "dout_uart3", "mout_uart3", CLK_DIV4, 28, 4),
0523     DIV(DOUT_MMC3, "dout_mmc3", "mout_mmc3", CLK_DIV4, 12, 4),
0524 
0525     DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV5, 4, 4),
0526 
0527     DIV(DOUT_DMC0, "dout_dmc0", "mout_dmc0", CLK_DIV6, 28, 4),
0528     DIV(DOUT_PWI, "dout_pwi", "mout_pwi", CLK_DIV6, 24, 4),
0529     DIV(DOUT_HPM, "dout_hpm", "dout_copy", CLK_DIV6, 20, 3),
0530     DIV(DOUT_COPY, "dout_copy", "mout_hpm", CLK_DIV6, 16, 3),
0531     DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV6, 8, 4),
0532 
0533     DIV(DOUT_DPM, "dout_dpm", "dout_pclkp", CLK_DIV7, 8, 7),
0534     DIV(DOUT_DVSEM, "dout_dvsem", "dout_pclkp", CLK_DIV7, 0, 7),
0535 };
0536 
0537 /* S5P6442-specific clock dividers. */
0538 static const struct samsung_div_clock s5p6442_div_clks[] __initconst = {
0539     DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4),
0540     DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4),
0541 
0542     DIV(DOUT_MIXER, "dout_mixer", "mout_vpll", CLK_DIV1, 0, 4),
0543 };
0544 
0545 /* Common clock gates. */
0546 static const struct samsung_gate_clock gate_clks[] __initconst = {
0547     GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0),
0548     GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0),
0549     GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0),
0550     GATE(CLK_FIMC0, "fimc0", "dout_hclkd", CLK_GATE_IP0, 24, 0, 0),
0551     GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0),
0552     GATE(CLK_MDMA, "mdma", "dout_hclkd", CLK_GATE_IP0, 2, 0, 0),
0553 
0554     GATE(CLK_SROMC, "sromc", "dout_hclkp", CLK_GATE_IP1, 26, 0, 0),
0555     GATE(CLK_NANDXL, "nandxl", "dout_hclkp", CLK_GATE_IP1, 24, 0, 0),
0556     GATE(CLK_USB_OTG, "usb_otg", "dout_hclkp", CLK_GATE_IP1, 16, 0, 0),
0557     GATE(CLK_TVENC, "tvenc", "dout_hclkd", CLK_GATE_IP1, 10, 0, 0),
0558     GATE(CLK_MIXER, "mixer", "dout_hclkd", CLK_GATE_IP1, 9, 0, 0),
0559     GATE(CLK_VP, "vp", "dout_hclkd", CLK_GATE_IP1, 8, 0, 0),
0560     GATE(CLK_FIMD, "fimd", "dout_hclkd", CLK_GATE_IP1, 0, 0, 0),
0561 
0562     GATE(CLK_HSMMC2, "hsmmc2", "dout_hclkp", CLK_GATE_IP2, 18, 0, 0),
0563     GATE(CLK_HSMMC1, "hsmmc1", "dout_hclkp", CLK_GATE_IP2, 17, 0, 0),
0564     GATE(CLK_HSMMC0, "hsmmc0", "dout_hclkp", CLK_GATE_IP2, 16, 0, 0),
0565     GATE(CLK_MODEMIF, "modemif", "dout_hclkp", CLK_GATE_IP2, 9, 0, 0),
0566     GATE(CLK_SECSS, "secss", "dout_hclkp", CLK_GATE_IP2, 0, 0, 0),
0567 
0568     GATE(CLK_PCM1, "pcm1", "dout_pclkp", CLK_GATE_IP3, 29, 0, 0),
0569     GATE(CLK_PCM0, "pcm0", "dout_pclkp", CLK_GATE_IP3, 28, 0, 0),
0570     GATE(CLK_TSADC, "tsadc", "dout_pclkp", CLK_GATE_IP3, 24, 0, 0),
0571     GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0),
0572     GATE(CLK_WDT, "watchdog", "dout_pclkp", CLK_GATE_IP3, 22, 0, 0),
0573     GATE(CLK_KEYIF, "keyif", "dout_pclkp", CLK_GATE_IP3, 21, 0, 0),
0574     GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0),
0575     GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
0576     GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
0577     GATE(CLK_SYSTIMER, "systimer", "dout_pclkp", CLK_GATE_IP3, 16, 0, 0),
0578     GATE(CLK_RTC, "rtc", "dout_pclkp", CLK_GATE_IP3, 15, 0, 0),
0579     GATE(CLK_SPI0, "spi0", "dout_pclkp", CLK_GATE_IP3, 12, 0, 0),
0580     GATE(CLK_I2C2, "i2c2", "dout_pclkp", CLK_GATE_IP3, 9, 0, 0),
0581     GATE(CLK_I2C0, "i2c0", "dout_pclkp", CLK_GATE_IP3, 7, 0, 0),
0582     GATE(CLK_I2S1, "i2s1", "dout_pclkp", CLK_GATE_IP3, 5, 0, 0),
0583     GATE(CLK_I2S0, "i2s0", "dout_pclkp", CLK_GATE_IP3, 4, 0, 0),
0584 
0585     GATE(CLK_SECKEY, "seckey", "dout_pclkp", CLK_GATE_IP4, 3, 0, 0),
0586     GATE(CLK_CHIPID, "chipid", "dout_pclkp", CLK_GATE_IP4, 0, 0, 0),
0587 
0588     GATE(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", CLK_SRC_MASK0, 25,
0589             CLK_SET_RATE_PARENT, 0),
0590     GATE(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", CLK_SRC_MASK0, 24,
0591             CLK_SET_RATE_PARENT, 0),
0592     GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
0593             CLK_SET_RATE_PARENT, 0),
0594     GATE(SCLK_SPI0, "sclk_spi0", "dout_spi0", CLK_SRC_MASK0, 16,
0595             CLK_SET_RATE_PARENT, 0),
0596     GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14,
0597             CLK_SET_RATE_PARENT, 0),
0598     GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,
0599             CLK_SET_RATE_PARENT, 0),
0600     GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12,
0601             CLK_SET_RATE_PARENT, 0),
0602     GATE(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", CLK_SRC_MASK0, 10,
0603             CLK_SET_RATE_PARENT, 0),
0604     GATE(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", CLK_SRC_MASK0, 9,
0605             CLK_SET_RATE_PARENT, 0),
0606     GATE(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", CLK_SRC_MASK0, 8,
0607             CLK_SET_RATE_PARENT, 0),
0608     GATE(SCLK_FIMD, "sclk_fimd", "dout_fimd", CLK_SRC_MASK0, 5,
0609             CLK_SET_RATE_PARENT, 0),
0610     GATE(SCLK_CAM1, "sclk_cam1", "dout_cam1", CLK_SRC_MASK0, 4,
0611             CLK_SET_RATE_PARENT, 0),
0612     GATE(SCLK_CAM0, "sclk_cam0", "dout_cam0", CLK_SRC_MASK0, 3,
0613             CLK_SET_RATE_PARENT, 0),
0614     GATE(SCLK_MIXER, "sclk_mixer", "mout_mixer", CLK_SRC_MASK0, 1,
0615             CLK_SET_RATE_PARENT, 0),
0616 
0617     GATE(SCLK_FIMC2, "sclk_fimc2", "dout_fimc2", CLK_SRC_MASK1, 4,
0618             CLK_SET_RATE_PARENT, 0),
0619     GATE(SCLK_FIMC1, "sclk_fimc1", "dout_fimc1", CLK_SRC_MASK1, 3,
0620             CLK_SET_RATE_PARENT, 0),
0621     GATE(SCLK_FIMC0, "sclk_fimc0", "dout_fimc0", CLK_SRC_MASK1, 2,
0622             CLK_SET_RATE_PARENT, 0),
0623 };
0624 
0625 /* S5PV210-specific clock gates. */
0626 static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = {
0627     GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0),
0628     GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0),
0629     GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
0630     GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
0631     GATE(CLK_IMEM, "imem", "dout_hclkm", CLK_GATE_IP0, 5, 0, 0),
0632     GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0),
0633 
0634     GATE(CLK_NFCON, "nfcon", "dout_hclkp", CLK_GATE_IP1, 28, 0, 0),
0635     GATE(CLK_CFCON, "cfcon", "dout_hclkp", CLK_GATE_IP1, 25, 0, 0),
0636     GATE(CLK_USB_HOST, "usb_host", "dout_hclkp", CLK_GATE_IP1, 17, 0, 0),
0637     GATE(CLK_HDMI, "hdmi", "dout_hclkd", CLK_GATE_IP1, 11, 0, 0),
0638     GATE(CLK_DSIM, "dsim", "dout_pclkd", CLK_GATE_IP1, 2, 0, 0),
0639 
0640     GATE(CLK_TZIC3, "tzic3", "dout_hclkm", CLK_GATE_IP2, 31, 0, 0),
0641     GATE(CLK_TZIC2, "tzic2", "dout_hclkm", CLK_GATE_IP2, 30, 0, 0),
0642     GATE(CLK_TZIC1, "tzic1", "dout_hclkm", CLK_GATE_IP2, 29, 0, 0),
0643     GATE(CLK_TZIC0, "tzic0", "dout_hclkm", CLK_GATE_IP2, 28, 0, 0),
0644     GATE(CLK_TSI, "tsi", "dout_hclkd", CLK_GATE_IP2, 20, 0, 0),
0645     GATE(CLK_HSMMC3, "hsmmc3", "dout_hclkp", CLK_GATE_IP2, 19, 0, 0),
0646     GATE(CLK_JTAG, "jtag", "dout_hclkp", CLK_GATE_IP2, 11, 0, 0),
0647     GATE(CLK_CORESIGHT, "coresight", "dout_pclkp", CLK_GATE_IP2, 8, 0, 0),
0648     GATE(CLK_SDM, "sdm", "dout_pclkm", CLK_GATE_IP2, 1, 0, 0),
0649 
0650     GATE(CLK_PCM2, "pcm2", "dout_pclkp", CLK_GATE_IP3, 30, 0, 0),
0651     GATE(CLK_UART3, "uart3", "dout_pclkp", CLK_GATE_IP3, 20, 0, 0),
0652     GATE(CLK_SPI1, "spi1", "dout_pclkp", CLK_GATE_IP3, 13, 0, 0),
0653     GATE(CLK_I2C_HDMI_PHY, "i2c_hdmi_phy", "dout_pclkd",
0654             CLK_GATE_IP3, 11, 0, 0),
0655     GATE(CLK_I2C1, "i2c1", "dout_pclkd", CLK_GATE_IP3, 10, 0, 0),
0656     GATE(CLK_I2S2, "i2s2", "dout_pclkp", CLK_GATE_IP3, 6, 0, 0),
0657     GATE(CLK_AC97, "ac97", "dout_pclkp", CLK_GATE_IP3, 1, 0, 0),
0658     GATE(CLK_SPDIF, "spdif", "dout_pclkp", CLK_GATE_IP3, 0, 0, 0),
0659 
0660     GATE(CLK_TZPC3, "tzpc.3", "dout_pclkd", CLK_GATE_IP4, 8, 0, 0),
0661     GATE(CLK_TZPC2, "tzpc.2", "dout_pclkd", CLK_GATE_IP4, 7, 0, 0),
0662     GATE(CLK_TZPC1, "tzpc.1", "dout_pclkp", CLK_GATE_IP4, 6, 0, 0),
0663     GATE(CLK_TZPC0, "tzpc.0", "dout_pclkm", CLK_GATE_IP4, 5, 0, 0),
0664     GATE(CLK_IEM_APC, "iem_apc", "dout_pclkp", CLK_GATE_IP4, 2, 0, 0),
0665     GATE(CLK_IEM_IEC, "iem_iec", "dout_pclkp", CLK_GATE_IP4, 1, 0, 0),
0666 
0667     GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP5, 29, 0, 0),
0668 
0669     GATE(SCLK_SPDIF, "sclk_spdif", "mout_spdif", CLK_SRC_MASK0, 27,
0670             CLK_SET_RATE_PARENT, 0),
0671     GATE(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", CLK_SRC_MASK0, 26,
0672             CLK_SET_RATE_PARENT, 0),
0673     GATE(SCLK_SPI1, "sclk_spi1", "dout_spi1", CLK_SRC_MASK0, 17,
0674             CLK_SET_RATE_PARENT, 0),
0675     GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15,
0676             CLK_SET_RATE_PARENT, 0),
0677     GATE(SCLK_MMC3, "sclk_mmc3", "dout_mmc3", CLK_SRC_MASK0, 11,
0678             CLK_SET_RATE_PARENT, 0),
0679     GATE(SCLK_CSIS, "sclk_csis", "dout_csis", CLK_SRC_MASK0, 6,
0680             CLK_SET_RATE_PARENT, 0),
0681     GATE(SCLK_DAC, "sclk_dac", "mout_dac", CLK_SRC_MASK0, 2,
0682             CLK_SET_RATE_PARENT, 0),
0683     GATE(SCLK_HDMI, "sclk_hdmi", "mout_hdmi", CLK_SRC_MASK0, 0,
0684             CLK_SET_RATE_PARENT, 0),
0685 };
0686 
0687 /* S5P6442-specific clock gates. */
0688 static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = {
0689     GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0),
0690     GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0),
0691     GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
0692     GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),
0693     GATE(CLK_IMEM, "imem", "dout_hclkd", CLK_GATE_IP0, 5, 0, 0),
0694 
0695     GATE(CLK_ETB, "etb", "dout_hclkd", CLK_GATE_IP1, 31, 0, 0),
0696     GATE(CLK_ETM, "etm", "dout_hclkd", CLK_GATE_IP1, 30, 0, 0),
0697 
0698     GATE(CLK_I2C1, "i2c1", "dout_pclkp", CLK_GATE_IP3, 8, 0, 0),
0699 
0700     GATE(SCLK_DAC, "sclk_dac", "mout_vpll", CLK_SRC_MASK0, 2,
0701             CLK_SET_RATE_PARENT, 0),
0702 };
0703 
0704 /*
0705  * Clock aliases for legacy clkdev look-up.
0706  * NOTE: Needed only to support legacy board files.
0707  */
0708 static const struct samsung_clock_alias s5pv210_aliases[] __initconst = {
0709     ALIAS(DOUT_APLL, NULL, "armclk"),
0710     ALIAS(DOUT_HCLKM, NULL, "hclk_msys"),
0711     ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"),
0712 };
0713 
0714 /* S5PV210-specific PLLs. */
0715 static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = {
0716     [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll",
0717                         APLL_LOCK, APLL_CON0, NULL),
0718     [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
0719                         MPLL_LOCK, MPLL_CON, NULL),
0720     [epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll",
0721                         EPLL_LOCK, EPLL_CON0, NULL),
0722     [vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
0723                         VPLL_LOCK, VPLL_CON, NULL),
0724 };
0725 
0726 /* S5P6442-specific PLLs. */
0727 static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = {
0728     [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll",
0729                         APLL_LOCK, APLL_CON0, NULL),
0730     [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
0731                         MPLL_LOCK, MPLL_CON, NULL),
0732     [epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll",
0733                         EPLL_LOCK, EPLL_CON0, NULL),
0734     [vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll",
0735                         VPLL_LOCK, VPLL_CON, NULL),
0736 };
0737 
0738 static void __init __s5pv210_clk_init(struct device_node *np,
0739                       unsigned long xxti_f,
0740                       unsigned long xusbxti_f,
0741                       bool is_s5p6442)
0742 {
0743     struct samsung_clk_provider *ctx;
0744     struct clk_hw **hws;
0745 
0746     ctx = samsung_clk_init(np, reg_base, NR_CLKS);
0747     hws = ctx->clk_data.hws;
0748 
0749     samsung_clk_register_mux(ctx, early_mux_clks,
0750                     ARRAY_SIZE(early_mux_clks));
0751 
0752     if (is_s5p6442) {
0753         samsung_clk_register_fixed_rate(ctx, s5p6442_frate_clks,
0754             ARRAY_SIZE(s5p6442_frate_clks));
0755         samsung_clk_register_pll(ctx, s5p6442_pll_clks,
0756             ARRAY_SIZE(s5p6442_pll_clks), reg_base);
0757         samsung_clk_register_mux(ctx, s5p6442_mux_clks,
0758                 ARRAY_SIZE(s5p6442_mux_clks));
0759         samsung_clk_register_div(ctx, s5p6442_div_clks,
0760                 ARRAY_SIZE(s5p6442_div_clks));
0761         samsung_clk_register_gate(ctx, s5p6442_gate_clks,
0762                 ARRAY_SIZE(s5p6442_gate_clks));
0763     } else {
0764         samsung_clk_register_fixed_rate(ctx, s5pv210_frate_clks,
0765             ARRAY_SIZE(s5pv210_frate_clks));
0766         samsung_clk_register_pll(ctx, s5pv210_pll_clks,
0767             ARRAY_SIZE(s5pv210_pll_clks), reg_base);
0768         samsung_clk_register_mux(ctx, s5pv210_mux_clks,
0769                 ARRAY_SIZE(s5pv210_mux_clks));
0770         samsung_clk_register_div(ctx, s5pv210_div_clks,
0771                 ARRAY_SIZE(s5pv210_div_clks));
0772         samsung_clk_register_gate(ctx, s5pv210_gate_clks,
0773                 ARRAY_SIZE(s5pv210_gate_clks));
0774     }
0775 
0776     samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
0777     samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
0778     samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
0779 
0780     samsung_clk_register_fixed_factor(ctx, ffactor_clks,
0781                         ARRAY_SIZE(ffactor_clks));
0782 
0783     samsung_clk_register_alias(ctx, s5pv210_aliases,
0784                         ARRAY_SIZE(s5pv210_aliases));
0785 
0786     samsung_clk_sleep_init(reg_base, s5pv210_clk_regs,
0787                    ARRAY_SIZE(s5pv210_clk_regs));
0788 
0789     samsung_clk_of_add_provider(np, ctx);
0790 
0791     pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n"
0792         "\tmout_epll = %ld, mout_vpll = %ld\n",
0793         is_s5p6442 ? "S5P6442" : "S5PV210",
0794         clk_hw_get_rate(hws[MOUT_APLL]),
0795         clk_hw_get_rate(hws[MOUT_MPLL]),
0796         clk_hw_get_rate(hws[MOUT_EPLL]),
0797         clk_hw_get_rate(hws[MOUT_VPLL]));
0798 }
0799 
0800 static void __init s5pv210_clk_dt_init(struct device_node *np)
0801 {
0802     reg_base = of_iomap(np, 0);
0803     if (!reg_base)
0804         panic("%s: failed to map registers\n", __func__);
0805 
0806     __s5pv210_clk_init(np, 0, 0, false);
0807 }
0808 CLK_OF_DECLARE(s5pv210_clk, "samsung,s5pv210-clock", s5pv210_clk_dt_init);
0809 
0810 static void __init s5p6442_clk_dt_init(struct device_node *np)
0811 {
0812     reg_base = of_iomap(np, 0);
0813     if (!reg_base)
0814         panic("%s: failed to map registers\n", __func__);
0815 
0816     __s5pv210_clk_init(np, 0, 0, true);
0817 }
0818 CLK_OF_DECLARE(s5p6442_clk, "samsung,s5p6442-clock", s5p6442_clk_dt_init);
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