clk/samsung/clk-s5pv210-audss.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 Tomasz Figa <t.figa@samsung.com>
0004  *
0005  * Based on Exynos Audio Subsystem Clock Controller driver:
0006  *
0007  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0008  * Author: Padmavathi Venna <padma.v@samsung.com>
0009  *
0010  * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
0011 */
0012
0013 #include <linux/io.h>
0014 #include <linux/clk.h>
0015 #include <linux/clk-provider.h>
0016 #include <linux/of_address.h>
0017 #include <linux/syscore_ops.h>
0018 #include <linux/init.h>
0019 #include <linux/platform_device.h>
0020
0021 #include <dt-bindings/clock/s5pv210-audss.h>
0022
0023 static DEFINE_SPINLOCK(lock);
0024 static void __iomem *reg_base;
0025 static struct clk_hw_onecell_data *clk_data;
0026
0027 #define ASS_CLK_SRC 0x0
0028 #define ASS_CLK_DIV 0x4
0029 #define ASS_CLK_GATE 0x8
0030
0031 #ifdef CONFIG_PM_SLEEP
0032 static unsigned long reg_save[][2] = {
0033     {ASS_CLK_SRC,  0},
0034     {ASS_CLK_DIV,  0},
0035     {ASS_CLK_GATE, 0},
0036 };
0037
0038 static int s5pv210_audss_clk_suspend(void)
0039 {
0040     int i;
0041
0042     for (i = 0; i < ARRAY_SIZE(reg_save); i++)
0043         reg_save[i][1] = readl(reg_base + reg_save[i][0]);
0044
0045     return 0;
0046 }
0047
0048 static void s5pv210_audss_clk_resume(void)
0049 {
0050     int i;
0051
0052     for (i = 0; i < ARRAY_SIZE(reg_save); i++)
0053         writel(reg_save[i][1], reg_base + reg_save[i][0]);
0054 }
0055
0056 static struct syscore_ops s5pv210_audss_clk_syscore_ops = {
0057     .suspend    = s5pv210_audss_clk_suspend,
0058     .resume     = s5pv210_audss_clk_resume,
0059 };
0060 #endif /* CONFIG_PM_SLEEP */
0061
0062 /* register s5pv210_audss clocks */
0063 static int s5pv210_audss_clk_probe(struct platform_device *pdev)
0064 {
0065     int i, ret = 0;
0066     const char *mout_audss_p[2];
0067     const char *mout_i2s_p[3];
0068     const char *hclk_p;
0069     struct clk_hw **clk_table;
0070     struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio;
0071
0072     reg_base = devm_platform_ioremap_resource(pdev, 0);
0073     if (IS_ERR(reg_base))
0074         return PTR_ERR(reg_base);
0075
0076     clk_data = devm_kzalloc(&pdev->dev,
0077                 struct_size(clk_data, hws, AUDSS_MAX_CLKS),
0078                 GFP_KERNEL);
0079
0080     if (!clk_data)
0081         return -ENOMEM;
0082
0083     clk_data->num = AUDSS_MAX_CLKS;
0084     clk_table = clk_data->hws;
0085
0086     hclk = devm_clk_get(&pdev->dev, "hclk");
0087     if (IS_ERR(hclk)) {
0088         dev_err(&pdev->dev, "failed to get hclk clock\n");
0089         return PTR_ERR(hclk);
0090     }
0091
0092     pll_in = devm_clk_get(&pdev->dev, "fout_epll");
0093     if (IS_ERR(pll_in)) {
0094         dev_err(&pdev->dev, "failed to get fout_epll clock\n");
0095         return PTR_ERR(pll_in);
0096     }
0097
0098     sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0");
0099     if (IS_ERR(sclk_audio)) {
0100         dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n");
0101         return PTR_ERR(sclk_audio);
0102     }
0103
0104     /* iiscdclk0 is an optional external I2S codec clock */
0105     cdclk = devm_clk_get(&pdev->dev, "iiscdclk0");
0106     pll_ref = devm_clk_get(&pdev->dev, "xxti");
0107
0108     if (!IS_ERR(pll_ref))
0109         mout_audss_p[0] = __clk_get_name(pll_ref);
0110     else
0111         mout_audss_p[0] = "xxti";
0112     mout_audss_p[1] = __clk_get_name(pll_in);
0113     clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
0114                 mout_audss_p, ARRAY_SIZE(mout_audss_p),
0115                 CLK_SET_RATE_NO_REPARENT,
0116                 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
0117
0118     mout_i2s_p[0] = "mout_audss";
0119     if (!IS_ERR(cdclk))
0120         mout_i2s_p[1] = __clk_get_name(cdclk);
0121     else
0122         mout_i2s_p[1] = "iiscdclk0";
0123     mout_i2s_p[2] = __clk_get_name(sclk_audio);
0124     clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss",
0125                 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
0126                 CLK_SET_RATE_NO_REPARENT,
0127                 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
0128
0129     clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
0130                 "dout_aud_bus", "mout_audss", 0,
0131                 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
0132     clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL,
0133                 "dout_i2s_audss", "mout_i2s_audss", 0,
0134                 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
0135
0136     clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss",
0137                 "dout_i2s_audss", CLK_SET_RATE_PARENT,
0138                 reg_base + ASS_CLK_GATE, 6, 0, &lock);
0139
0140     hclk_p = __clk_get_name(hclk);
0141
0142     clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss",
0143                 hclk_p, CLK_IGNORE_UNUSED,
0144                 reg_base + ASS_CLK_GATE, 5, 0, &lock);
0145     clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss",
0146                 hclk_p, CLK_IGNORE_UNUSED,
0147                 reg_base + ASS_CLK_GATE, 4, 0, &lock);
0148     clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss",
0149                 hclk_p, CLK_IGNORE_UNUSED,
0150                 reg_base + ASS_CLK_GATE, 3, 0, &lock);
0151     clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss",
0152                 hclk_p, CLK_IGNORE_UNUSED,
0153                 reg_base + ASS_CLK_GATE, 2, 0, &lock);
0154     clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss",
0155                 hclk_p, CLK_IGNORE_UNUSED,
0156                 reg_base + ASS_CLK_GATE, 1, 0, &lock);
0157     clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss",
0158                 hclk_p, CLK_IGNORE_UNUSED,
0159                 reg_base + ASS_CLK_GATE, 0, 0, &lock);
0160
0161     for (i = 0; i < clk_data->num; i++) {
0162         if (IS_ERR(clk_table[i])) {
0163             dev_err(&pdev->dev, "failed to register clock %d\n", i);
0164             ret = PTR_ERR(clk_table[i]);
0165             goto unregister;
0166         }
0167     }
0168
0169     ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
0170                      clk_data);
0171     if (ret) {
0172         dev_err(&pdev->dev, "failed to add clock provider\n");
0173         goto unregister;
0174     }
0175
0176 #ifdef CONFIG_PM_SLEEP
0177     register_syscore_ops(&s5pv210_audss_clk_syscore_ops);
0178 #endif
0179
0180     return 0;
0181
0182 unregister:
0183     for (i = 0; i < clk_data->num; i++) {
0184         if (!IS_ERR(clk_table[i]))
0185             clk_hw_unregister(clk_table[i]);
0186     }
0187
0188     return ret;
0189 }
0190
0191 static const struct of_device_id s5pv210_audss_clk_of_match[] = {
0192     { .compatible = "samsung,s5pv210-audss-clock", },
0193     {},
0194 };
0195
0196 static struct platform_driver s5pv210_audss_clk_driver = {
0197     .driver = {
0198         .name = "s5pv210-audss-clk",
0199         .suppress_bind_attrs = true,
0200         .of_match_table = s5pv210_audss_clk_of_match,
0201     },
0202     .probe = s5pv210_audss_clk_probe,
0203 };
0204
0205 static int __init s5pv210_audss_clk_init(void)
0206 {
0207     return platform_driver_register(&s5pv210_audss_clk_driver);
0208 }
0209 core_initcall(s5pv210_audss_clk_init);