clk/samsung/clk-s3c64xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
0004  *
0005  * Common Clock Framework support for all S3C64xx SoCs.
0006 */
0007
0008 #include <linux/slab.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/clk/samsung.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013
0014 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
0015
0016 #include "clk.h"
0017 #include "clk-pll.h"
0018
0019 /* S3C64xx clock controller register offsets. */
0020 #define APLL_LOCK       0x000
0021 #define MPLL_LOCK       0x004
0022 #define EPLL_LOCK       0x008
0023 #define APLL_CON        0x00c
0024 #define MPLL_CON        0x010
0025 #define EPLL_CON0       0x014
0026 #define EPLL_CON1       0x018
0027 #define CLK_SRC         0x01c
0028 #define CLK_DIV0        0x020
0029 #define CLK_DIV1        0x024
0030 #define CLK_DIV2        0x028
0031 #define HCLK_GATE       0x030
0032 #define PCLK_GATE       0x034
0033 #define SCLK_GATE       0x038
0034 #define MEM0_GATE       0x03c
0035 #define CLK_SRC2        0x10c
0036 #define OTHERS          0x900
0037
0038 /* Helper macros to define clock arrays. */
0039 #define FIXED_RATE_CLOCKS(name) \
0040         static struct samsung_fixed_rate_clock name[]
0041 #define MUX_CLOCKS(name)    \
0042         static struct samsung_mux_clock name[]
0043 #define DIV_CLOCKS(name)    \
0044         static struct samsung_div_clock name[]
0045 #define GATE_CLOCKS(name)   \
0046         static struct samsung_gate_clock name[]
0047
0048 /* Helper macros for gate types present on S3C64xx. */
0049 #define GATE_BUS(_id, cname, pname, o, b) \
0050         GATE(_id, cname, pname, o, b, 0, 0)
0051 #define GATE_SCLK(_id, cname, pname, o, b) \
0052         GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
0053 #define GATE_ON(_id, cname, pname, o, b) \
0054         GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
0055
0056 static void __iomem *reg_base;
0057 static bool is_s3c6400;
0058
0059 /*
0060  * List of controller registers to be saved and restored during
0061  * a suspend/resume cycle.
0062  */
0063 static unsigned long s3c64xx_clk_regs[] __initdata = {
0064     APLL_LOCK,
0065     MPLL_LOCK,
0066     EPLL_LOCK,
0067     APLL_CON,
0068     MPLL_CON,
0069     EPLL_CON0,
0070     EPLL_CON1,
0071     CLK_SRC,
0072     CLK_DIV0,
0073     CLK_DIV1,
0074     CLK_DIV2,
0075     HCLK_GATE,
0076     PCLK_GATE,
0077     SCLK_GATE,
0078 };
0079
0080 static unsigned long s3c6410_clk_regs[] __initdata = {
0081     CLK_SRC2,
0082     MEM0_GATE,
0083 };
0084
0085 /* List of parent clocks common for all S3C64xx SoCs. */
0086 PNAME(spi_mmc_p)    = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
0087 PNAME(uart_p)       = { "mout_epll", "dout_mpll" };
0088 PNAME(audio0_p)     = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
0089                 "pcmcdclk0", "none", "none", "none" };
0090 PNAME(audio1_p)     = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
0091                 "pcmcdclk0", "none", "none", "none" };
0092 PNAME(mfc_p)        = { "hclkx2", "mout_epll" };
0093 PNAME(apll_p)       = { "fin_pll", "fout_apll" };
0094 PNAME(mpll_p)       = { "fin_pll", "fout_mpll" };
0095 PNAME(epll_p)       = { "fin_pll", "fout_epll" };
0096 PNAME(hclkx2_p)     = { "mout_mpll", "mout_apll" };
0097
0098 /* S3C6400-specific parent clocks. */
0099 PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" };
0100 PNAME(irda_p6400)   = { "mout_epll", "dout_mpll", "none", "clk48m" };
0101 PNAME(uhost_p6400)  = { "clk48m", "mout_epll", "dout_mpll", "none" };
0102
0103 /* S3C6410-specific parent clocks. */
0104 PNAME(clk27_p6410)  = { "clk27m", "fin_pll" };
0105 PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" };
0106 PNAME(irda_p6410)   = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" };
0107 PNAME(uhost_p6410)  = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" };
0108 PNAME(audio2_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk2",
0109                 "pcmcdclk1", "none", "none", "none" };
0110
0111 /* Fixed rate clocks generated outside the SoC. */
0112 FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = {
0113     FRATE(0, "fin_pll", NULL, 0, 0),
0114     FRATE(0, "xusbxti", NULL, 0, 0),
0115 };
0116
0117 /* Fixed rate clocks generated inside the SoC. */
0118 FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = {
0119     FRATE(CLK27M, "clk27m", NULL, 0, 27000000),
0120     FRATE(CLK48M, "clk48m", NULL, 0, 48000000),
0121 };
0122
0123 /* List of clock muxes present on all S3C64xx SoCs. */
0124 MUX_CLOCKS(s3c64xx_mux_clks) __initdata = {
0125     MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
0126     MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
0127     MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
0128     MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
0129     MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
0130     MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3),
0131     MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3),
0132     MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1),
0133     MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2),
0134     MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2),
0135     MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2),
0136     MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2),
0137     MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2),
0138 };
0139
0140 /* List of clock muxes present on S3C6400. */
0141 MUX_CLOCKS(s3c6400_mux_clks) __initdata = {
0142     MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2),
0143     MUX(MOUT_IRDA, "mout_irda", irda_p6400, CLK_SRC, 24, 2),
0144     MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6400, CLK_SRC, 26, 2),
0145     MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6400, CLK_SRC, 28, 2),
0146 };
0147
0148 /* List of clock muxes present on S3C6410. */
0149 MUX_CLOCKS(s3c6410_mux_clks) __initdata = {
0150     MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2),
0151     MUX(MOUT_IRDA, "mout_irda", irda_p6410, CLK_SRC, 24, 2),
0152     MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6410, CLK_SRC, 26, 2),
0153     MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6410, CLK_SRC, 28, 2),
0154     MUX(MOUT_DAC27, "mout_dac27", clk27_p6410, CLK_SRC, 30, 1),
0155     MUX(MOUT_TV27, "mout_tv27", clk27_p6410, CLK_SRC, 31, 1),
0156     MUX(MOUT_AUDIO2, "mout_audio2", audio2_p6410, CLK_SRC2, 0, 3),
0157 };
0158
0159 /* List of clock dividers present on all S3C64xx SoCs. */
0160 DIV_CLOCKS(s3c64xx_div_clks) __initdata = {
0161     DIV(DOUT_MPLL, "dout_mpll", "mout_mpll", CLK_DIV0, 4, 1),
0162     DIV(HCLKX2, "hclkx2", "mout_syncmux", CLK_DIV0, 9, 3),
0163     DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
0164     DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
0165     DIV(DOUT_SECUR, "dout_secur", "hclkx2", CLK_DIV0, 18, 2),
0166     DIV(DOUT_CAM, "dout_cam", "hclkx2", CLK_DIV0, 20, 4),
0167     DIV(DOUT_JPEG, "dout_jpeg", "hclkx2", CLK_DIV0, 24, 4),
0168     DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV0, 28, 4),
0169     DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV1, 0, 4),
0170     DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV1, 4, 4),
0171     DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV1, 8, 4),
0172     DIV(DOUT_LCD, "dout_lcd", "mout_lcd", CLK_DIV1, 12, 4),
0173     DIV(DOUT_SCALER, "dout_scaler", "mout_scaler", CLK_DIV1, 16, 4),
0174     DIV(DOUT_UHOST, "dout_uhost", "mout_uhost", CLK_DIV1, 20, 4),
0175     DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV2, 0, 4),
0176     DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV2, 4, 4),
0177     DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV2, 8, 4),
0178     DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV2, 12, 4),
0179     DIV(DOUT_UART, "dout_uart", "mout_uart", CLK_DIV2, 16, 4),
0180     DIV(DOUT_IRDA, "dout_irda", "mout_irda", CLK_DIV2, 20, 4),
0181 };
0182
0183 /* List of clock dividers present on S3C6400. */
0184 DIV_CLOCKS(s3c6400_div_clks) __initdata = {
0185     DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 3),
0186 };
0187
0188 /* List of clock dividers present on S3C6410. */
0189 DIV_CLOCKS(s3c6410_div_clks) __initdata = {
0190     DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4),
0191     DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4),
0192     DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV2, 24, 4),
0193 };
0194
0195 /* List of clock gates present on all S3C64xx SoCs. */
0196 GATE_CLOCKS(s3c64xx_gate_clks) __initdata = {
0197     GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
0198     GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
0199     GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
0200     GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
0201     GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
0202     GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
0203     GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
0204     GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
0205     GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17),
0206     GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16),
0207     GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15),
0208     GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14),
0209     GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13),
0210     GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12),
0211     GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11),
0212     GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10),
0213     GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9),
0214     GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8),
0215     GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7),
0216     GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
0217     GATE_BUS(HCLK_ROT, "hclk_rot", "hclk", HCLK_GATE, 4),
0218     GATE_BUS(HCLK_LCD, "hclk_lcd", "hclk", HCLK_GATE, 3),
0219     GATE_BUS(HCLK_TZIC, "hclk_tzic", "hclk", HCLK_GATE, 2),
0220     GATE_ON(HCLK_INTC, "hclk_intc", "hclk", HCLK_GATE, 1),
0221     GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
0222     GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
0223     GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
0224     GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
0225     GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
0226     GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
0227     GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
0228     GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
0229     GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
0230     GATE_BUS(PCLK_IIS0, "pclk_iis0", "pclk", PCLK_GATE, 15),
0231     GATE_BUS(PCLK_AC97, "pclk_ac97", "pclk", PCLK_GATE, 14),
0232     GATE_BUS(PCLK_TZPC, "pclk_tzpc", "pclk", PCLK_GATE, 13),
0233     GATE_BUS(PCLK_TSADC, "pclk_tsadc", "pclk", PCLK_GATE, 12),
0234     GATE_BUS(PCLK_KEYPAD, "pclk_keypad", "pclk", PCLK_GATE, 11),
0235     GATE_BUS(PCLK_IRDA, "pclk_irda", "pclk", PCLK_GATE, 10),
0236     GATE_BUS(PCLK_PCM1, "pclk_pcm1", "pclk", PCLK_GATE, 9),
0237     GATE_BUS(PCLK_PCM0, "pclk_pcm0", "pclk", PCLK_GATE, 8),
0238     GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7),
0239     GATE_BUS(PCLK_RTC, "pclk_rtc", "pclk", PCLK_GATE, 6),
0240     GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
0241     GATE_BUS(PCLK_UART3, "pclk_uart3", "pclk", PCLK_GATE, 4),
0242     GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3),
0243     GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2),
0244     GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1),
0245     GATE_BUS(PCLK_MFC, "pclk_mfc", "pclk", PCLK_GATE, 0),
0246     GATE_SCLK(SCLK_UHOST, "sclk_uhost", "dout_uhost", SCLK_GATE, 30),
0247     GATE_SCLK(SCLK_MMC2_48, "sclk_mmc2_48", "clk48m", SCLK_GATE, 29),
0248     GATE_SCLK(SCLK_MMC1_48, "sclk_mmc1_48", "clk48m", SCLK_GATE, 28),
0249     GATE_SCLK(SCLK_MMC0_48, "sclk_mmc0_48", "clk48m", SCLK_GATE, 27),
0250     GATE_SCLK(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", SCLK_GATE, 26),
0251     GATE_SCLK(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", SCLK_GATE, 25),
0252     GATE_SCLK(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", SCLK_GATE, 24),
0253     GATE_SCLK(SCLK_SPI1_48, "sclk_spi1_48", "clk48m", SCLK_GATE, 23),
0254     GATE_SCLK(SCLK_SPI0_48, "sclk_spi0_48", "clk48m", SCLK_GATE, 22),
0255     GATE_SCLK(SCLK_SPI1, "sclk_spi1", "dout_spi1", SCLK_GATE, 21),
0256     GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20),
0257     GATE_SCLK(SCLK_DAC27, "sclk_dac27", "mout_dac27", SCLK_GATE, 19),
0258     GATE_SCLK(SCLK_TV27, "sclk_tv27", "mout_tv27", SCLK_GATE, 18),
0259     GATE_SCLK(SCLK_SCALER27, "sclk_scaler27", "clk27m", SCLK_GATE, 17),
0260     GATE_SCLK(SCLK_SCALER, "sclk_scaler", "dout_scaler", SCLK_GATE, 16),
0261     GATE_SCLK(SCLK_LCD27, "sclk_lcd27", "clk27m", SCLK_GATE, 15),
0262     GATE_SCLK(SCLK_LCD, "sclk_lcd", "dout_lcd", SCLK_GATE, 14),
0263     GATE_SCLK(SCLK_POST0_27, "sclk_post0_27", "clk27m", SCLK_GATE, 12),
0264     GATE_SCLK(SCLK_POST0, "sclk_post0", "dout_lcd", SCLK_GATE, 10),
0265     GATE_SCLK(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", SCLK_GATE, 9),
0266     GATE_SCLK(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", SCLK_GATE, 8),
0267     GATE_SCLK(SCLK_SECUR, "sclk_secur", "dout_secur", SCLK_GATE, 7),
0268     GATE_SCLK(SCLK_IRDA, "sclk_irda", "dout_irda", SCLK_GATE, 6),
0269     GATE_SCLK(SCLK_UART, "sclk_uart", "dout_uart", SCLK_GATE, 5),
0270     GATE_SCLK(SCLK_MFC, "sclk_mfc", "dout_mfc", SCLK_GATE, 3),
0271     GATE_SCLK(SCLK_CAM, "sclk_cam", "dout_cam", SCLK_GATE, 2),
0272     GATE_SCLK(SCLK_JPEG, "sclk_jpeg", "dout_jpeg", SCLK_GATE, 1),
0273 };
0274
0275 /* List of clock gates present on S3C6400. */
0276 GATE_CLOCKS(s3c6400_gate_clks) __initdata = {
0277     GATE_ON(HCLK_DDR0, "hclk_ddr0", "hclk", HCLK_GATE, 23),
0278     GATE_SCLK(SCLK_ONENAND, "sclk_onenand", "parent", SCLK_GATE, 4),
0279 };
0280
0281 /* List of clock gates present on S3C6410. */
0282 GATE_CLOCKS(s3c6410_gate_clks) __initdata = {
0283     GATE_BUS(HCLK_3DSE, "hclk_3dse", "hclk", HCLK_GATE, 31),
0284     GATE_ON(HCLK_IROM, "hclk_irom", "hclk", HCLK_GATE, 25),
0285     GATE_ON(HCLK_MEM1, "hclk_mem1", "hclk", HCLK_GATE, 22),
0286     GATE_ON(HCLK_MEM0, "hclk_mem0", "hclk", HCLK_GATE, 21),
0287     GATE_BUS(HCLK_MFC, "hclk_mfc", "hclk", HCLK_GATE, 0),
0288     GATE_BUS(PCLK_IIC1, "pclk_iic1", "pclk", PCLK_GATE, 27),
0289     GATE_BUS(PCLK_IIS2, "pclk_iis2", "pclk", PCLK_GATE, 26),
0290     GATE_SCLK(SCLK_FIMC, "sclk_fimc", "dout_fimc", SCLK_GATE, 13),
0291     GATE_SCLK(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", SCLK_GATE, 11),
0292     GATE_BUS(MEM0_CFCON, "mem0_cfcon", "hclk_mem0", MEM0_GATE, 5),
0293     GATE_BUS(MEM0_ONENAND1, "mem0_onenand1", "hclk_mem0", MEM0_GATE, 4),
0294     GATE_BUS(MEM0_ONENAND0, "mem0_onenand0", "hclk_mem0", MEM0_GATE, 3),
0295     GATE_BUS(MEM0_NFCON, "mem0_nfcon", "hclk_mem0", MEM0_GATE, 2),
0296     GATE_ON(MEM0_SROM, "mem0_srom", "hclk_mem0", MEM0_GATE, 1),
0297 };
0298
0299 /* List of PLL clocks. */
0300 static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = {
0301     PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
0302                     APLL_LOCK, APLL_CON, NULL),
0303     PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
0304                     MPLL_LOCK, MPLL_CON, NULL),
0305     PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
0306                     EPLL_LOCK, EPLL_CON0, NULL),
0307 };
0308
0309 /* Aliases for common s3c64xx clocks. */
0310 static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
0311     ALIAS(FOUT_APLL, NULL, "fout_apll"),
0312     ALIAS(FOUT_MPLL, NULL, "fout_mpll"),
0313     ALIAS(FOUT_EPLL, NULL, "fout_epll"),
0314     ALIAS(MOUT_EPLL, NULL, "mout_epll"),
0315     ALIAS(DOUT_MPLL, NULL, "dout_mpll"),
0316     ALIAS(HCLKX2, NULL, "hclk2"),
0317     ALIAS(HCLK, NULL, "hclk"),
0318     ALIAS(PCLK, NULL, "pclk"),
0319     ALIAS(PCLK, NULL, "clk_uart_baud2"),
0320     ALIAS(ARMCLK, NULL, "armclk"),
0321     ALIAS(HCLK_UHOST, "s3c2410-ohci", "usb-host"),
0322     ALIAS(HCLK_USB, "s3c-hsotg", "otg"),
0323     ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "hsmmc"),
0324     ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "mmc_busclk.0"),
0325     ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
0326     ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
0327     ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
0328     ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
0329     ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
0330     ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
0331     ALIAS(HCLK_CAMIF, "s3c-camif", "camif"),
0332     ALIAS(HCLK_LCD, "s3c-fb", "lcd"),
0333     ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"),
0334     ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi"),
0335     ALIAS(PCLK_IIC0, "s3c2440-i2c.0", "i2c"),
0336     ALIAS(PCLK_IIS1, "samsung-i2s.1", "iis"),
0337     ALIAS(PCLK_IIS0, "samsung-i2s.0", "iis"),
0338     ALIAS(PCLK_AC97, "samsung-ac97", "ac97"),
0339     ALIAS(PCLK_TSADC, "s3c64xx-adc", "adc"),
0340     ALIAS(PCLK_KEYPAD, "samsung-keypad", "keypad"),
0341     ALIAS(PCLK_PCM1, "samsung-pcm.1", "pcm"),
0342     ALIAS(PCLK_PCM0, "samsung-pcm.0", "pcm"),
0343     ALIAS(PCLK_PWM, NULL, "timers"),
0344     ALIAS(PCLK_RTC, "s3c64xx-rtc", "rtc"),
0345     ALIAS(PCLK_WDT, NULL, "watchdog"),
0346     ALIAS(PCLK_UART3, "s3c6400-uart.3", "uart"),
0347     ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"),
0348     ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"),
0349     ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),
0350     ALIAS(SCLK_UHOST, "s3c2410-ohci", "usb-bus-host"),
0351     ALIAS(SCLK_MMC2, "s3c-sdhci.2", "mmc_busclk.2"),
0352     ALIAS(SCLK_MMC1, "s3c-sdhci.1", "mmc_busclk.2"),
0353     ALIAS(SCLK_MMC0, "s3c-sdhci.0", "mmc_busclk.2"),
0354     ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi_busclk0"),
0355     ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi_busclk2"),
0356     ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi_busclk0"),
0357     ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"),
0358     ALIAS(SCLK_AUDIO1, "samsung-pcm.1", "audio-bus"),
0359     ALIAS(SCLK_AUDIO1, "samsung-i2s.1", "audio-bus"),
0360     ALIAS(SCLK_AUDIO0, "samsung-pcm.0", "audio-bus"),
0361     ALIAS(SCLK_AUDIO0, "samsung-i2s.0", "audio-bus"),
0362     ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
0363     ALIAS(SCLK_CAM, "s3c-camif", "camera"),
0364 };
0365
0366 /* Aliases for s3c6400-specific clocks. */
0367 static struct samsung_clock_alias s3c6400_clock_aliases[] = {
0368     /* Nothing to place here yet. */
0369 };
0370
0371 /* Aliases for s3c6410-specific clocks. */
0372 static struct samsung_clock_alias s3c6410_clock_aliases[] = {
0373     ALIAS(PCLK_IIC1, "s3c2440-i2c.1", "i2c"),
0374     ALIAS(PCLK_IIS2, "samsung-i2s.2", "iis"),
0375     ALIAS(SCLK_FIMC, "s3c-camif", "fimc"),
0376     ALIAS(SCLK_AUDIO2, "samsung-i2s.2", "audio-bus"),
0377     ALIAS(MEM0_SROM, NULL, "srom"),
0378 };
0379
0380 static void __init s3c64xx_clk_register_fixed_ext(
0381                 struct samsung_clk_provider *ctx,
0382                 unsigned long fin_pll_f,
0383                 unsigned long xusbxti_f)
0384 {
0385     s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f;
0386     s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
0387     samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks,
0388                 ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks));
0389 }
0390
0391 /* Register s3c64xx clocks. */
0392 void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
0393                  unsigned long xusbxti_f, bool s3c6400,
0394                  void __iomem *base)
0395 {
0396     struct samsung_clk_provider *ctx;
0397     struct clk_hw **hws;
0398
0399     reg_base = base;
0400     is_s3c6400 = s3c6400;
0401
0402     if (np) {
0403         reg_base = of_iomap(np, 0);
0404         if (!reg_base)
0405             panic("%s: failed to map registers\n", __func__);
0406     }
0407
0408     ctx = samsung_clk_init(np, reg_base, NR_CLKS);
0409     hws = ctx->clk_data.hws;
0410
0411     /* Register external clocks. */
0412     if (!np)
0413         s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f);
0414
0415     /* Register PLLs. */
0416     samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
0417                 ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
0418
0419     /* Register common internal clocks. */
0420     samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,
0421                     ARRAY_SIZE(s3c64xx_fixed_rate_clks));
0422     samsung_clk_register_mux(ctx, s3c64xx_mux_clks,
0423                     ARRAY_SIZE(s3c64xx_mux_clks));
0424     samsung_clk_register_div(ctx, s3c64xx_div_clks,
0425                     ARRAY_SIZE(s3c64xx_div_clks));
0426     samsung_clk_register_gate(ctx, s3c64xx_gate_clks,
0427                     ARRAY_SIZE(s3c64xx_gate_clks));
0428
0429     /* Register SoC-specific clocks. */
0430     if (is_s3c6400) {
0431         samsung_clk_register_mux(ctx, s3c6400_mux_clks,
0432                     ARRAY_SIZE(s3c6400_mux_clks));
0433         samsung_clk_register_div(ctx, s3c6400_div_clks,
0434                     ARRAY_SIZE(s3c6400_div_clks));
0435         samsung_clk_register_gate(ctx, s3c6400_gate_clks,
0436                     ARRAY_SIZE(s3c6400_gate_clks));
0437         samsung_clk_register_alias(ctx, s3c6400_clock_aliases,
0438                     ARRAY_SIZE(s3c6400_clock_aliases));
0439     } else {
0440         samsung_clk_register_mux(ctx, s3c6410_mux_clks,
0441                     ARRAY_SIZE(s3c6410_mux_clks));
0442         samsung_clk_register_div(ctx, s3c6410_div_clks,
0443                     ARRAY_SIZE(s3c6410_div_clks));
0444         samsung_clk_register_gate(ctx, s3c6410_gate_clks,
0445                     ARRAY_SIZE(s3c6410_gate_clks));
0446         samsung_clk_register_alias(ctx, s3c6410_clock_aliases,
0447                     ARRAY_SIZE(s3c6410_clock_aliases));
0448     }
0449
0450     samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
0451                     ARRAY_SIZE(s3c64xx_clock_aliases));
0452
0453     samsung_clk_sleep_init(reg_base, s3c64xx_clk_regs,
0454                    ARRAY_SIZE(s3c64xx_clk_regs));
0455     if (!is_s3c6400)
0456         samsung_clk_sleep_init(reg_base, s3c6410_clk_regs,
0457                        ARRAY_SIZE(s3c6410_clk_regs));
0458
0459     samsung_clk_of_add_provider(np, ctx);
0460
0461     pr_info("%s clocks: apll = %lu, mpll = %lu\n"
0462         "\tepll = %lu, arm_clk = %lu\n",
0463         is_s3c6400 ? "S3C6400" : "S3C6410",
0464         clk_hw_get_rate(hws[MOUT_APLL]),
0465         clk_hw_get_rate(hws[MOUT_MPLL]),
0466         clk_hw_get_rate(hws[MOUT_EPLL]),
0467         clk_hw_get_rate(hws[ARMCLK]));
0468 }
0469
0470 static void __init s3c6400_clk_init(struct device_node *np)
0471 {
0472     s3c64xx_clk_init(np, 0, 0, true, NULL);
0473 }
0474 CLK_OF_DECLARE(s3c6400_clk, "samsung,s3c6400-clock", s3c6400_clk_init);
0475
0476 static void __init s3c6410_clk_init(struct device_node *np)
0477 {
0478     s3c64xx_clk_init(np, 0, 0, false, NULL);
0479 }
0480 CLK_OF_DECLARE(s3c6410_clk, "samsung,s3c6410-clock", s3c6410_clk_init);